JPH07210528A - Switch circuit - Google Patents

Abstract

PURPOSE:To improve the working rate of a switch by reducing the number of idle output ports by storing a message which is forcedly waited by contention arbitration in a FIFO buffer for temporarily storing it. CONSTITUTION:The message selected by switching selectors 14W-14Z is stored in output buffers 15W-15Z by a message contention arbitrating part 11 and transferred through lines L23W-L23Z to the input port of a processor or a switch at a following step. Lines L24W-L24Z are provided for a message transfer suppressing signal from the following step and while this signal is outputted, the message transfer to the following step is suppressed. In this case, a FIFO buffer 13 is provided and the message which is forcedly temporarily waited by the contention caused by transfer requests from the plural input ports to the same output port, can be fetched through a selector 12. Thus, the input port provided with the message waited by the contention is opened, and the next message can be transferred.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch circuit that constitutes a network for connecting parallel processors and the like composed of a large number of processors.

[0002]

2. Description of the Related Art In the field of scientific and technological calculation processing, parallel processors aiming to improve the performance by the number of unit processors by combining a large number of element processors are being commercialized. In parallel processors, it is important to use the inter-processor coupling method that connects a large number of processors. At present, this inter-processor coupling method is generally a multi-stage network in which a plurality of several m-input n-output switches (m and n are integers) are connected.

FIG. 4 shows a Benes network which is a typical multistage network. Of course, cube-type coupling such as lattice coupling and hypercube coupling, and tree coupling are also multi-stage networks in which a plurality of m-input n-output switches are connected. In the Benes network of FIG. 4, 16 processors are connected by connecting switches with 4 inputs and 4 outputs in three stages. Of these, the first one is a redundant switch, and by having such a redundant stage, a route for performing data transfer of all combinations in the network when the transfer destination processor does not overlap is secured without collision. can do.

In the following, data transfer between processors is called message transfer. A message is a message in which the destination processor number, the transfer data amount (message length), etc. are added to the transfer data as message information, and the message is actively used by using the message information in this message. The route is judged in each switch and the data to be sent is transferred to the destination processor.

FIG. 5 shows an example of the structure of a message. Message configuration information, such as the destination processor number and message length, is typically held in the first part of the message. The message is due to the physical number of signal lines,
It is sent in multiple batches. Therefore, a control signal indicating the validity of the data line is required every time each part is sent. Further, since the transfer destination information of a message is only at the beginning of the message, it is necessary to secure a route through which all the messages that have started to pass have passed.

Originally, large-scale scientific and technological calculation processing was considered as a target application of a parallel computer, but as non-numerical processing, the application range is in the field of knowledge processing such as inference processing and databases and online transaction processing. It is being expanded. Further, in such a field, unlike the large-scale scientific and technological calculation processing, it is considered that the amount of transfer data transferred at one time is not very long. In addition, recently, the distributed shared storage parallel computer that unifies the address space of the storage devices in all processors, which has been put to practical use, requires access to other processors more than ever, and this data access unit Is the line phase of the cache (several tens to several tens) from one data (several bytes unit).
Very small (0 byte unit).

On the other hand, looking at the hardware situation, LS
I Highly integrated, the number of gates per chip has increased dramatically. However, the number of signal pins is not as integrated as the number of gates, and the gate / pin ratio is increasing.

[0008]

In the Benes network, by providing a redundant switch, it is possible to secure a route for performing data transfer of all combinations in the network when the transfer destination processors do not overlap each other without collision. it can. However, except for the message transfer between static processors (that is, when the message transfer method is known in advance) in the fixed scientific calculation processing, it is not guaranteed that the transfer destination processors do not overlap. Have difficulty. Even if the transfer destination processors do not overlap, each processor operates independently (so-called MIMD type: Mu
ltiple Instruction Mutiple Data) In a parallel computer system, there is a difference in the processing progress of each processor. In such a case, inevitably there will be contention between the messages on the switches in the network, and the message transfer time will continue to increase.

For example, suppose there are a plurality of message transfers from the same input port to different destination processors in succession. If the first message gets waited as a result of contention arbitration with a message from another input port, the next message will request the next processor even if the output port connected to the destination processor is free. I can't send a message. This is especially true when transferring small units of data (ie short message lengths)
The transfer time greatly affects the performance.

An object of the present invention is to release an input port having a message waiting for contention even in such a case,
It is an object of the present invention to provide a switch that constitutes a multistage switch network that enables the transfer of the next message.

[0011]

In order to solve the above problems, a FIFO (First In First Out) buffer, which is larger than a message transfer unit, is provided in a switch on a network, and a message kept waiting due to contention is provided. Is temporarily saved in this FIFO buffer, thereby freeing the input port and allowing the next message to participate in the contention arbitration and be transferred.

[0012]

By providing the above FIFO buffer,
The input port can be released, and the transfer of the next message can be expedited. If the message temporarily saved in the FIFO has a higher priority and is used for the next selection, the message saved in the FIFO is not particularly waited for more than necessary.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an example of a switch configuration of the present invention.
In the figure, 10A to 10D are input buffers corresponding to the respective input ports, 11 is a message selection processing unit, 12 is a selector, 13 is a FIFO buffer adopted by the present invention,
14W to 14Z are selectors, and 15W to 15Z are output buffers corresponding to the respective output ports. Further, lines L20A to L20D are lines L21A to L21 for inputting a message from a switch or processor in the preceding stage.
21D is a message transmission inhibiting output signal that informs the switch or processor in the preceding stage that the input buffers 10A to 10D cannot store the message due to waiting of the message, and lines L23W to L23Z are the latter stage. The output of the message to the switch or processor, line L24W to line L24Z is a message transmission inhibiting signal from the switch or processor in the subsequent stage.

The input buffer 10A or 10D which receives the input message from the switch or processor in the preceding stage via the line L20A or the line L20D extracts the message configuration information such as the transfer destination processor number and the message length from the input message, and the line L22A. Alternatively, it is sent to the message selection processing unit 11 via the line L22D, and the message body is sent to the selector 14W or 1
Send to 4Z.

In FIG. 1, the input port 4 and the output port 4 are shown, but of course other numbers may be used. Furthermore, the number of input ports and the number of output ports may be different.

In the message contention arbitration unit 11, from the message transfer requests from a plurality of input ports, the selector 1 is output for each output port via the line L29W to the line L29Z.
By switching between 4W and 14Z, one input port having a message transfer request is selected. At the time of this selection, information on the use status of the output buffers 15W to 15Z corresponding to each output port (whether or not the output buffer can receive a message) is displayed on the lines L30W to L30Z.
Is sent to the message contention arbitration unit 11 via this, and this information is also used when selecting a message.

In the message contention arbitration unit 11, the selector 14
The message selected by switching W to 14Z is stored in the output buffer 15W to 15Z, and the line L23W
Through the line L23Z to the input port of the subsequent processor or switch. Lines L24W to L24Z are message transfer suppression signals from the subsequent stage,
When this signal is output, message transfer to the subsequent stage is suppressed.

This switch has a FIF used in the present invention.
The O-buffer 13 is provided, and a message that has been forced to wait due to contention due to transfer requests from a plurality of input ports to the same output port can be fetched through the selector 12. As control at this time, switching of the selector 12 from the message contention arbitration unit 11 via the (1) line L25, (2)
The instruction of the writing location to the FIFO buffer is sent from the line L26, and the instruction of (3) the reading location from the FIFO buffer is sent from the line L27.

The message as the output from the FIFO buffer 13 is sent to the selectors 14W to 14Z corresponding to the respective output ports via the line L28 and at the same time,
The transfer destination processor number information in the message is also sent to the message contention arbitration unit 11 and treated as one of the input port selection candidates for each output port in the message contention arbitration unit 11. At this time, the request from the FIFO should have the highest priority.

FIG. 2 shows the internal structure of the message contention arbitration unit 11. In the figure, 40 is an OR circuit, 41W to 41Z are output port compatible contention arbitration units, and 42 is a FIFO buffer control unit.

Output port competing arbitration units 41W to 4
1Z is a message contention arbitration unit corresponding to each output port. All of these competitive arbitration units have the same configuration. Inputs are input buffers 10A to 1
0D (FIG. 1) to request message transmission via line L22A to line L22D, and output buffers 15W to 1
It is the use status information of the output buffer from 5Z (FIG. 2) via line L30W to line L30Z. On the other hand, the outputs are the switching signals of the selectors 14W to 14Z (FIG. 1) via the lines L29W to L29Z and the input buffers 10A to 10D via the lines L19A to 19D.
(Fig. 1) is the response to the results of competitive mediation.

Contention arbitration units 41W to 1 corresponding to output ports
4Z uses the FIFO buffer as an input having a fifth high priority, as described later, and (1) the FIFO buffer control unit 42.
Receiving message information on the FIFO buffer from the FIFO buffer, and (2) transferring message information relating to an input port having a message transfer request that has lost the contention arbitration to the FIFO buffer control unit 42. Since it can be used as it is,
No detailed description is given here.

Next, the FIFO buffer controller 42 will be described. The FIFO buffer control unit 42 uses the FIFO
The buffer 13 (FIG. 1) is controlled.

The input is a contention arbitration unit 41 corresponding to each output port.
As message information from W to 41Z, line L50
A request to store a message in the FIFO buffer is sent via W or line 50Z, and an input port number of a transmission source that makes a message store request is sent via line L52W or line 52Z. The end information and the valid information of the message are sent via the lines L53W and 53Z, respectively.

Based on these pieces of information, the FIFO buffer control unit 42 determines the message to be fetched, and the line L2
5, the selector 12 (FIG. 1) is switched to the input from the corresponding input buffer 10A or 10D, and the line L
The location to be written in the FIFO buffer 13 (FIG. 1) is set via 26.

Further, the FIFO buffer control unit 42 is
In order to send out the message stored in the FIFO buffer 13 (FIG. 1), the transfer destination processor number as the message information in the message is fetched through the line L28, and the output port corresponding contention is performed through the line L55W or the line L55Z. The arbitration unit 41W to 41Z is requested to arbitrate, the result is received by the line L54W to the line L54Z, and accordingly, the place to be read out of the FIFO buffer 13 (FIG. 1) is instructed via the line L27. To do.

The detailed structure and operation of the FIFO buffer controller will be described with reference to FIG. In FIG. 3, 50 is a contention arbitration unit, 51 and 52 are registers for holding states, 53 and
54 is a selector, 55 is an AND circuit, 56 is a write pointer WP of the FIFO buffer, 57 is a read point RP of the FIFO buffer, 58 is an OR circuit, and 59 is FI.
A free area calculation unit of the FO buffer, and 60 is a request signal generation unit.

First, the fetching of a message into the FIFO buffer 13 (FIG. 1) in response to a request from the output port corresponding contention arbitration unit 41W to 41Z (FIG. 2) will be described. Output port compatible contention arbitration unit 41W to 41Z
As the message information from (FIG. 2), a message storage request to the FIFO buffer is input via line L50W to line 50Z, and an input port number of a transmission source which makes a message storage request is input via line L51W to line L51Z. And sent to the competition arbitration unit 50. The contention arbitration unit 50 selects one from the requested input ports. At this time, the FIFO buffer is
Since the buffer capacity must not overflow, the FIFO is one of the criteria for input port selection during contention arbitration.
Buffer free area information is read from the FIFO buffer free area calculation unit 59 described later. The other operations of the contention arbitration unit 50 are the same as those of the normal contention arbitration, and are omitted here.

The result of the competitive arbitration is as follows.
The fact that there is a message to be written in the buffer 13 (FIG. 1) is sent to the registers 51 to 52 via the line L71. The register 51 also stores the newly selected input port number via the line L70 according to the instruction on the line L71. The information in the register 51 is sent to the selector 12 via the line L25. Another register 52
Indicates the status of whether or not the data is currently being read into the FIFO buffer 13 (FIG. 1).

The SET of the register 52 (start of reading into the FIFO buffer) is performed through the line L71,
RESET (end of reading into the FIFO buffer)
Output port compatible contention arbitration units 41W to 41Z (FIG. 2)
This is performed by using the information selected by the selector 53 from the message end instruction, which is one of the message information sent from the lines L52W to L52Z.

The writing location of the FIFO buffer 13 (FIG. 1) is set as follows. Lines L53W to L5 from the output port compatible contention arbitration units 41W to 41Z (FIG. 2)
The FIFO buffer confirms that the information selected by the selector 54 from the valid information of the message, which is one of the message information sent via the 3Z, is currently being read into the FIFO buffer while confirming that the information is being read into the FIFO buffer. To the write pointer WP56. In the WP 56, the value of the held WP is incremented by 1 (the transfer unit in one cycle of the message is set to 1), and the result is sent to the FIFO buffer 13 (FIG. 1) via the line L26.

Next, the messages stored in the FIFO buffer 13 (FIG. 1) are output to the output buffers 15W to 1W.
The process for sending to 5Z (FIG. 1) will be described.
First, the transfer destination processor number as message information is fetched from the message stored in the FIFO buffer 13 (FIG. 1) via the line L28, and the request signal generation unit 6
Send to 0. The request signal generator 60 uses the free area calculator 59 of the FIFO buffer to cause the FIFO buffer 13 to operate.
It is confirmed that the message is stored on (FIG. 1), and via line L55W to line L55Z, to the output port compatible contention arbitration unit 41W to 41Z (FIG. 2),
Request mediation. In the output port compatible contention arbitration units 41W to 41Z (FIG. 2), the message in the FIFO buffer is treated in the same manner as the message in each input buffer.
The priority at the time of contention should be higher in the FIFO buffer.

This arbitration result is the result of lines L54W to L5.
It is received by 4Z and sent to the read pointer RP57 of the FIFO buffer via the OR circuit 58. RP5
7 increments the value of the held RP by 1 (the transfer unit in one cycle of the message is 1), and the result is the line L27.
Through the FIFO buffer 13 (FIG. 1).

Calculating section 58 of the free area of the FIFO buffer
Is a write pointer WP56 and a read pointer RP
57 as an input, on the FIFO buffer 13 (FIG. 1),
It calculates whether the message is stored or how much room is left for the message to be stored next, and sends the results to the request signal generation unit 60 and the contention arbitration unit 50, respectively.

The FIFO buffer of the present invention has one FI.
Although the FO configuration is adopted, it is also possible to prepare a plurality of FIFOs. Furthermore, by installing this FIFO for output ports, one output port can simultaneously receive a plurality of messages from a plurality of input ports. The larger the capacity of the FIFO, the more effective it is. These are the LSs that make up the switch
I or the gate size of the LSI group.

[0036]

According to the present invention, a FIF for temporarily storing a message forced to wait due to contention arbitration.
By storing in the O buffer, the input port can be released, and the next message can be the target of contention arbitration. Therefore, it is possible to reduce the number of vacant output ports and increase the operating rate of the switch.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a switch.

FIG. 2 is a block diagram showing an embodiment of a message arbitration control unit.

FIG. 3 is a block diagram showing an embodiment of a FIFO buffer control unit.

FIG. 4 is a block diagram showing an embodiment of a network between processors of a parallel computer.

FIG. 5 is an explanatory diagram showing an example of a message structure.

[Explanation of symbols]

50 ... competitive arbitration unit, 51, 52 ... registers, 53, 54
... selector, 55 ... AND circuit, 56 ... write pointer WP, 57 ... read pointer RP, 58 ... OR circuit, 59 ... FIFO buffer free area calculation section, 60 ... request signal generation section.

Claims (4)

[Claims] 1. With m inputs and n outputs used for data transfer, contention arbitration between transfer data from each input port is performed corresponding to an output port, and the transfer data not selected due to contention of the output port is output as the output. In a data transfer switch that performs control to wait until a port becomes free, having a buffer that temporarily holds the transfer data that has not been selected due to competition of the output ports, and releasing the input port that has sent the transfer data Switch circuit characterized by. 2. The message on the buffer according to claim 1, wherein the message on the buffer is m + 1 for contention arbitration of the output port when the transfer data is temporarily held on the buffer.
Switch circuit treated as the second input. 3. The switch circuit according to claim 2, wherein the contention arbitration of the output port when the transfer data is temporarily held in the buffer increases the priority of the message in the buffer. 4. The switch circuit according to claim 1, wherein the buffer is made larger than the size of the transfer data.