JPH07210505A - Bus arbitrating system - Google Patents

Abstract

PURPOSE:To eliminate a bus starvation and to equalize the bus use rate of plural processors at a system for which the plural processors are constructed by a serial arbitrating system. CONSTITUTION:Inside each processor, a bus request possessing circuit 503 for possessing the right of bus use is provided with a bus request suppressing circuit 601, and a bus request signal A on a bus is monitored. When the bus request from the other processor is existent, the bus requests to be generated from the present processor are suppressed to fixed frequency, and the opportunity of bus use is applied to the processor in the downstream rather than the present processor. The bus request suppressing circuit 601 counts the number of bus cycles after a bus cycle, in which the present processor uses the bus, by using a counter 604 and corresponding to this count value, it is decided whether the bus request is outputted to a bus request suppressing pattern extraction circuit (memory) 606 or not. Then, a bus request output circuit 607 outputs a bus request signal according to this signal and a bus busy signal on the bus or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for constructing a microcomputer system, and more particularly to a bus arbitration system for constructing a multi-processor system using a plurality of processors.

[0002]

2. Description of the Related Art In a multi-processor system using a plurality of processors, the process of determining which processor uses a system bus that is unique in the system is called arbitration process.

Two types of arbitration processing, a parallel arbitration method and a serial arbitration method, are widely known. Usually, either one of them or a combination of both is used.

The parallel arbitration method further includes a central arbitration method and a distributed arbitration method. Here, the central arbitration method will be described.

FIG. 3 shows a centralized parallel arbitration method. In the figure, 101 is a system bus. An arbiter circuit 102 controls the arbitration operation. 103 to 106 are processors.

Reference numerals 103a to 106a are bus request signals for each processor to request the use of the bus. Reference numerals 103b to 106b are bus permission (grant) signals which are the result of arbitration by the arbiter circuit. 10
7 is a busy signal indicating that one of the processors is using the bus.

As described above, in the case of the parallel arbitration method, there are as many bus request levels (signals) as there are processors, and arbitration between these levels is performed by the arbiter circuit.

The processors requesting to use the bus assert the bus request signals 103a to 106a possessed by the processors. All of these signals are arbiter circuit 102.
The arbiter circuit performs arbitration processing according to a predetermined priority (priority) determination rule, and gives a bus permission signal (any one of 103b to 106b) to any one of the processors. .

As a result, the processor given the bus permission signal can use the bus in the next cycle. The processor given the bus grant signal monitors the busy signal, and when it is negated, the bus can be used. At the same time when the bus starts to be used, this processor asserts the busy signal.

On the other hand, FIG. 4 shows a serial arbitration method. In the figure, 201 is a system bus. 202 is an arbiter circuit. 203 to 206 are processors.

Reference numerals 203a to 206a are bus request signals for each processor to request the use of the bus. 203b to 206b are bus grant (grant) input signals. Furthermore, in this case, bus output signals (grant) 203c to 206c are provided. 207
Is a busy signal.

As shown in the figure, in the case of the serial arbitration method, a plurality of processors output a bus request signal to the same bus request line. Therefore, the level of the bus request becomes single, and the arbiter circuit 202 returns the bus request signal or the bus grant signal 2 to the processor.
03b is always asserted.

The processors requesting the bus assert their own bus request signals 203a to 206a. These signals are wired-ORed to 1
Book bus request.

As described above, the bus permission signal 203b is
Since the bus request is looped back or is always asserted, the bus can be used in the next cycle whenever the processor 203 issues the bus request in this system. Bus usage can begin once the busy signal is negated.

When the processor 204 or later requests the bus, the processor 203 transmits the level of the bus grant signal input 203b to the bus grant signal output 203c when the processor 203 does not have the bus request. Similarly, each processor asserts the bus grant output signal when the bus grant signal input becomes active when it does not output the bus request.

The bus enable signal is sequentially transmitted in accordance with such a rule, but when the processor issuing the bus use request receives this enable signal, the bus can be used in the next cycle.

When the processor asserts the bus request signal and receives the bus grant signal, it monitors the busy signal, and when it is negated, the bus can be used. This processor asserts a busy signal at the same time when the bus starts to be used.

The signal transmission system of this permission signal is generally called a daisy chain system. According to this method,
A processor with a certain number is given the right to use the bus only when all the processors with a number lower than itself have not requested the bus.

In other words, in this system, the most upstream processor (203 in the figure) of the daisy chain circuit has the highest priority, and the further downstream the daisy chain, the lower the priority.

As described above, in the serial arbitration method, the arbiter circuit is not actually necessary, and the bus request signal may be folded back or the level may be fixed, so that the multiprocessor system is very simple and inexpensive. The feature is that can be constructed.

However, in this system, a system called a daisy chain of bus permission signals is used, so that a signal delay occurs in the daisy chain circuit of each processor, and arbitration does not end until this is transmitted to the final processor. Therefore, arbitration time is required in proportion to the number of processors, which is not suitable for a large-scale system with many processors. This is effective for a system with 1 to 4 processors.

On the other hand, in the case of the parallel arbitration system, the centralized arbiter circuit makes the priority judgment at once, so that the arbitration time is not so much influenced by the number of processors and can be carried out in a substantially constant time. it can.

However, the parallel arbitration method requires a complicated arbiter circuit in addition to each processor, and a dedicated bus wiring is required between each processor and the arbiter circuit. Since then, the number of processors has been limited. Generally, this method is suitable for a medium-scale multi-processor system (the number of processors is 2 to 8).

In the case of a large-scale system having more processors, a combination of the serial arbitration method and the parallel arbitration method described above is used to daisy-chain the bus permission signals of each priority level arbitrated by the parallel arbitration, and connect them in series. There is also an example in which the number of processors x the number of parallel levels are connected.

[0025]

[Problems to be Solved by the Invention] Multiprocessor
Among the arbitration processing methods for constructing a system, the serial arbitration method is an effective means because it can be realized at a low price when constructing a relatively small-scale system as described above.

In a large-scale system, the parallel arbitration method is generally used in combination, which is a highly important method.

However, in the case of this serial arbitration method, when a high-priority processor continuously uses the bus, a "bus starvation state" may occur in which the low-priority processor cannot use the bus forever. Have sex

For this reason, each processor normally operates in the "every time bus release mode" in which the bus is released every time a bus cycle is executed in order to avoid continuous use of the bus. However, even if this method is used, if the processor with the highest priority and the processor with the next highest priority continue to use the bus, this
Only one processor can use the bus alternately, and the third and subsequent processors cannot use the bus forever, resulting in a bus time-out state.

This situation will be described with reference to the system configuration diagram of FIG. 5 and the time chart of FIG.

In FIG. 5, 301 is a system bus.
302 is an arbiter circuit. 303 to 306 are processors P
1 to Pn.

Reference numeral 307 is a busy signal BUS / BUSY. Three
13 to 316 are daisy chain circuits of bus grant (grant) signals in each processor. Reference numerals 323 to 326 are bus timer circuits that monitor the time until the bus right is acquired in each processor.

Reference numerals 303a to 306a denote bus request signals P for each processor to request the use of the bus.
1-BRQ to Pn-BRQ, and the bus request on the wired / ORed bus is BUS-BRQ.

Reference numerals 303b to 306b are bus grant (grant) input signals P1-BGIN to Pn-BGIN. 303
c to 306c are bus permission (grant) output signals P1-B
GOUT to Pn-BGOUT.

Reference numerals 303d to 306d denote bus time-out signals P1-TOUT to Pn-T generated when the bus timer on each processor detects an abnormally long wait state.
It is OUT.

In the time chart shown in FIG. 6, 3
A case where the processors P1 to P3 are trying to continuously use the bus on the conventional serial arbitration type bus is shown. The signal names correspond to those in FIG. 5, and all signals are significant at the “L” level.

In this example, the processor P1 (303) and the processor P2 (304) open the bus each time, but since they have internal requests to constantly use the bus,
Alternately using the bus, processor P3 (30
5) shows that the bus time out is detected without being able to use the bus forever.

The operation will be described below in the order of the numbers added to the time chart.

1. The respective bus request circuits of the processors P1 to P3 simultaneously transmit the internal bus requests P1-INTBRQ to
Accept P3-INTBRQ. It is assumed that the grant input P1-BGIN of the processor P1 is always asserted at the L level.

2. The bus request circuits of P1 to P3 are respectively P1-BRQ to P3-BR according to the internal bus request.
Assert Q. Here, the bus / timer circuits 323 to 325 of the respective processors are activated to start the time counting operation.

3. Since P1-BGIN is asserted, P1 gets the bus.

4. P1 asserts the busy signals BUS and BUSY to notify the bus use state.

5. The bus request circuit of P1 is BUS
After the BUSY signal is asserted, the P1-BRQ signal is negated after a fixed time t _BRQN .

6. This asserts P1-BGOUT.

7. P1-BGOUT (B2-BGIN)
Is asserted, the processor P2 acquires the right to use the next bus.

8. P1 has finished using the bus and
After negating BUSY, P2 asserts BUS BUSY to start using the bus.

9. P1 asserts the P1-BRQ signal to request the use of the next bus.

10. Bus request circuit of P2 is BUS
After the BUSY signal is asserted, the P2-BRQ signal is negated after a fixed time t _BRQN .

11. Since P1-BGIN is in the asserted state, P1 acquires the right to use the next bus.

12. P2 finishes using the bus, BUS
・ P1 is BUS ・ BUSY after negating BUSY
To start using the bus.

13. The bus request circuit of P1 is BU
After asserting the S-BUSY signal, the P1-BRQ signal is negated after a fixed time t _BRQN .

14. This asserts P1-BGOUT.

15. P1-BGOUT (B2-BGI
By asserting N), the processor P2 acquires the right to use the next bus.

16. P1 finishes using the bus, BUS
・ After negating BUSY, P2 is BUS ・ BUSY
To start using the bus.

The above processes (9) to (16) are repeated.

17. P3 cannot acquire the right to use the bus forever and continues to assert P3-BRQ.

18. After a lapse of a certain time, the bus timer circuit of P3 times up and asserts P3-BTOUT.

The bus time-out in the processor is treated as a fatal abnormality and is a factor for stopping the operation of the system. Therefore, in order to prevent such "bus starvation" from occurring, the system designer should limit the number of processors used and make sure that continuous bus usage does not occur in the processor with high priority in the application of the processor. I had to do it.

However, the avoidance of the "bus starvation state" is a multi-task for real-time processing in which each processor independently processes a plurality of events that occur asynchronously.
It was a very difficult task for processor systems.

FIG. 7 shows an actual circuit example of each processor having the conventional serial arbitration method.

In the figure, 501 is the whole of one of the processors. 502 is a general circuit of the processor. A bus request acquisition circuit 503 acquires a right to use the bus in response to a request from a general circuit of the processor.

Reference numerals 504 and 505 denote output buffer circuits. Fifty
6 is an input buffer circuit. NAND circuits 507 and 510 have inverted inputs. Reference numeral 509 is an inversion circuit.

Reference numeral 508 is a bus timer circuit for monitoring the time from the processor requesting the bus to the acquisition and use of the bus.

Signals A to E are signals on the bus, and A is a "BUS-BRQ" signal indicating a bus request. B is a "BUS / BUSY" signal indicating that the bus is in use. C is a bus permission input "Pn-BGIN" signal. D is a bus permission signal "Pn-B
GOUT "signal. E is a "Pn-BTOUT" signal for notifying the bus acquisition abnormality to the outside.

Next, the circuit operation of FIG. 7 will be described. It is assumed that the processors shown in the figure are connected as shown in FIG.

First, when the general circuit 502 of the processor gives a request to use the bus to the bus request acquisition circuit 503,
503 asserts the bus request signal 503a. Then, the external bus signal A (BUS-
BRQ) is driven.

The bus grant signal by the arbiter circuit 302 on the system is given to this processor as the bus signal C. When the signal C becomes active, 503a
Inverted NAND because the signal is also active
The circuit asserts the 507a signal. This is the "bus acquisition signal".

When this signal becomes active and is monitored via the input buffer circuit 506, "BU
When the "S.BUSY" signal is inactive, the general circuitry of the processor can use the bus.

When actually using the bus,
The 03b signal is activated and the buffer 505 asserts the "BUS.BUSY" signal to inform the other processors that the bus is busy.

In the 510 circuit portion, the C signal side is active, but since the 503a signal is inverted and applied by the 509 circuit, the output remains negated. Therefore, the "bus grant output" of the bus signal does not become active.

On the other hand, when this processor is not requesting the bus (the 503a signal is inactive) and the bus permission signal C becomes active, both inputs of the 510 circuit become active, so that the bus signal becomes active. D (P
n-BGOUT) is asserted. As a result, the bus grant is given to a processor having a lower priority than this processor. The circuits 509 and 510 are daisy chain circuits.

The bus timer circuit 508 starts the timing operation when the 503a signal becomes active and issues a bus request, and stops this operation when the 503b signal becomes active and declares use of the bus. If the timekeeping operation is not stopped within a predetermined time, the signal E (Pn-BTOUT) on the bus is driven to notify the abnormality to the outside.

An object of the present invention is to provide a bus arbitration method which eliminates the bus starvation state in a system in which a plurality of processors are constructed by the serial arbitration method.

Another object of the present invention is to provide a bus arbitration method that equalizes the bus usage rates of a plurality of processors.

[0074]

In order to solve the above problems, the present invention provides a multiprocessor system in which one of a plurality of processors is given a right to use a bus by using a daisy chain of a bus grant signal. A bus request suppression circuit is provided in each processor, and the bus request suppression circuit is
It is provided with means for determining whether or not a bus use request signal from another processor is present on the bus, and suppressing the bus use request signal generated from the self processor to a certain frequency when there is a bus use request. Characterize.

Further, the bus request suppression circuit counts the number of bus cycles after the bus cycle in which the bus is used by itself, and determines whether or not to issue a bus request depending on the output condition of this counter. Bus request suppression pattern extraction means for judging by suppression frequency, output state of the bus request suppression pattern extraction means, own bus request signal is asserted, bus busy signal on bus is asserted, and fixed time A bus request output circuit for outputting a bus request signal when the time elapses, and a bus request signal from the self processor is not asserted and the bus request output condition of the bus request suppression pattern extracting means is not asserted, and a bus request signal on the bus A counter that counts up the counter when is asserted and the bus busy signal is asserted. Whether the bus request from the self-processor and the bus request output condition of the bus request suppression pattern extracting means are asserted and the bus busy signal on the bus is asserted Or a count / clear condition generation circuit for clearing the counter when the bus request signal on the bus is not asserted.

[0076]

When the bus use request signal from another processor exists on the bus, the bus use request signal generated from the self processor is suppressed to a certain frequency so that the bus is physically located downstream of the daisy chain. It gives the processor an opportunity to use the bus and eliminates the bus request starvation state of the downstream processor.

Counting up and counting the counter
Set the serial arbitration method by monitoring the clear condition and the bus request output condition for the bus request signal and busy signal status on the bus, the bus use request inside the processor, and the output condition of the bus request suppression pattern extraction circuit. However, a uniform bus usage rate equivalent to the round robin method of parallel arbitration method is obtained.

[0078]

1 is a bus request suppressing circuit diagram on a processor board showing an embodiment of the present invention. The figure shows a circuit portion mounted on a single processor board, but the serial arbitration method of the present invention is realized by using a plurality of processor boards respectively mounted with this circuit. In this case, the system construction method is the same serial arbitration method as in FIG.

In FIG. 1, elements indicated by numerals in the 500s have the same contents as those in FIG.

Reference numeral 601 denotes the entire bus request suppressing circuit for realizing the serial arbitration method. This constitutes a part of the bus request acquisition circuit 503 shown in FIG.

Reference numeral 602 is a count-up condition creating circuit.
Reference numeral 602a is a count-up condition pulse signal of the counter. Reference numeral 603 is a counter clear condition generation circuit. 603a
Is a counter clear condition pulse signal. Reference numeral 604 denotes a counter circuit, which shows a case where a count-up condition and a clear condition are input and the count-up is performed by a synchronous clock. A signal group 604a indicates a counter value.

Reference numeral 605 is a setting circuit for setting by hardware. Reference numeral 605a is a set condition signal group. 606 is the count value shown in 604a and 605a
It is a bus request suppression pattern extraction circuit for extracting and outputting a unique value from the setting condition shown in (1), which is realized by a ROM (Read Only Memory). Here, it is called a bus request suppression pattern extraction circuit. An output signal 606a is a signal indicating whether or not the bus request signal can be output.

The circuit 606 includes not only ROM but also RAM.
Although it can be realized by a (random access memory), in this case, a data writing circuit by software is required instead of the circuit 605.

Reference numeral 607 denotes a bus request output circuit,
This circuit sets or clears the bus request signal depending on the state of the a signal, the presence / absence of an internal bus request, and the bus busy state. Reference numeral 607a is a bus request signal of this processor board, which is equivalent to the signal 503a in FIG.

Reference numeral 608 denotes a bus request signal BUS-B on the bus.
Buffer for inputting RQ. Reference numeral 608a is the input signal.

Signals A to D are signals on the bus, and A is a BUS-BRQ signal indicating a bus request. B is a BUS-BUSY signal indicating that the bus is in use. C is a bus permission input Pn-BG
IN signal. D is a bus permission signal Pn-BGOUT signal.

The signal F indicates the bus request signal Pn-INTBRQ from the internal processor. The signal G is a clock signal for synchronization. The presence or absence of this signal, the frequency, etc. do not matter in particular.

Next, the operating conditions of the circuit shown in FIG. 1 will be described.

The count-up condition generating circuit 602 generates a condition signal for the counter circuit 604 to count up (synchronize with the synchronous clock). count·
The conditions for generating the up signal are as follows.

(1) The internal bus request Pn-INTBRQ is asserted.

(2) The request output condition 606a of its own is not asserted.

(3) The bus request signal input 608a on the bus is asserted.

(4) The bus busy signal 506a on the bus is asserted.

When the above conditions are satisfied, the signal 602a is asserted and the counter value of 604 is incremented by one.

Next, the counter clear condition generating circuit 60
3 generates a condition signal for clearing the counter circuit 604 (synchronizing with the synchronous clock G).

The conditions for generating the counter clear signal are as follows.

(1) The internal bus request Pn-INTBRQ is not asserted.

Or (2) The own request output condition 606a is asserted.

And (3) The bus busy signal on the bus is asserted.

Or (4) The bus request signal input 608a on the bus is not asserted.

When the above conditions are satisfied, the signal 603a is asserted and the counter value of the counter circuit 604 becomes 0.
Will be cleared.

The counter circuit 604 performs a count-up / clear operation according to the count-up condition by the signal 602a and the clear condition of 603a, and outputs the count value as 604a.

Reference numeral 606 is a bus request suppression pattern extraction circuit for extracting and outputting a unique value from the count value indicated by 604a, which has a memory circuit configuration realized by ROM or RAM.

As the data contents of the circuit 606, a predetermined value is written when it is realized by a ROM.
It is necessary to add a hardware setting circuit such as 605 to select one of them. In addition, when it is realized by RAM, it is also possible to directly write the data by software. In this case, instead of the 605 circuit, a writing circuit for writing data by software is required.

The data to be written in the bus request suppression pattern extraction circuit 606 is as shown in Table 1.

[0106]

[Table 1]

The contents set by the setting circuit 605 will be referred to as bus request suppression frequencies. This bus request suppression frequency is because there are other processors that request the bus,
It is a value that sets how many bus cycles each bus request can be issued when the bus requests are continuously generated.

The larger this value is, the higher the degree of suppression of bus use is, and the degree of even use of the bus is increased in the system in which many processors are mounted.

As can be seen from Table 1, when the degree of suppression is N, the output of 606a is 1 (high level) when the counter value is 0 to (N-2), and the output is -1 when the count value is N-1. It is defined to be 0 (low level).

In this way, the bus request output enable signal 606a of its own is asserted only when the count values of 604a are aligned with respect to the bus request suppression pattern extraction circuit 606 in which the data is written.

The bus request output circuit 607 receives BUS-BR on the bus under the condition of the bus request output enable signal 606a.
It is a circuit for outputting a Q signal and negating it at a necessary timing.

This is not a circuit peculiar to this embodiment, but is also mounted on a conventional circuit of the serial arbitration system.
However, in order to realize the arbitration method according to the present invention, it is necessary to negate the bus request signal 607a under the following conditions.

(1) The bus request signal 607a of its own is asserted.

And (2) The bus busy signal B on the bus is asserted.

(3) The fixed time t _BRQN has elapsed.

Here, the constant time t _BRQN is set to a value sufficiently larger than the time when the bus request output circuit 607 asserts the bus request signal Pn-BRQ by asserting the bus busy.

Next, the operation of a system using a plurality of processor boards each having the circuit shown in FIG. 1 will be described.

FIG. 2 shows an operation example in a system using the bus request suppression circuit shown in FIG. Here, it is shown that the three processors on the bus adopting the serial arbitration method by the daisy chain of the bus grant are respectively provided with the bus request suppressing circuit according to the present embodiment and are arbitrating and using the bus. . The bus request suppression circuit has a suppression frequency of 3 for all three processors (one request every three cycles).

The respective processor numbers are designated as P1 to P3.
The signal name shown in FIG. 1 is added after the processor number for description.

The operation will be described below in the order of the numbers in the time chart.

1. The respective bus request suppressing circuits of the processors P1 to P3 simultaneously generate the internal bus request P1-INTBR
Accepts Q to P3-INTBRQ. Processor P1
It is assumed that the grant input P1-BGIN of is always asserted at the L level.

2. Since the processors P1 to P3 have not asserted the bus requests P1-BRQ to P3-BRQ so far and the bus request signal BUS-BRQ on the bus is in the negated state, the bus request suppression circuits of the processors P1 to P3 are According to the internal bus request, P1-BRQ ~
Assert P3-BRQ. In this state, the count values of each bus request suppression circuit are all zero.

3. The bus grant input P1-BGIN is asserted so that the processor P1 acquires the bus.

4. The processor P1 uses the busy signal BUS-
Busy is asserted to notify the bus usage state.

5. The bus request suppression circuit of the processor P1 negates the P1-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

6. As a result, the bus permission output P1-B
GOUT is asserted.

7. P1-BGOUT (P2-BGIN)
Is asserted by the processor P2 to acquire the right to use the bus.

8. After the processor P1 finishes using the bus and negates BUS-BUSY, the processor P1
2 asserts BUS-BUSY to start using the bus.

9. The bus request suppression circuit of the processor P2 negates the P2-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

By asserting the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which monitors this becomes 1. It remains at 0 for processors P2 and P3.

10. This asserts P2-BGOUT.

11. P2-BGOUT (P3-BGI
By asserting N), the processor P3 acquires the right to use the bus.

12. After the processor P2 finishes using the bus and negates BUS-BUSY, the processor P2
3 asserts BUS-BUSY to start using the bus.

By asserting the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which is monitoring it becomes 2, and the count value of the processor P2 becomes 1. That of processor P3 remains zero.

13. Since the counter value of the processor P1 becomes 2, the processor P1 can issue the next bus request in accordance with the internal bus request, and P1-
Assert BRQ.

14. The bus request suppression circuit of the processor P3 negates the P3-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

15. By asserting P1-BRQ, P1-BGOUT and P2-BGOUT are sequentially negated.

16. Since P1-BGIN is in the asserted state, the processor P1 acquires the right to use the bus.

17. After the processor P3 finishes using the bus and negates BUS-BUSY, the processor P3
1 asserts BUS-BUSY to start using the bus.

By asserting the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which is monitoring this becomes 0, and that of the processor P2 becomes 2. That of the processor P3 is 1.

18. Since the counter value of the processor P2 becomes 2, the processor P2 can issue the next bus request according to the internal bus request, and P2-
Assert BRQ.

19. The bus request suppression circuit of the processor P1 negates the P1-BRQ signal after a predetermined time t _BRQN after asserting the BUS-BUSY signal by itself.

20. P1-BGOUT is asserted due to P1-BRQ being negated.

21. P1-BGOUT (P2-BGI
By asserting N), the processor P2 acquires the right to use the bus.

22. After the processor P1 finishes using the bus and negates BUS-BUSY, the processor P1
2 asserts BUS-BUSY to start using the bus.

By asserting the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which is monitoring it is 1, that of the processor P2 is 0, and that of the processor P3 is 2.

23. Since the counter value of the processor P3 becomes 2, the processor P3 can issue the next bus request according to the internal bus request, and P3-
Assert BRQ.

24. The bus request suppression circuit of the processor P2 negates the P2-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

25. P2-BGOUT is asserted due to P2-BRQ being negated.

26. P2-BGOUT (P3-BGI
By asserting N), the processor P3 acquires the right to use the bus.

27. After the processor P2 finishes using the bus and negates BUS-BUSY, the processor P2
3 asserts BUS-BUSY to start using the bus.

By asserting the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which is monitoring it is 2, that of the processor P2 is 1, and that of the processor P3 is 0.

28. Since the counter value of the processor P1 becomes 2, the processor P1 can issue the next bus request in accordance with the internal bus request, and P1-
Assert BRQ.

29. The bus request suppression circuit of the processor P3 negates the P3-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

Consider a case where the internal bus request of the processor P3 is eliminated by this bus access and P3-INTBRQ is negated.

30. By asserting P1-BRQ, P1-BGOUT and P2-BGOUT are sequentially negated.

31. Since P1-BGIN is in the asserted state, the processor P1 acquires the right to use the bus.

32. After the processor P3 finishes using the bus and negates BUS-BUSY, the processor P3
1 asserts BUS-BUSY to start using the bus.

By asserting the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which is monitoring it is 0, that of the processor P2 is 2, and that of the processor P3 is 0.

33. Since the counter value of the processor P2 becomes 2, the processor P2 can issue the next bus request according to the internal bus request, and P2-
Assert BRQ.

34. The bus request suppression circuit of the processor P1 negates the P1-BRQ signal after a predetermined time t _BRQN after asserting the BUS-BUSY signal by itself.

35. P1-BGOUT is asserted due to P1-BRQ being negated.

36. P1-BGOUT (P2-BGI
Since N) is in the asserted state, the processor P2 acquires the right to use the bus.

37. After the processor P1 finishes using the bus and negates BUS-BUSY, the processor P1
2 asserts BUS-BUSY to start using the bus.

By the assertion of the BUS-BUSY signal, the count value of the bus request suppression circuit of the processor P1 which monitors it is 1, the processor P2 has 0, and the processor P3 has 0.

38. The bus request suppression circuit of the processor P2 negates the P2-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

At this point in time, there is no other processor that outputs a bus request, so the bus request signal B on the bus is output.
US-BRQ is negated once.

39. When the bus request suppression circuit of the processors P1 and P2 monitoring the BUS-BRQ detects the negation of this signal, it outputs the bus request regardless of the value of the bus request suppression counter. P1-BRQ and P2-BRQ
Is asserted.

40. Since P1-BGIN is in the asserted state, the processor P1 acquires the right to use the bus.

41. After the processor P2 finishes using the bus and negates BUS-BUSY, the processor P2
1 asserts BUS-BUSY to start using the bus.

The count value of the bus request suppression circuit of the processor P1 which is monitoring this by asserting the BUS-BUSY signal is 0, 0 because the processor P2 has already issued a request, and 0 because the processor P3 has no request.
Becomes

42. The bus request suppression circuit of the processor P1 negates the P1-BRQ signal after a predetermined time t _BRQN after asserting the BUS-BUSY signal by itself. P
P1-BGO by negating 1-BRQ
UT is asserted.

43. P1-BGOUT (P2-BGI
Since N) is in the asserted state, the processor P2 acquires the right to use the bus.

44. After the processor P1 finishes using the bus and negates BUS-BUSY, the processor P1
2 asserts BUS-BUSY to start using the bus.

The count value of the bus request suppression circuit of the processor P1 which monitors this by asserting the BUS-BUSY signal is 1, and that of the processors P2 and P3 remains 0.

45. The bus request suppression circuit of the processor P2 negates the P2-BRQ signal after a certain time t _BRQN after asserting the BUS-BUSY signal by itself.

At this point in time, there is no other processor that outputs a bus request, so the bus request signal B on the bus is output.
US-BRQ is negated once.

46. When the bus request suppression circuit of the processors P1 and P2 monitoring the BUS-BRQ detects the negation of this signal, it outputs the bus request regardless of the value of the bus request suppression counter. P1-BRQ and P2-BRQ
Is asserted.

Hereinafter, the above-mentioned No. 41 and after will be repeated.

(1) As is apparent from the above description, in the present embodiment, the processor P3 can use the bus from the time point of number 12, but in the conventional method (FIG. 6), the processor P1 again uses the bus. Since they are used, the processors P1 and P2 alternately use the buses and the processor P
3 is permanently starved.

That is, in the present embodiment, in a system in which a bus is constantly requested by any of the processors, in order to avoid that only two processors upstream in the daisy chain continue to use the bus, Bus request signal B issued by each processor from another processor
By monitoring the US-BRQ and suppressing the bus request output by itself at a constant rate, it is possible to give the processor placed downstream of the daisy chain an opportunity to use the bus.

This makes it possible to avoid the starvation state of the low-priority processor, which is the biggest defect of the serial arbitration method.

Further, in the present embodiment, even if the suppression level of the bus request is set high, the bus request can be immediately output when the bus request from the processor other than itself is not asserted. Therefore, there is no demerit that the bus request is suppressed in the state where the bus is vacant and the usage efficiency is reduced.

(2) Further, in the present embodiment, in adopting the inexpensive serial arbitration method with one bus request line,
Enables even distribution of bus usage, which was previously considered impossible. In particular, when the bus request frequency is set equal to or more than the number of processors connected to the bus for operation, as is clear from the operation of the three processors in FIG. Robin arbitration method (A method in which the processor that last used the bus always has the lowest priority, and the bus can be used according to the request when the priority becomes higher in each bus cycle and becomes the highest priority. It is possible to obtain the same bus arbitration.

(3) Further, in the serial arbitration method capable of constructing a multi-processor system easily and inexpensively, the occurrence of a bus time out due to continuous bus starvation, which has been a problem in the past, is prevented in advance. It is possible to prevent inadvertent occurrence of a fatal abnormality that causes the entire system to stop. As a result, a safe multi-processor system free from bus starvation can be constructed easily and inexpensively.

(4) In particular, in the field of industrial control devices, real-time control with a large number of interrupt factors is performed by a plurality of processors, but when this is configured by the serial arbitration method, the bus starvation state is prevented. Therefore, when trying to set the bus usage rate of each processor to an absolutely safe value, it is necessary to select a considerably small value on the assumption that all interrupt requests occur frequently at the same time.

[0187] This causes the bus usage rate to drop, assuming a very rare increase in bus frequency, resulting in extremely poor efficiency.
In such a case, the present embodiment is most effective.

Originally, when considering the multiplicity of processors with an average bus usage rate of a suitable value (for example, about 20 to 30%), the sum of the maximum values of the frequencies of these buses that are used most frequently. A system in which the ratio exceeds 100% cannot be realized by the conventional serial arbitration method (in order to prevent the bus time out from occurring due to the bus starvation state). The only way to achieve this is to reduce the number of processors or reduce the bus utilization of each.

However, according to the present embodiment, even if the total sum of the maximum bus usage rates of the processors exceeds 100%, the occurrence frequency is not so high and it occurs temporarily and then is alleviated. In such a case, this can be fully realized.

That is, in order to prevent the bus starvation, it is not necessary to design the bus usage frequency assuming a transient saturation of the bus usage, and it is safe to use the average bus usage. It is possible to design various systems.
As a result, it is possible to design a system with high performance and high bus utilization as a whole.

[0191]

As described above, according to the present invention, a bus provided to each processor in a multi-processor system in which one of a plurality of processors is given a right to use the bus by using a daisy chain of bus grant signals. When the bus use request signal from another processor exists on the bus by the request suppressor circuit, the bus use request signal generated from the self processor is suppressed to a certain frequency, so that it is physically downstream of itself in the daisy chain. It is possible to provide a bus utilization opportunity to a processor located in the above, and to eliminate a bus request starvation state of a downstream processor.

As the bus request conditions by the bus request suppression circuit, the states of the bus request signal and the busy signal on the bus,
By monitoring the bus use request inside the processor and the output condition of the bus request suppression pattern extraction circuit, it is possible to realize a uniform bus use rate equivalent to the round arbitration method of the parallel arbitration method while using the serial arbitration method.

[Brief description of drawings]

FIG. 1 is a bus request suppressing circuit diagram showing an embodiment of the present invention.

FIG. 2 is an operation example of a bus arbitration circuit according to the embodiment.

FIG. 3 shows an example of a multi-processor system using a parallel arbitration method.

FIG. 4 shows an example of a multi-processor system using a serial arbitration method.

FIG. 5 shows a problem example of a multi-processor system using a serial arbitration method.

FIG. 6 shows a problematic operation example of a conventional bus arbitration circuit.

FIG. 7 shows an example of a circuit realizing a conventional serial arbitration method.

[Explanation of symbols]

 503 ... Bus request acquisition circuit 601 ... Bus request suppression circuit 602 ... Count up condition generation circuit 603 ... Count clear condition generation circuit 604 ... Counter circuit 605 ... Setting circuit 606 ... Bus request suppression pattern extraction circuit 607 ... Bus request output circuit

Claims (2)

[Claims] 1. A multi-processor system for granting a bus use right to one of a plurality of processors by using a daisy chain of a bus grant signal, wherein each processor is provided with a bus request restraining circuit, and the bus demand restraining circuit is provided. The circuit is
It is provided with means for determining whether or not a bus use request signal from another processor is present on the bus, and suppressing the bus use request signal generated from the self processor to a certain frequency when there is a bus use request. Characteristic bus arbitration method. 2. The bus request suppression circuit includes a counter that counts the number of bus cycles after the bus cycle in which the bus is used by itself, and a bus request whether or not to issue a bus request depending on the output condition of the counter. Bus request suppression pattern extraction means for judging by suppression frequency; output state of the bus request suppression pattern extraction means; bus request signal of its own asserted;
A bus request output circuit which outputs a bus request signal when a busy signal is asserted and a predetermined time has elapsed, and a bus request from the self processor is asserted and a bus request output condition of the bus request suppression pattern extracting means is asserted. And a bus request signal on the bus is asserted and a bus busy signal is asserted, a count-up condition generation circuit for counting up the counter, and a bus request from the self-processor is not asserted or A count for clearing the counter when the bus request output condition of the bus request suppression pattern extracting means is asserted and the bus busy signal on the bus is asserted or the bus request signal on the bus is not asserted. A clear condition generating circuit is provided. Bus arbitration scheme.