JPH05242047A - Method and device for series arbitration of multi-processor system - Google Patents

Abstract

PURPOSE:To simply and inexpensively construct a safe system by renouncing the own bus obtaining right, and transferring a bus permitting signal to the next processor, when an active input of an emergency informing signal asserted by other processor. CONSTITUTION:Processors 70 (70a-70n) contain an arithmetic processing part 74, a bus request obtaining circuit 71 for obtaining the right of using of a bus by a request from this arithmetic processing part 74, output buffer circuits 75a, 75b, an input buffer circuit 76a, a NAND circuit 78a and a NAND circuit 78b. Also, these processors 70 (70a-70n) are provided with an emergency informing timer circuit 80 having a time constant being shorter than that of bus timer circuits 73 (73a-73n) and for driving an output before the timer circuits 73 become time-out, an output buffer circuit 75c, an input buffer circuit 76b, inverting circuits 77b, 77c, NAND circuits 78c, 78d, and a NOR circuit 79.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for constructing a microcomputer system, and more particularly to an arbitration method and apparatus for constructing a multi-processor system using a plurality of processors.

[0002]

2. Description of the Related Art In a multi-processor system using a plurality of processors, an arbitration process is a process for determining which processor uses a system bus that is unique in the system. Call.

Two types of arbitration processing, a parallel arbitration method and a serial arbitration method, are widely known, and generally, any one of them or a combination of both is used.
The parallel arbitration method further includes a central arbitration method and a distributed arbitration method. Here, for the sake of simplicity of explanation, the central arbitration method will be taken up and described.

FIG. 4 shows a general multiprocessor system using a centralized parallel arbitration method. In FIG. 4, 51 is a system bus, 52 is an arbiter circuit for controlling arbitration operation, and 70a to 70n are shown. It is a processor. 4, 53a to 53n are bus request (request) signals for each processor to request the use of the bus, 54a to 54n are bus grant (grant) signals which are the result of arbitration by the arbiter circuit 52, and 56.
Is a busy signal indicating that either processor is using the bus.

As described above, in the case of the parallel type arbitration method, there are as many bus request levels (signals) as there are processors, and arbitration between these levels is performed by the arbiter circuit 52.
Done by The bus request signals 53a to 53n possessed by the processors requesting the use of the bus.
Assert. These signals are all arbiter circuit 5
2 is input to this arbiter circuit according to a predetermined priority (priority) determination rule.
Arbitration processing is performed, and any one of the bus permission signals 54a to 54n is given to any one of the processors. As a result, the processor given the bus permission signal can use the bus in the next cycle. The processor given the bus grant signal monitors the busy signal and can use the bus when it is negated. As soon as the bus is used, this processor asserts a busy signal.

[0006] FIG. 5 shows a multi-channel system using a general serial arbitration method.
5 shows a processor system, and the same members or corresponding portions 10 as those in FIG. 4 are designated by the same reference numerals in FIG. 5, but 55a to 55n are bus permission (grant) output signals. The signal becomes the bus grant input signal of the next processor. Therefore, the signal 55a is the signal 5
4b, the signal 55b is the same signal 54c, and the signal 55c is the same signal 54n.

As shown in the figure, in the case of the serial arbitration method, a plurality of processors output a bus request signal to the same bus request line. Therefore, the level of the bus request is single, and the arbiter circuit 52 may loop the bus request signal or may always assert the bus grant signal 54a for the processor.

The processor requesting the bus asserts the respective bus request signals 53a to 53n. These signals are wired-ORed into one bus request. As described above, the bus permission signal 54a
Since the bus request is looped back or is always asserted, in this system, the bus can be used in the next cycle whenever the processor 70a issues the bus request (when the busy signal is negated, the bus is started to be used). it can).

When the processor 70b or later requests the bus, the processor 70a transmits the level of the bus grant input signal 54a to the bus grant output signal 55a when it does not have the bus request. Similarly, each processor asserts the bus grant output signal when the bus grant input signal becomes active when it is not outputting the bus request.

According to this rule, the bus permission signals are sequentially transmitted, but when the processor issuing the bus use request receives this permission signal, the bus can be used in the next cycle. The processor that asserts the bus request signal and receives the bus grant signal monitors the busy signal and can use the bus when it is negated. As soon as the bus is used, this processor asserts a busy signal.

The signal transmission system of this permission signal is generally called a daisy chain system. According to this method, a processor with a certain number is given the right to use the bus only when all the processors with a number smaller than itself do not request the bus. In other words, in this system, the most upstream processor (70a in this figure) in the daisy chain circuit has the highest priority,
The further down the daisy chain (the higher the number), the lower the priority.

As described above, the serial arbitration method does not require an arbiter circuit in practice, and the bus request signal may be folded back or the level may be fixed. Therefore, the serial arbitration method is very simple and inexpensive. -The feature is that a processor system can be constructed.

However, in this method, since a method called a daisy chain of bus permission signals is used, a signal delay occurs in the daisy chain circuit of each processor, and arbitration ends until this is transmitted to the final processor. Therefore, arbitration time is required in proportion to the number of processors, which is not suitable for a large-scale system with many processors (effective for about 1 to 4 processors).

On the other hand, in the case of the parallel arbitration method, since the centralized arbiter circuit makes the priority determination at once, the arbitration time is not affected much by the number of processors, and the arbitration time is performed in a substantially constant time. be able to. However, in addition to each processor, a complicated arbiter circuit is required and a dedicated bus wiring is required between each processor and the arbiter circuit, which limits the number of processors physically and economically. Is coming out. Generally, this method is suitable for a medium-scale multi-processor system (the number of processors is 2 to 8).

In the case of a large-scale system having more processors, a combination of the serial arbitration method and the parallel arbitration method described above is used to daisy-chain the bus grant signals of each priority level arbitrated by the parallel arbitration, thereby making a serial connection. Number of connected units ×
There is also an example in which processors with parallel level numbers are connected.

FIG. 6 shows in detail the configuration of the processor portion of the multiprocessor system shown in FIG.
˜71n are bus request acquisition circuits for performing bus request output and bus acquisition determination, 72a to 72n are daisy chain circuits of bus grant signals in each processor, and 73a to 73n.
Is a bus timer circuit that monitors the time until the bus usage right is acquired in each processor. 57a-57n
Is a bus timeout signal generated when the bus timer on each processor detects an abnormally long wait state.

FIG. 7 shows an actual circuit example of each processor 70 (70a to 70n) having the conventional serial arbitration method. The processor 70 is an arithmetic processing unit 74, and a bus request from the arithmetic processing unit 74 causes the bus to operate. The bus request acquisition circuit 71 (71a to 71n) for acquiring the right of use, the output buffer circuits 75a and 75b, the input buffer circuit 76, the inversion circuit 77, and the NAND gates 78a and 78b are provided.

Signals A to E are signals on the bus, A is a "BREQ L" signal indicating a bus request, B is a "BUSY L" signal indicating that the bus is in use, and C is a bus permission input "BGI."
NL "signal, D is bus enable output" BGOUT L ", E
Is a "BTOUT L" signal for notifying the bus acquisition abnormality to the outside.

First, when the arithmetic processing unit 74 gives a request to use the bus to the bus request acquisition circuit 71, the bus timer circuit 73 asserts a "bus request signal" 81. Then, the output buffer 75a causes the external bus signal A ("B
REQ L ”signal) is driven.

Bus enable signal by the arbiter circuit on the system (or return of this "BREQ L" signal)
Is provided to this processor as a bus signal C.

When the signal C becomes active, the signal 81 is already active.
Signal 84 is asserted by circuit 78a. This is the "bus acquisition signal". This signal becomes active and is monitored via circuit 73 at "B" on the bus.
When the "USY L" signal is inactive, the arithmetic processing unit 74 can use the bus. When the bus is actually used, the signal 81 is activated by itself and the output buffer 75b asserts the "BUSY L" signal to notify the other processors that the bus is in use.

In the NAND circuit 78b portion, the C signal side is active, but since the bus request signal 81 is inverted by the inversion circuit 77 and given, the output remains negated. Therefore, the "bus grant output" of the bus signal D does not become active.

On the other hand, when the bus permission signal C becomes active when the processor is not requesting the bus (the signal 81 is inactive), both inputs of the NAND circuit 78 become the active state. Signal D
Assert (“BGOUT L” signal). As a result, the bus grant is given to a processor having a lower priority than this processor. This circuit 77, 78
b is a daisy chain circuit.

The bus / timer circuit 73 enters a timing operation when the signal 81 becomes active and issues a bus request, and stops this operation at the time when the signal 82 becomes active and bus use is declared. If the timekeeping operation is not stopped within a predetermined time, the signal E (“BTOUT L” signal) on the bus is driven to notify the abnormality to the outside.

FIG. 8 shows an example of the operation of the multi-processor system shown in FIGS. 6 and 7. The signal names are
In accordance with FIG. 6, all signals are “low level (L level)” and have meaning. In this example, the processor 70a
And although the processor 70b opens the bus every time,
Since there is an internal request to constantly use the bus, the buses are alternately used, and the processors 70c, 70n
Shows that the bus cannot be used forever and the bus timeout is detected.

The operation will be described in the order of the numbers added in the time chart of FIG.

(1) The processor 70a requests the bus,
Assert the bus request number 53a.

(2) The processor 70b requests the bus,
Assert the bus request signal 53b.

(3) The processor 70c requests the bus,
Assert the bus request signal 53c. Processor 70c
The bus timer circuit of is started and the time counting operation is started.

(4) The processor 70n requests the bus,
Assert the bus request signal 53n. Processor 70n
The bus timer circuit of is started and the time counting operation is started.

(5) The bus permission signal for the processor 70a is always in the active state.

(6) Since the processor 70a has acquired the bus, it starts using the bus and asserts the busy signal 56.

(7) The processor 70a negates the bus request.

(8) Since the processor 70a negates the bus request, the bus grant signal is transmitted to the processor 70b.

(9) The processor 70a negates the busy signal 56 when it finishes using the bus. The processor with the active bus request and grant at this point then wins the bus. Here, the processors 70b, 70c,
Although 70n issues a bus request, the bus permission is given to the processor 70b, so that 70b can use the bus next time.

(10) The processor 70b acquires the bus and negates the bus request.

(11) Since the bus request of the processor 70b is negated, the bus permission signal for the processor 70c is once asserted.

(12) Since the processor 70b has acquired the bus, it starts using the bus and asserts the busy signal 56.

(13) The processor 70a asserts the next bus request.

(14) The bus permission given to the processor 70b is negated.

(15) The bus permission given to the processor 70c is negated.

(16) The processor 70b negates the busy signal 56 when it finishes using the bus. The processor with the active bus request and grant at this point then wins the bus. Here, the processors 70a, 70
Although c and 70n issue the bus request, the bus permission is given to the processor 70a, so that 70a can use the bus next time.

(17) Since the processor 70a has acquired the bus, it starts using the bus and asserts the busy signal 56.

(18) When the operations of (1) to (17) are continued, the processor 70c, which continues to issue the bus request from (3), cannot acquire the bus even if it waits forever, and this bus timer circuit , The bus time-out signal 57c is output.

(19) When the operations of (1) to (17) are continued, the processor 70n which keeps issuing the bus request from (4) cannot acquire the bus no matter how long it waits, and this bus timer circuit , The bus time-out signal 57c is output.

[0046]

[Problems to be Solved by the Invention] Multiprocessor
Among the arbitration processing methods for constructing the system, the serial arbitration method is an effective means for realizing this at a low price when constructing a relatively small-scale system, as described above. In a large-scale system, this is used in combination with the parallel arbitration method.
This is a general and highly important method.

However, in the case of this system, when a high-priority processor continuously uses the bus, a "bus starvation state" may occur in which a low-priority processor cannot use the bus forever. I have sex.

For this reason, each processor normally operates in the "every time bus release mode" in which the bus is released every time a bus cycle is executed in order to avoid continuous use of the bus. However, even if this method is used, if the processor with the highest priority and the processor with the next highest priority use the bus continuously, the two processors can only use the bus alternately,
The third and subsequent processors cannot use the bus forever, resulting in a bus timeout condition.

The bus time-out in the processor is treated as a fatal abnormality and is a factor to stop the operation of the system. Therefore, in order to prevent such "bus starvation" from occurring, system designers must limit the number of processors used and ensure that continuous bus usage does not occur in high-priority processors due to processor applications. It was necessary to pay attention.

However, the avoidance of this "bus starvation" is as follows.
This is a very difficult problem in a multi-processor system for real-time processing in which each processor independently processes a plurality of events that occur asynchronously.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to solve the above-mentioned conventional problems.

[0052]

In order to achieve the above object, the present invention transmits and receives processing information of a plurality of processors through a system bus, and each processor requests a use of the system bus. In a multi-processor system that outputs a signal and exchanges a bus permission signal for permitting the use of the system bus between the processors in the next stages, each processor 70 includes an arithmetic processing unit 74 for instructing a bus request, Bus acquisition circuit 71 for acquiring the bus use right in response to a request from the arithmetic processing unit 74
And a bus timer circuit 73 for detecting a bus timeout
And an emergency notification timer circuit 80 having a time constant shorter than that of the bus timer circuit 73, and processing an emergency bus acquisition request signal of the emergency notification timer circuit 80 to give a bus permission signal to the corresponding processor. The daisy chain circuit 72 constitutes a serial arbitration device.

[0053]

In the present invention, the bus enable signal daisy
In a multi-processor system using a chain, each processor acquires the right to use the bus based on the bus request command of the arithmetic processing unit, outputs the bus acquisition signal in an emergency, and is determined by the physical arrangement. Even if the relevant processor is granted the right to use the next bus by priority, it will relinquish its own right to acquire the bus and receive the right to use the next processor when there is an active input of the emergency notification signal asserted by another processor. The bus permission signal.

[0054]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 2 shows the structure of a multi-processor system for executing the arbitration method according to the embodiment of the present invention. The same or corresponding parts as those of FIGS. 5 and 6 are designated by the same reference numerals. ing. Further, FIG. 1 shows the configuration of the processor in the system of FIG. 2, and the same or corresponding parts as those of FIG. 7 are designated by the same reference numerals.

As shown in FIG. 1, the processor 70 (70
a to 70n) are, as described above, the arithmetic processing unit 74, the bus request acquisition circuit 71 for acquiring the right to use the bus in response to the request from the arithmetic processing unit 74, and the output buffer circuit 75.
a, 75b, an input buffer circuit 76a, an input buffer circuit 76a, a NAND circuit 78a, and a NAND circuit 78a,
Including 78b.

Further, in this embodiment, the processor 70 (7
0a to 70n) is further added to the bus timer circuit 73 (7
3a to 73n) and an emergency notification timer circuit 80 having a time constant shorter than 3a to 73n) and driving an output before the bus timer circuit times out, an output buffer circuit 75c, an input buffer circuit 76b, invert circuits 77b and 77c, a NAND circuit 78c. , 78d and a NOR circuit 79 are provided.

Signals A to E are signals on the same bus as before, A is "BREQL" indicating a bus request, B is a "BUSY L" signal indicating that the bus is in use, and C is a bus permission input "B".
“GIN L” signal, D is bus permission output “BGOUT
"L" signal, E is "BTO
UT L "signal. Further, the signal F is a signal added by the present invention, which is an emergency bus acquisition request signal "EMGC".
Y L ".

The processors shown in FIG. 1 are connected as shown in FIG. 2 and FIG. 1, the signal A of FIG. 1 corresponds to the busy signal 56 of FIG. 2, the signal B is the bus request signals 53a to 53n, the signal C is the bus permission input signals 54a to 54n, and the signal D. Is the bus permission output signal 55a-
55n, the signal E is the bus timeout signals 57a-5
It corresponds to 7n. Further, in FIG. 2, 58 is an emergency signal “EMGCY L”, and 59a to 59n are emergency input / output signals of each processor.

In the processor of FIG. 1, first, the arithmetic processing unit 74 issues a request for using the bus to the bus request acquisition circuit 71.
To the bus request acquisition circuit 71 "bus request signal" 8
Assert one. Then, the output buffer circuit 75a drives the external bus signal A (“BREQ L” signal).

Bus enable signal by the arbiter circuit on the system (or return of this "BREQ L" signal)
Is provided to this processor as a bus signal C.
When the signal C becomes active, the signal 81 is already active. Therefore, if the output signal 85 of the inverter 77b is active, the inverted NAND circuit 78a is activated.
Causes signal 84 to be asserted. This is the "bus acquisition signal".

The input signal of the inverter 77b is the output signal 86 of the inverted NAND circuit 78a.
Has asserted the "CYL" signal. " The condition that signal 85 is active is that none of the other processors have asserted the "EMGCY L" signal or that they are asserting this.

When the bus acquisition signal becomes active and the "BUSY L" signal on the bus monitored via the input buffer circuit 76a is inactive, the arithmetic processing unit 74 can use the bus. it can. When the bus is actually used, the signal itself is activated and the output buffer 75b asserts the "BUSY L" signal to notify the other processors that the bus is in use.

In the NAND circuit 78b portion, the C signal side is active, but since the signal 81 is inverted by the inversion circuit 77a and given, the output remains negated. Therefore, the "bus grant output" of the bus signal D will not become active unless the NAND circuit 78c output 87 becomes active. The condition that the circuit 78c becomes active is that the signal 86 indicating that "a processor other than itself asserts the emergency signal" EMGCY L "signal" is active and the bus permission input C signal becomes active. ..

On the other hand, when the bus permission signal C becomes active when the processor is not requesting the bus (bus request signal 89 is inactive), the NAND circuit 7 is activated.
Both inputs of 8b are in the active state, so that the signal 88 is asserted and the bus signal D (“BGOUT
The "L" signal) also becomes active. As a result, the bus grant is given to a processor having a lower priority than this processor.

The bus timer circuit 73 uses the bus request signal 8
When 1 becomes active and issues a bus request, the timing operation starts, and when signal 82 becomes active and bus use is declared, this operation is stopped. If the timekeeping operation is not stopped within a predetermined time, the signal E (“BTOUT L” signal) on the bus is driven to notify the abnormality to the outside. The circuit operation up to this point is approximately the same as the conventional circuit in FIG.

In the part added by the present invention,
First, the “emergency notification timer circuit” 80 is a timer circuit whose time constant is set shorter than that of the bus timer circuit 73 as described above, and the conditions for starting and stopping are the same as those of the bus timer circuit 73. In other words, the "emergency notification timer circuit" is used before the bus / timer circuit 73 detects an abnormality, notifies the outside of the time-out, and causes the system to stop due to a fatal failure.
Activates the "EMCCY L" signal F on the bus.

The output buffer 75c is "EMCCY L".
The signal F is driven, and the input buffer circuit 76b takes in this signal internally. The inverter circuit 77c inverts the phase of the output 89 of the "emergency notification timer circuit" 80.

The "EMCCY L" signal F is a signal of a wired OR driven by a plurality of processors. The signal 90 and the signal 91 which take this signal are passed to the inverted NAND circuit 78d. Processor has asserted the emergency signal "EMCCY L" signal. "

When this signal 86 is active, it is inverted by the inverter 77b and enters the NAND circuit 77b. Therefore, even if this processor issues a bus request and the bus permission signal input C becomes active, The bus acquisition signal 84 is not asserted.

At this time, the inputs of the circuit 78c are
Since it becomes active, the signal 87 is asserted and the output of the NOR circuit 79, that is, the bus permission signal output D is asserted regardless of the output state of the NAND circuit 78b.

This is the basic operation of the present invention. With this circuit configuration, "Even if the user is allowed to use the next bus by the priority determined by the physical arrangement," EMCCY " L "
If there is an active input of a signal, it abandons its own bus acquisition and transmits a bus grant signal to the next processor ”.

For this reason, in the serial arbitration type multi-processor system adopting this circuit configuration, the processor having the higher physical priority continuously uses the bus, so that the processor having the lower priority is Even if the bus cannot be used for a long time, the low-priority processor outputs the "EMCCY L" signal F and interrupts the bus usage of the upper processor before the system is stopped due to the original bus timeout abnormality. Then, the processor that outputs this signal can acquire the bus.

FIG. 3 shows the state of arbitration in the case of the present circuit configuration, in contrast to the state of bus timeout occurrence in the conventional serial arbitration system shown in FIG. Signal names and the like use the symbols in FIG.

The operation will be described in the order of the numbers added in the time chart of FIG.

(1) The processor 70a requests the bus,
Assert the bus request number 53a.

(2) The processor 70b requests the bus,
Assert the bus request signal 53b.

(3) The processor 70c requests the bus,
Assert the bus request number 53c. Processor 70c
The bus timer circuit of is started and the time counting operation is started.

(4) The processor 70n requests the bus,
Assert the bus request signal 53n. Processor 70n
The bus timer circuit of is started and the time counting operation is started.

(5) The bus permission signal for the processor 70a is always active.

(6) Since the processor 70a has acquired the bus, it starts using the bus and asserts the busy signal 56.

(7) The processor 70a negates the bus request.

(8) Since the processor 70a negates the bus request, the bus grant signal is transmitted to the processor 70b.

(9) The processor 70a negates the busy signal 56 when the use of the bus is completed. The processor with the active bus request and grant at this point then wins the bus. Here, the processors 70b, 70c,
Although 70n issues a bus request, the bus permission is given to the processor 70b, so that 70b can use the bus next time.

(10) The processor 70b acquires the bus and negates the bus request.

(11) Since the bus request of the processor 70b is negated, the bus permission signal for the processor 70c is once asserted.

(12) Since the processor 70b has acquired the bus, it starts using the bus and asserts the busy signal 56.

(13) The processor 70a asserts the next bus request.

(14) The bus permission given to the processor 70b is negated.

(15) The bus permission given to the processor 70c is negated.

(16) The processor 70b negates the busy signal 56 when it finishes using the bus. The processor with the active bus request and grant at this point then wins the bus. Here, the processors 70a, 70
Although c and 70n issue the bus request, the bus permission is given to the processor 70a, so that 70a can use the bus next time.

(17) Since the processor 70a has acquired the bus, it starts using the bus and asserts the busy signal 56. The operation up to this point is the same as in FIG.

(18) If bus acquisition is not continued, it is expected that the processor 70b will time out the bus at the time of (19), but prior to this, the emergency notification signal 59
c is asserted. The "EMGCY L" signal on the bus becomes active.

(19) In this example, since the processor 70a is using the bus and negates the bus request, the bus grant signal 59a (59b) to the processor 70b is already active, but the "EMGCY L" signal is output. Is asserted to force 59a to become active.

(20) 59a is already active,
Also, the assertion of the "EMGCY L" signal forces 59b (59c) to become active.

(21) Next, at the rising edge of the busy signal,
The processor 70c acquires the bus. As a result, the processor 70c negates the bus request signal 59c.

(22) The processor 70c starts using the bus and asserts the busy signal 56.

(23) When the processor 70c asserts the busy signal, the emergency notification timer and the bus timer on the processor 70c stop the time counting operation. The emergency notification number 59c is negated. As a result, the bus timer stops before the timing (19) when the bus timer times out, and the timeout error does not occur.

(24) The processor 70a issues the next bus request.

(25) The bus permission signal 55a to the processor 70b is negated.

(26) Bus grant signal 5 to the processor 70c by negating the "EMGCY L" signal.
5b is negated.

(27) The processor 70c negates the busy signal 56 when the use of the bus is completed. At this point the next processor wins the bus. In this case, the processor 70a acquires the bus again.

(28) If bus acquisition is not continued, it is expected that the processor 70c will time out the bus at the time of (30), but prior to this, the emergency notification signal 59
n is asserted. (The "EMGCY L" signal on the bus becomes active.) (29) In this example, the processor 70a is using the bus and negates the bus request.
The bus permission signal 59a (59b) for b is already active, but 55a is forcibly activated by asserting the "EMGCY L" signal.

(30) 55a is already active,
Moreover, 59b (59c) is forcibly asserted by asserting the "EMGCY L" signal.

(31) 55b is already active,
Moreover, 55c (54n) is forcibly asserted by asserting the "EMGCY L" signal.

(32) At the next rising edge of the busy signal,
The processor 70n acquires the bus. As a result, the processor 70n negates the bus request signal 53n.

(33) The processor 70n starts using the bus and asserts the busy signal 56.

(34) When the processor 70n asserts the busy signal, the emergency notification timer and the bus timer on the processor 70n stop the time counting operation. The emergency notification signal 59n is negated. As a result, the bus timer stops before the timing (30) when the bus timer times out, and the timeout error does not occur.

(35) Bus grant signal 5 to the processor 70c by negating the "EMGCY L" signal.
5b is negated.

(36) By negating the "EMGCY L" signal, the bus grant signal 5 to the processor 70n
5c is negated.

(37) The processor 70a issues the next bus request.

(38) The bus permission signal 55a for the processor 70b is negated.

(39) When the processor 70n finishes using the bus, it negates the busy signal 56. At this point, the next processor acquires the bus. In this case, the processor 70a acquires the bus again.

[0114]

The present invention is as described above, and the following effects can be obtained.

(A) In the serial arbitration method capable of constructing a multi-processor system easily and inexpensively, a bus problem caused by continuous bus starvation has been a problem in the past.
It prevents the occurrence of a timeout in advance and prevents the fatal anomaly that would cause the entire system to stop. As a result, a safe multi-processor system without bus starvation can be constructed easily and inexpensively.

(B) Particularly in the field of industrial control devices, real-time control with a large number of interrupt factors is performed by a plurality of processors. If this is configured by the serial arbitration method, bus starvation is prevented. In order to
In order to set the bus utilization of each processor to an absolutely safe value, it is necessary to select a considerably small value on the assumption that all interrupt elements occur frequently at the same time. This is extremely inefficient because the bus usage rate is reduced assuming a very rare increase in bus frequency. The method of the present invention is most effective in such a case.

(C) Originally, when considering the multiplicity of processors with an average bus usage rate of a suitable value (for example, about 20 to 30%), the maximum value of the frequent maximum value in which these processors use the bus most frequently is considered. A system in which the sum exceeds 100% cannot be realized by the conventional serial arbitration method (to prevent a bus timeout from occurring due to a bus starvation state). The only way to achieve this was to reduce the number of processors or reduce the bus utilization of each. However, according to this method, even if the sum of the maximum bus usage rates of the processors exceeds 100%, the frequency of occurrence is not so high and it occurs temporarily and then relaxes. Will be fully able to do this. In other words, in order to prevent bus starvation, it is not necessary to design the bus usage frequency assuming a transient saturation of the bus usage rate, and a system that is safe even with an average bus usage rate is used. Design can be done. This enables a high performance system design with an overall high bus utilization.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor which is a main part of a serial arbitration device of a multi-processor system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a serial arbitration device of a multi-processor system according to an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the serial arbitration device of the multi-processor system according to the embodiment of the present invention.

FIG. 4 is a block diagram of a multiprocessor system using a general parallel arbitration method.

FIG. 5 is a block diagram of a multiprocessor system using a general serial arbitration method.

FIG. 6 is a block diagram of a serial arbitration device of a conventional multi-processor system.

FIG. 7 is a configuration diagram of a processor which is a main part of a serial arbitration device of a conventional multi-processor system.

FIG. 8 is an operation explanatory diagram of a serial arbitration device of a conventional multi-processor system.

[Explanation of symbols]

51 ... System bus, 52 ... Arbiter circuit, A (56)
... busy signal, B (53a to 53n) ... bus request signal,
C (54a to 54n) bus permission signal, D (55a to 55)
n) ... Bus permission input signal, E (57a to 57n) ... Bus timeout signal, F ... Emergency bus acquisition request signal, 5
8 ... emergency signal, 59a to 59n ... emergency input / output signal, 70
(70a to 70n) ... Processor, 71 (71a to 71)
n) ... bus request acquisition circuit, 72 ... daisy chain circuit, 73 (73a to 73n) ... bus timer circuit, 74 ...
Arithmetic processing unit, 75a to 75c ... Output buffer circuit, 76
a, 76b ... Input buffer circuit, 77a-77c ... Invert circuit, 78a-78d ... NAND circuit, 79 ... NOR circuit, 80 ... Emergency notification timer circuit.

Claims (2)

[Claims] 1. Processing information of a plurality of processors is transmitted and received through a system bus, and each processor outputs a bus request signal requesting use of the system bus, and the processor of the next stage uses the system bus. In a multi-processor system that sends and receives bus grant signals that permit the bus, each processor acquires the bus usage right based on the bus request command from the arithmetic processing unit, outputs the bus acquisition signal in an emergency, and Even if the processor is in a state in which the next bus usage right is recognized by the priority determined by the physical allocation, it will relinquish its own bus acquisition right when there is an active input of the emergency notification signal asserted by another processor. , A multi-processor characterized by transmitting a bus grant signal to the next processor Series arbitration method of the system. 2. Processing information of a plurality of processors is transmitted and received through a system bus, and each processor outputs a bus request signal requesting the use of the system bus, and the processor of the next stage uses the system bus. In a multi-processor system for exchanging a bus permission signal for permitting each bus, each processor (70) uses an arithmetic processing unit (74) for instructing a bus request, and a bus use by a request from this arithmetic processing unit (74). A bus acquisition circuit (71) for acquiring the right, a bus timer circuit (73) for detecting a bus timeout,
An emergency notification timer circuit (80) having a time constant shorter than the time constant of the bus timer circuit (73) and a bus acquisition request signal in an emergency of the emergency notification timer circuit (80) are processed to provide a bus to a corresponding processor. Serial arbitration device for a multi-processor system, characterized in that it is constituted by a daisy chain circuit (72) for giving a permission signal.