JPH07210499A - Bus driver selecting circuit - Google Patents

Abstract

PURPOSE:To prevent the collision of data on a multiple bus by making each driver on main and extension substrates have a selective use right and instructing the output of data by means of a control signal for accessing to each block of a divided address area. CONSTITUTION:CPU 2 and its access device 16 are mounted on the main substrate 1 and the same device 16 is mounted on the extension substrate 18. Then, the interval of the main and the extension substrates 1 and 18 is connected by the multiple bus 3. Then, transceiver output valid signals 14 and 15 making a data transceiver IC 10 recognize a using right are generated by control signals 6 to 8 concerning access through the use of address decode IC 11. Then, the use right of the mutiple bus is given to only the data transceiver IC 10 on the main substrate 1 when CPU 2 accesses to the access device 16 on the main substrate 16, but to only data transceiver IC 10 on the extension substrate 18 when CPU 2 accesses to the access device 16 on the extension substrate 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU module constituting a control device for a plant or the like, which is characterized by an arbitration means for bus use right when a plurality of bus drivers drive a data bus of one CPU. Regarding driver selection method.

[0002]

2. Description of the Related Art A control device such as a plant is usually a CPU.
It is realized by mounting a plurality of semiconductor chips such as ICs, LSIs, etc., whose chips are control centers, on a substrate. 2. Description of the Related Art Conventionally, in a control circuit of this type of device, when a CPU that inputs and outputs both address and data by time division is used on the same multiplex bus, a circuit configuration as shown in FIG. 2 is adopted.

FIG. 2 is a CP using a CPU having multiple buses.
It is a block diagram which shows the basic composition of a U module. Figure 2
In the figure, 1 is a main board on which various circuit elements constituting the above-mentioned control device are mounted, 2 is a CPU that controls the entire device, and 3 is a multiplex bus. Reference numerals 4, 5 and 8 are control signals output from the CPU 1, and 4 is an address valid signal for notifying an address output timing.
Is an input / output control signal for informing the data input / output direction, and 8 is a data valid signal for informing the data input / output timing. Reference numeral 9 is an address holding IC (AL-IC), 10 is a data transceiver IC (DT-IC), 12 is an address bus, 13 is a data bus, and 16 is an access device of the CPU 2.

In the above structure, the address and data on the multiplex bus 3 output from the CPU 2 are the address holding IC (AL-IC) 9 and the data transceiver IC.
The data is distributed to the address bus 12 and the data bus 13 by the (DT-IC) 10 and supplied to the access device 16. That is, using the address holding IC (AL-IC) 9 and the data transceiver IC (DT-IC) 10, the control signals 4 and 8 for notifying the valid timing of each address and data from the CPU 2 and the data input / output. Addresses and data are distributed to the access device 16 of the CPU 2 by using the control signal 5 indicating the direction.

In such a CPU module, in the case of adopting a plurality of boards (for connecting the expansion board to the main board 1 by a connector) in order to expand the signal input / output function and the like, in the conventional case, the expanded board is used. The address and data bus lines of the address holding IC 9 are as shown in FIG.
And the buses 12 and 13 after being distributed by the data transceiver IC 10 were wired.

FIG. 3 is a block diagram showing a conventional hardware configuration when addresses and data are individually wired. In FIG. 3, 18 is an expansion board, 19 is a connector for connecting the expansion board 18 to the main board 1, and 20, 2
1 is a buffer IC for each address and data (BUF
-IC).

In the configuration shown in FIG. 3, since there is only one transceiver IC 10 that drives the multiplex bus 3 of the CPU 2, data collision does not occur, but a signal line (cable) 17 connected via the connector 19 is used. Will increase in number. Further, since the wiring length of the address bus 12 and the data bus 13 to the extension board 18 becomes long, the buffer IC 20,
21 must be added.

FIG. 4 is a block diagram showing a hardware configuration when there is a possibility of data collision on the multiplex bus 3. The multiple bus 3 of the CPU 2 is driven by a plurality of data transceiver ICs (each of the data transceiver ICs on the main board 1 and the extension board 18) 10 and the output thereof is validated by the same data valid signal 8. Data collision on 3 occurs.

[0009]

As described above, FIG.
In the conventional method shown in (1), since the address and data are individually wired to the extension board 18, the number of signal lines to be wired increases, and accordingly, the main board 1 and the extension board 18 are connected.
Since the size of the connector 19 and the like for connecting the components becomes large, problems such as a decrease in component mounting efficiency and an increase in cost are brought about.

When the address and data are not individually wired but the multiplex bus 3 of the CPU 2 is wired as shown in FIG. 4, the number of signal lines (cables) 20 is reduced, but the address holding IC 9 is used. , Data transceiver IC
Since a plurality of ICs such as 10 share the multiplex bus 3 of the CPU 2, when these ICs input data to the CPU 2, data collision may occur on the multiplex bus.

The present invention has been made in view of the above circumstances,
In order to arbitrate the right to use the bus so that the bus collision does not occur when the CPU multiple bus is wired on the expansion board and the address holding IC and the data transceiver IC are arranged on each of the main board and the expansion board. It is an object to provide a bus driver selection method provided with a function.

[0012]

As shown in FIG. 1, the hardware configuration of the present invention is, as shown in FIG.
In the CPU module including the above, the CPU 2 and the access device 16 for the CPU 2 are mounted (mounted) on the main board 1, and the access device 16 for the CPU 2 on the main board 1 is also mounted on the extension board 18. Is installed.

The bus connection between the main board 1 and the extension board 18 is made by the multiplex bus 3 of the CPU 2.
In such a hardware configuration, when the CPU 2 accesses the access device 16 on the main board 1 only the data transceiver IC 10 on the main board 1 so that the data collision does not occur on the multiplex bus 3. Further, when accessing the access device 16 on the extension board 18, the data transceiver IC 10 of the extension board 18 is
Only the right to use the multiple buses is given to the other. At this time, the control signals 6, 7,
8, the address decoding IC (AD-IC) 11 is used to generate the transceiver output valid signals 14 and 15 for causing the data transceiver IC 10 to recognize the usage right.

[0014]

In the configuration shown in FIG. 4, the data transceiver IC
10 outputs the data on the data bus 13 to the multiplex bus 3, but the data bus 1 on the device side which is not accessed
Since the value of 3 is indefinite, the output of the data transceiver IC 10 on the device side becomes indefinite, which may cause data collision on the multiplex bus 3. In order to solve such a problem, FIG. In the configuration according to the embodiment of the present invention shown, the collision of data on the multiplex bus 3 is avoided by using the access selection signals 6 and 7 of the CPU 2.
The access selection signals 6 and 7 respectively receive a predetermined range of the accessible address area of the CPU 2, and when the range is accessed, the CPU 2 notifies the access target of the range. Is equipped with. That is, when the CPU 2 accesses the access device 16 on the main board 1, the corresponding address is output via the address holding IC 9, and the access selection signal 6 is output accordingly. Then CPU2
When the data valid signal 8 is output at the data input / output timing of, the address decoding IC 11 outputs the transceiver output valid signal 14 to enable only the data output of the data transceiver IC 10 on the main board 1.
Similarly, the access to the access device 16 on the extension board 18 enables only the data output of the data transceiver IC 10 on the extension board 18 by the transceiver valid signal 15. With such control means, it is possible to avoid data collision on the multiplex bus 3 of the CPU 2.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a hardware configuration according to an embodiment of the present invention. In FIG. 1, the main board 1
The upper CPU 2 uses the multiplex bus 3 to input / output addresses and data to / from the access device 16 in a time division manner.

The address holding ICs 9 on the main board 1 and the extension board 18 both recognize the address output timing of the CPU 2 by using the address valid signal 4.
The address is output to the address bus 12.

This address is held in the address holding IC 9 until the next address output timing. The access device 16 which has recognized the access to itself by this address is the multiplex bus 3, the data transceiver IC1.
Data is input / output to / from the CPU 2 via 0 and the data bus 13.

The direction of data input / output at this time is determined by controlling the data transceiver IC 10 by the input / output control signal 5. In such a circuit configuration, when the CPU 2 receives data from the access device 16, the access device 16 outputs the data onto the data bus 13 when it recognizes the access to itself.

The data output on the data bus 13 is input to the data transceiver IC 10. The data transceiver IC 10 outputs the data on the data bus 13 to the multiplex bus 3. However, since the value of the data bus 13 on the device side which is not accessed is undefined, the output of the data transceiver IC 10 on the device side is undefined. , Data collision on the multiplex bus 3 may occur.

In order to solve such a problem, in the embodiment of the present invention, the access selection signals 6 and 7 of the CPU 2 are used. These signals 6 and 7 are
Of the two accessible address areas, the CPU receives a predetermined range, and when the range is accessed, the CPU notifies the access target of the range.
2 has.

In the circuit of the embodiment shown in FIG. 1, the access device 16 on the main board 1 is arranged in the address area for the access signal 6, and the access device 16 on the expansion board 18 is arranged in the address area for the access signal 7. Place these access selection signals 6, 7 and CPU
2 from the data valid signal 8 indicating the data input / output timing, the transceiver output valid signals 14 and 1 for instructing the data transceiver IC 10 to output the data by using the address decoding IC (AD-IC) 11.
5 is generated.

That is, when the CPU 2 accesses the access device 16 on the main board 1, the corresponding address is output via the address holding IC 9 and the access selection signal 6 is output in accordance with the output.

After that, when the data valid signal 8 is output at the data input / output timing of the CPU 2, the address decoding IC 11 causes the transceiver output valid signal 14
Data transceiver IC1 on the main board 1
Only the data output of 0 is valid.

Similarly to the access to the access device 16 on the extension board 18, only the data output of the data transceiver IC 10 on the extension board 18 is validated by the transceiver valid signal 15.

By the above control means, it is possible to avoid data collision on the multiplex bus 3 of the CPU 2. It should be noted that in the block diagram of FIG.
The connector 19 and the cable 17 are provided for connection between the extension board 18 and the expansion board 18, but the present invention can be applied to other connection configurations.

[0026]

As described above in detail, according to the present invention, C
Since it is possible to connect a plurality of bus drivers to the PU multiplex bus, it is possible to directly connect the multiplex bus through a connector or the like to a CPU module having a plurality of boards, and reduce the number of signal lines. Low cost and high mounting efficiency of modules can be expected due to miniaturization of connectors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a hardware configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a board configuration of a CPU module using a CPU having a multiple bus.

FIG. 3 is a block diagram showing a hardware configuration in the case of a conventional address and data individual wiring.

FIG. 4 is a block diagram showing a hardware configuration when there is a possibility of data collision on a multiplex bus.

[Explanation of symbols]

1 ... Main board, 2 ... CPU, 3 ... Multiplex bus, 4 ... Address valid signal, 5 ... Input / output control signal, 6 ... Access selection signal, 7 ... Access selection signal, 8 ... Data valid signal, 9
Address holding IC (AL-IC), 10 data transceiver IC (DT-IC), 11 address decoding IC (AD-IC), 12 address bus, 13 data bus, 14 transceiver output enable signal, 15 ... Transceiver valid signal, 16 ... Access device, 17 ...
Cable, 18 ... Expansion board, 19 ... Connector.

Claims (1)

[Claims] 1. An address and data are input / output by a single multiplex bus by a first control signal indicating an address, a valid timing of data, and a second control signal indicating a direction of data input / output, and access is performed. The possible address area is divided into several blocks, and C is provided with a third control signal for accessing each block.
A first board on which a PU and a driver for driving a multiplex bus of the same CPU are mounted, and a CP provided on the same board
In a control circuit comprising a second board which is connected to a U multiplex bus and has a driver for driving the same bus, the control circuit is individually provided to each driver based on the third control signal. A circuit for generating a control signal for instructing the output of data is provided, and a plurality of drivers on each of the above-mentioned boards are individually given a selective use right to avoid data collision on the bus by a plurality of drivers. Bus driver selection method.