JPH07210272A - Power reset circuit - Google Patents

Abstract

PURPOSE:To prevent such a defect of a data transmitter where the wrong reception output is transmitted according the rise and drop of the power voltage in a power application mode or a power voltage instant drop reset mode. CONSTITUTION:A power reset circuit 4 includes a forced discharge circuit 3 added to a power ON-mode reset circuit consisting of a capacitor C1, a resistance R1 and a transistor Q1. In such a constitution, the circuit 4 can always operate in a normal state even in a circuit constant setting mode such as a power voltage instant drop reset mode going against a power application mode. Then the unallowable wrong transmission of the reception output is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply reset circuit for use in an optical transmission module receiving circuit in optical transmission, which is capable of recovering from a power supply voltage drop.

[0002]

2. Description of the Related Art Conventionally, a power-on reset circuit is described in Japanese Patent Publication No. 5-7893.
Or Nikkei Electronics 1983, 7, 18
139. There is a power-on reset circuit in ATC circuit example I.

These circuits are, for example, as shown in FIG.
In order to prevent the output voltage VO, which should be at the L level when no signal is input, from being fixed at the H level following the rise of the power when the power is turned on, the capacitor C ₁ , the resistor R ₁ , the transistor Q ₁
A power-on reset circuit consisting of was added. As a result, the reset circuit is operated only in the transient state when the power is turned on, and the reference voltage VR is forcibly set to the L level, whereby the output voltage VO becomes the L level.

Further, the base voltage VB at power fast rise time of the power supply, increases as a larger resistance value consisting of capacitance and R ₁ of a capacitor consisting of C _1, Q ₁
Turn on the transistor consisting of, and create the initial reference voltage. To operate stably with respect to the power supply rising time in the conventional circuit in consideration of time Thus voltage is turned on, C ₁
The capacitance of the capacitor consisting of R ₁ and the resistance value consisting of R ₁ were set large.

[0005]

In the conventional circuit described above, since the capacitance of the capacitor made up of C ₁ and the resistance value made up of R ₁ are made large, the initial reference voltage is stabilized by the stable operation when the power is turned on. Can be made.

On the other hand, on the other hand, in the field of FA where the power supply condition is bad, when the power supply drops instantaneously and the power supply voltage is restored again in a short time, the capacity of the capacitor composed of C ₁ and R ₁ Since the resistance value is large, the electric charge accumulated in C ₁ cannot be completely discharged, and the transistor formed by Q ₁ does not recover to the cutoff voltage, so that the output voltage VO is erroneously output. I would like to reduce the capacity of the capacitor composed of C ₁ and the resistance value composed of R ₁ , but as mentioned above, C ₁ and R ₁ at power-on and power-off
Since the constant conditions of are contradictory, it is difficult to set the constant in a power supply environment such as a power supply voltage instantaneous drop recovery.

[0007]

SUMMARY OF THE INVENTION The present invention provides a power supply reset circuit that solves the above-mentioned problems. The power supply reset circuit is a power-on reset circuit to which a capacitor forced discharge circuit is added. The purpose is to discharge the electric charge accumulated in the capacitor and accelerate the restoration of the base voltage of the transistor.

[0008]

According to such a circuit, first, when the power is turned on, the capacitor capacitance and the resistance value are set large, and the transistor is stably operated with respect to the power supply rising time to generate the initial reference voltage.

On the other hand, even when the power source voltage is instantaneously dropped, the capacity of the capacitor is large, but since the base voltage of the transistor is restored early by the forced discharge circuit, there is no erroneous output of the output voltage VO. Therefore, it is possible to cover both power supply environments not only when the power is turned on, but also under constant condition conditions where the capacitor capacity and the resistance value in the reset circuit conflict with each other, such as when the power is turned on again.

[0010]

Embodiments of the present invention will be described with reference to FIGS. FIG. 2 shows a circuit according to the present invention, and FIG. 3 shows a concrete example thereof. This receiving circuit is a receiving circuit composed of an ATC circuit including a power supply reset circuit including a C ₁ capacitor, an R ₁ resistor, a Q ₁ transistor, and a discharging circuit 3 and a comparator.

Transistor base voltage VB when power is turned on
Rises as the rise time of the power source is faster and the capacitance of the capacitor made up of C ₁ and the resistance value made up of R ₁ become larger, turning on the transistor made up of Q ₁ to create an initial reference voltage. Therefore, in consideration of the power-on time, the capacitance of the capacitor composed of C ₁ and the resistance value composed of R ₁ are set large in order to operate stably with respect to the power-on time.

Meanwhile, power is instantaneously lowered in such cutting, when the shorter time by the power supply voltage Madokafu return such re return occurs, Q ₁ by also forced discharge circuit with the capacitance of the capacitor consisting of C ₁ is greater By quickly recovering the base voltage VB of the transistor consisting of, the output voltage VO will not be erroneously output following the power supply voltage VCC. At this time, for example, a D ₁ diode may be used in the forced discharge circuit.

[0013]

By adding a forced discharge circuit to the conventional power-on reset circuit, the reset circuit operates normally even under the setting of circuit constants that conflict with power-on, such as recovery from a power supply voltage drop. No erroneous output of received output voltage is eliminated. In particular, it is effective in a receiving circuit under an environment where the power supply condition is bad such as FA field.

[Brief description of drawings]

FIG. 1 is a receiving circuit diagram including a conventional power-on reset circuit.

FIG. 2 is a receiving circuit diagram including a power supply reset circuit of the present invention.

FIG. 3 is a receiving circuit diagram including a power supply reset circuit as a specific circuit example of the present invention.

FIG. 4 is a diagram showing waveforms at various points in the conventional circuit shown in FIG. 1 and the circuits according to the present invention shown in FIGS. 2 and 3.

[Explanation of Codes] 1 ... Power-on reset circuit, 2 ... ATC circuit, 3 ... Capacitor forced discharge circuit, 4 ... Power supply reset circuit, 5 ... Comparator, VA ... Input voltage, VB ... Transistor base voltage, VR ... Reference Voltage, VO ... Output voltage, VCC ... Power supply voltage.

Claims (2)

[Claims] 1. A power supply reset circuit characterized by adding a capacitor forced discharge circuit to the power-on reset circuit to cope with a momentary drop in power supply voltage. 2. An optical transmission module, comprising the power supply reset circuit according to claim 1.