JPH0720929Y2 - High voltage semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a high breakdown voltage semiconductor device for high voltage switching, and more particularly to a high breakdown voltage semiconductor device improved so as to be capable of switching a high voltage in a small size.

<Prior Art> FIG. 4 is a configuration diagram showing a configuration of a conventional high withstand voltage MOS type FET. (A) is a partial plan view, (b) is a partial vertical cross-sectional view,
(C) shows the symbolic representation of the MOS type FET formed in (A) and (B), respectively.

10 low concentrations of P-type (P ^-) is a substrate of silicon semiconductor,
High-concentration P-type silicon (P ⁺ ) is diffused to the outermost part of the substrate 10 to form a connection portion 11 with the substrate 10, and high-concentration n-type silicon (n ⁺ ) is diffused to the inside to form a source. 12 are formed respectively.

Both the connecting portion 11 and the source 12 are connected to the source electrode S wired on them.

In the central part surrounded by the source 12, a high concentration of n-type silicon n ⁺
Is diffused to form a drain 13, and the drain 13 is wired by a drain electrode D.

The gate electrode G is arranged between the source 12 and the drain 13 and close to the source 12 so as to face the substrate 10 via an oxide film.

A drift layer 14 in which n-type silicon is diffused at a low concentration (n ⁻ ) is formed in a portion of the substrate 10 between the gate electrode G and the drain electrode D.

The above MOS type FET can be expressed as a general element symbol.
It becomes a MOS type FET Q _O as shown in Fig. (C).

When such a low-concentration drift layer 14 is provided, the drift layer functions as a drift region in the ON state, but functions as a depletion layer in the OFF state and can maintain a high breakdown voltage. With such a configuration, for example, 1000V
Although it is possible to obtain a high breakdown voltage, to obtain a higher breakdown voltage, these are connected in cascade as shown in FIG.

Next, FIG. 5 will be described. In this embodiment, the fourth
Switch from the switch power supply 15 between the shows, the gate electrode G and the source electrode S of the MOS type FETs Q _O1 case of three use of a MOS type FET having the structure shown in FIG Q _O1, Q _O2 and Q _O3 The voltage E _S is applied to turn on / off the MOS FET Q _O1 .

On the other hand, the MOS type FETs Q _O2 and Q _O3 are galvanically isolated via the voltage output type photo couplers PC ₂ and PC ₃ to control their gates.

<Problems to be Solved by the Invention> However, in such a conventional high breakdown voltage semiconductor device, for example, a MOS type FET shown in FIG. 4 has a limit to the high breakdown voltage, and as shown in FIG. In the case of cascade connection, the source potential of the added FET in the off state becomes a high voltage, so in order to control this FET, it is troublesome to insulate it in terms of direct current to provide the gate-source potential. Moreover,
Attempting to maintain a high breakdown voltage leads to a decrease in the degree of integration and an increase in cost due to an increase in the number of elements.

<Means for Solving the Problems> In order to solve the above problems, the present invention has a source and a drain formed on a silicon substrate and a gate connected between them via an insulating film. Further, a plurality of constituent elements composed of a MOS type FET having a low-concentration drift layer between the former silicon substrate portion facing the gate and the former drain and further having an auxiliary drain formed on the former drift layer are provided. The plurality of constituent elements are cascade-connected so that the auxiliary drain and drain of one constituent element are mutually connected to the gate and the source of the other constituent element, and the drain of the last constituent element is one end. The power source is connected to the other end of the load.

<Operation> An auxiliary drain is provided in the drift layer, and a potential change generated in the auxiliary drain and drain of the first element element by the switch voltage applied to the gate is directly applied to the gate and source of the second element element. The potential changes of the auxiliary drain and the drain of the second element element are applied to the gate and the source of the third element element, and these are successively propagated to turn on / off each element element.

<Embodiment> An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is an embodiment showing the essential part of the present invention. 1 (a) is a partial cross-sectional view, (b) is its electric circuit representation,
(C) shows the equivalent circuit representation of (B). In addition,
The parts having the same functions as those of the related art are designated by the same reference numerals and the description thereof will be appropriately omitted.

Reference numeral 15 is a low-concentration P-type silicon (P ⁻ ) substrate, and an auxiliary drain 16 in which high-concentration n-type silicon (n ⁺ ) is diffused in the vicinity of the drain electrode D in the drift layer 14.
Are formed by diffusion or the like. This auxiliary drain 16
An auxiliary drain electrode D ^- is laid on the top surface.

The substrate 15, the source 12, the auxiliary drain 16 and the gate electrode G form an N-channel MOSFET Q ₁ , and the substrate G, the source 16 and the drain 13 form an n-channel junction FET Q ₂ as the gate G ^−. is doing. Therefore, the source 12 of the MOS type FET Q ₁ is connected to the gate G ⁻ (substrate 15) of the junction type FET Q ₂ .

These are shown in Fig. 1 (b) as a connection representation of an electric circuit, but for simplicity, Fig. 1 (c) shows the MOS type FET Q ₁ and the junction type FET Q shown in Fig. 1 (b). ₂ and are collectively shown as an enhancement type MOS type FET Q _E.

Next, the operation of the MOS type FET Q _E configured as above will be described.

When the voltage V _GS between the gate / source of the MOS type FETs Q ₁ enhancement type is V _GS = 0 is, Q ₁ is a large portion of the voltage of the voltage V _DS is applied between the drain / source off Q ₁ source 12 (S) and the auxiliary drain 16 (D ^-) relates to a while, the gate electrode G of the junction FETs Q ₂ ^- the source 12 of Q ₁ (S)
And because at the same potential, Q ₂ of the source 16 (the auxiliary drain D ^-)
The gate electrode G ^- is the potential is in the negative potential, the potential negative is Q ₂ is also turned off when the turn-on voltage V _T less than the Q _2.

Therefore, both Q ₁ and Q ₂ are turned off, and the potential of the auxiliary drain 16 is determined as the potential at which the leak currents of Q ₁ and Q ₂ are equal. Therefore, in this case, even considering the vicinity of the withstand voltage of Q ₁ , there is always a potential difference between the drain 13 (D) and the auxiliary drain 16 (D ⁻ ).

FIG. 2 shows the essential parts of another embodiment of the present invention configured as a depletion type MOS FET. FIG. 2 (a) shows a case where it is expressed as an electric circuit, and (b) shows it by a symbol for simplicity.

Q ₁ ^- shows the case of constituting a MOS type FET having a depletion mode by doping impurities into the substrate under the gate, in this case the Q ₁ ^- between the gate electrode G and the source electrode S of the A gate protection diode D _i is inserted in. (B) is a depletion type MOS type F
Shown as ETQ _D.

Next, an embodiment in which a high breakdown voltage semiconductor device is configured by using the element elements of these MOS type FETs Q _E and Q _D will be described with reference to FIG.

17 is a power supply to be used for on / off use, and 18 is a load. A switch composed of MOS type FETs Q _E , Q _D1 , Q _D2, etc. is connected in series to the power supply 17 and the load 18.

Between the gate electrode G and the source electrode S of the MOS type FET Q _E ,
A switch voltage E _S is applied from the switch power supply 15, and its drain electrode D and auxiliary drain electrode D ⁻ are connected to the source electrode S and gate electrode G of the MOS type FET Q _D1 , respectively.

The drain electrode D and the auxiliary drain electrode D ⁻ of the MOS type FET Q _D1 are connected to the source electrode S and the gate electrode G of the MOS type FET Q _D2 , respectively.

The drain electrode D of the MOS type FET Q _D2 is connected to one end of the load 18.

In the above configuration, compared to the resistance of load 18, MOS type FET
The on-resistance of Q _E , Q _D1 and Q _D2 shall be negligible.

First, when Q _E is turned on by the application of the switch voltage E _S , the voltage between the drain electrode D and the auxiliary drain electrode D ⁻ becomes substantially zero, so that the voltage between the gate electrode G and the source electrode S of Q _D1 is The potential difference becomes almost zero, and Q _D1 turns on.

Similarly, Q _D2 is also turned on and turned on as a whole.

Next, when the MOS type FET Q _E is off, if a high voltage is applied, a potential difference occurs between the drain electrode D of Q _E and the auxiliary drain electrode D ^−, and this potential difference is the source electrode S of Q _D2. and is applied to the gate electrode G, Q _D2 is turned off since the potential difference is below the turn-on voltage V _T of Q _D2.

Similarly, Q _D2 is also turned off and turned off as a whole.

<Effects of the Invention> As described above in detail with the embodiments, the present invention has the following effects.

(B) Unlike conventional products, it can be connected in series without the need for a floating power supply, so it can be made inexpensive and compact.

(B) When insulation is performed using a photocoupler as in the related art, there is a problem that the switching time becomes long because the output resistance is large, but according to the present invention, switching can be performed at a higher speed than this.

() As in the prior art, when a photo coupler is used, the upper limit of the number of connections is determined by the withstand voltage of the photo coupler, but the present invention does not have such a limit, and any number can be arbitrarily connected.

[Brief description of drawings]

FIG. 1 is a block diagram showing an essential part of an embodiment of the present invention, FIG. 2 is an element block diagram showing an essential part of another embodiment of the present invention, and FIG. 3 is an overall view showing the entire structure of the present invention. FIG. 4 is a main part configuration diagram showing a main part of a conventional high breakdown voltage semiconductor device, and FIG. 5 is an overall configuration diagram showing an entire conventional high breakdown voltage semiconductor device. 10 ... Substrate, 11 ... Connection part, 12 ... Source, 13 ... Drain, 14 ... Drift layer, 15 ... Substrate, 16 ... Auxiliary drain, S ... Source electrode, D ... Drain electrode, G
...... gate electrode, D ^- ...... auxiliary drain electrode.

Claims (1)

[Scope of utility model registration request] 1. A source and a drain are formed on a silicon substrate, and a gate is formed between the source and the drain, which are coupled to each other through an insulating film. Further, a portion of the silicon substrate facing the gate and the drain. A plurality of MOS FET elements each having a low-concentration drift layer and further having an auxiliary drain formed on the drift layer, the plurality of elements being one auxiliary drain and drain, It is characterized in that the gates and sources of other components are cascade-connected to each other, and the drain of the last element is connected to the other end of the load whose one end is connected to the power supply. High voltage semiconductor device.