JPH07203453A - Context generator and coder using the same - Google Patents

Abstract

PURPOSE:To generate context data at a high speed only with shift operation by realizing the generation of a state identification number required for coding for each state by the coder, that is, a context with only a general-purpose arithmetic logic circuit and its peripheral hardware. CONSTITUTION:The coder used for a context generator is made up of, e.g. a 40-bit arithmetic logic circuit l, a 40-bit shifter 2, a data RAM 3 storing picture data whose word width is 16-bit, a register bank 4 being a register set of 40-bit, an address control section 5 controlling R/W of the bank 4, an address control section 6 controlling the RAM 3, and a microprogram control section 7 controlling the generation of a context. In order to activate the coder, i-th image data word of a line Y-2 is set to a high-order word of the register R1, (i+1)th image data are given to a low-order word of the register R1, picture data of a line Y-1 are set to the register R2 and i-th word of the picture line is given to a low-order word of the register R3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device for image data, and more particularly, to a coding symbol which is a pixel for a peripheral n pixel P0,
P1, ... State defined by Pn Si = (P
0, P1, ... Pn) and generates a state identification number Si (hereinafter, referred to as context) necessary for encoding each state.

[0002]

2. Description of the Related Art Conventionally, this type of device is required in a Markov model coding device using arithmetic code or the like. Before describing the context generation process in the conventional encoding device, the position of the context generation in the whole encoding process will be described. FIG. 12 is a schematic configuration diagram of a binary image Markov model encoder using arithmetic codes. The arithmetic code uses a binary point corresponding to the occurrence probability of the encoded symbol sequence as a code. Further, FIG. 13 shows an example of arrangement of coded symbols and reference pixels for constructing a Markov model, where "?" Is a symbol (pixel) to be coded, Y line is a processing line including the symbol,
After that, the Y-1 line is the previous line, the Y-2 line is the previous line, and each line has A as a reference pixel as shown.
~ J are included. The encoder shown in FIG. 12 includes a context generation unit 101, a probability estimation unit 102, a predicted value of a dominant symbol (MPS) and a probability estimation unit 1 for each context.
It is configured by a RAM (context table in this case) 103 for storing the state number 02 and an arithmetic encoder 104. In such an encoder, the context generation unit 101 arranges the reference pixels in an appropriate order (hereinafter, referred to as ABC order), and outputs the state identification signal.

[0003]

[Equation 1] Make n = 0 to (210-1). Since each pixel has two values for the state identification signal Sn, there are a total of 2 @ 10 values. The content * Sn of the context table corresponding to the context Sn is composed of the predicted value of the MPS and the state number of the probability estimation table (Qe table). That is,

[0004]

## EQU00002 ## * Sn = [MPS predicted value, Qe table state number] where * X represents the contents of the memory indicated by X. The arithmetically encoded data Ci of the i-th symbol is obtained as follows by a recursive arithmetic operation process using the content of the context table and the content of the probability estimation unit 102 (probability estimated value Qe) pointed to by the context table.

[0005]

## EQU00003 ## Ci = Ci-1 + f {MPS predicted value, Qe} = Ci-1 + f {* Sn, * [* Sn]} (1) Here, "+" is a communication process of code data and f is a code Representation algorithm. However, this is outside the scope of the invention and details are described in "ISO 11544 (JBIG)" or [CCITT Recommendation T. 82]. In order to efficiently execute such encoding processing, it is important to make the generation of the context Sn and the reading of * Sn efficient.

Conventionally, the generation of the context in this type of encoding device has been executed by using dedicated hardware or an arithmetic logic unit (ALU) of a general-purpose microprocessor. FIG. 14 is a block diagram showing dedicated hardware for generating a protect. Note that the specific configuration of such dedicated hardware is described in detail in Japanese Patent Laid-Open No. 4-6954. As shown in the figure, a plurality of line memories and a 1-bit delay element following the line memory are arranged so as to correspond to the arrangement of reference pixels, and the output of each delay element is used as an input signal of a dedicated register to form a context identification signal. To do.
When the encoding of one symbol is completed, the image data is moved to the right by 1
A new context is created by bit shifting.

FIG. 15 to FIG. 16 use a general-purpose ALU to
This is an example realized by program processing. FIG. 15 shows the arrangement of coded pixels (?) And reference pixels (A to J) on the memory. Given this state, a conventional processing example will be described according to the flow of FIG. In process 1401, the address of the word data including the reference pixel is calculated. The process 1402 is performed by the register R that creates a context.
Clear 1. In process 1403, the image data of word A is loaded into the register R1. In processing 1404, it is determined whether the pixel C is "1", and if it is "1", processing 14
At 05, the b2 bit of the register is set to "1". Here, the bits of the register R1 are b0, b1, and LSB from the LSB side.
b2, ..., b15. When the above processing is repeated for all the reference pixels, the context data is formed in the register R1. When the encoding of one pixel is completed,
The reference pixel position is calculated by processing 1401 and the above processing is repeated. In the microprocessor, processing 140
2, the processing 1403 and the processing 1405 can be executed in one machine cycle, but the condition judgment such as the processing 1404 usually takes 2 to 3 machine cycles. Then, in order to generate one context, at least 30 to 40 machine cycles are required even if the evaluation is performed excluding the processing 1401 and the like.

[0008]

The realization by the dedicated hardware configured as described above has problems such as an increase in circuit scale and an unrealizable cost at a low cost because a dedicated circuit is required at high speed. Occurs. Further, although the conventional configuration using the general-purpose ALU can solve the above-mentioned problems, a new problem that processing time is required arises.

The present invention has been made in view of the above problems, and a main object of the present invention is to provide an encoding device for generating a context at high speed by program processing using a general-purpose ALU.

[0010]

In order to solve the above problems, the present invention has a memory for storing a predetermined number of lines of image data and a capacity of at least twice the word width of this memory + a predetermined number of bits or more. A plurality of registers for inputting image data in units of words from the memory, and shift means for shifting the image data in the registers to the left and right in bit units to generate a state separation signal for encoding processing. It is equipped with and.

[0011]

With the above-described configuration, the encoding device of the present invention can realize the context generation only by the ALU and the hardware around it, so that the context data can be processed at high speed only by the shift operation without deteriorating the versatility of the hardware. Can be generated.

[0012]

1 is a block diagram of a circuit for executing a process for generating a context in an encoding apparatus according to the present invention. 1 is a 40-bit (40-bit in the present embodiment, but is not limited to this, and may be a predetermined number or more) ALU, 2 is a 40-bit (ALU
(The same as the above), 3 is a data RAM having a word width of 16 bits for storing image data, and 4 is 40 bits (A
A register bank, which is a collection of registers (similar to LU), will be described in detail later. Reference numeral 5 is an address control unit that controls the R / W of the register 4, 6 is an address control unit that controls access to the data RAM 3, and 7 is a microprogram control unit that controls operations in context generation. The control program is this microprogram. It is included in the control unit 7. In addition, 8 is a control bus and 9 is a data bus.

Further, FIG. 2 shows a detailed configuration of the register 4 of FIG. In FIG. 2, reference numeral 41 indicates a register configuration of the register bank 4. A 40-bit register has a lower word (0 to 15 bits) and an upper word (16 to 31 bits).
Bits) and extension bytes (32 to 39 bits). Reference numerals 42 and 43 are selectors, which select the data from the ALU 1 or the data from the data bus 9 and write them in the upper word and the lower word, respectively. Reference numeral 44 is a selector that selects and reads out data from the upper word and the lower word and outputs it to the data bus 9. These selectors 4
2, 43, and 44 make it possible to independently perform R / W (read / write) to the data RAM 3 or another register. The signals for controlling it are 45 to 47. These control signals are output from the address control unit 6 according to the above-mentioned microprogram.

FIG. 3 shows the internal structure of the data RAM 3. It is assumed that the state transition and the context table of the probability estimation unit are set in the areas A and B, respectively. In the area C, the image data has 3 lines (Y to Y-
2 lines) It is assumed that it has been input. ADP0-AD
P4 is a 16-bit address pointer, which is included in the address control unit 6.

Next, the operation of the coding apparatus according to the present invention will be described. FIG. 4 shows how to use the register. The upper word of the register R1 receives the i-th image data word of the Y-2 line, and the lower word thereof receives the (i + 1) th image data word. Similarly, the data of the Y-1 line is input to the register R2. Register R3 is R1, R
Unlike 2, the i of the Y line (processing line) is added to the lower word.
Enter the th image data word. With this arrangement, the reference pixels C, H, and G are located in the extension byte of each register as shown in FIG. , F, I, J will be located in the upper word of each register.

FIG. 5 is a flow chart showing the operation of the encoding process for one line. In process 401, one line of image data is externally input to the address indicated by ADP2 in FIG. In process 402, "0" is written in the address next to the last word on the data RAM. By this processing, the state of the line end is as shown in FIG. Register R in process 403
The data used for encoding the previous lines 1 to R3 are cleared, and the image data stored in ADP2 to ADP4 on the data RAM 3 is loaded into the register bank 4. Incidentally, the storage state of each register in the initial state is shown in FIG. Processes 402 and 403 are "0" outside the line data.
Is equivalent to In process 404, context data is created. Although the processings 405 to 407 are encoding processings, they are outside the scope of the present invention, and detailed description thereof will be omitted. 1
When the pixel coding is completed, in steps 408 to 410, the registers R1 to R3 are shifted to the left by 1 bit. Process 411
It is determined whether or not 16 symbols have been completed. If not completed, the process returns to the upstream of the process 404 and the above processes are repeatedly executed. As described above, the processes 404 to 410 are repeated 16 times. When the encoding for one word is completed, the image data is input to the lower words of R1, R2, and R3 by processes 412 to 414. At the judgment of processing 415,
The above process is repeated until the encoding of one line is completed.
When the encoding of one line is completed, the contents of the address pointer ADP2 are moved to ADP3 by processing 416, and AD
The contents of P3 are moved to ADP4, and the contents of ADP4 are ADP
Move to 2. By doing this, ADP2, ADP
3, the address indicated by ADP4 always indicates the processing line, the preceding line, and the preceding line.

Next, a concrete operation of the context data generation of the process 404 will be described with reference to FIGS. 8 and 9. Figure 8
FIG. 8 is a flowchart showing a first example of context generation of process 404. In this embodiment, the register R0 is used to generate context data. Register 501 in process 501
The contents of 1 are shifted to the right by 17 bits and written to R0. As a result, the contents of R0 are as shown at 701 in FIG. In process 502, R2 is shifted to the right by 13 bits and written in the upper word of R0. By this, R
0 becomes as indicated by 702 in FIG. Process 503 is R0
Is shifted to the right by 5 bits (703 in FIG. 9). Processing 50
4 writes the upper word of R3 to the upper word of R0 (704 in FIG. 9). In process 505, R0 is shifted to the left by 22 bits, and in process 506, it is shifted to the right by 30 bits.
At this time, "0" is entered from the left of R0,
Context data is generated in the lower word of R0 as shown by 706 in FIG. From the left and right when shifting with the shifter
The configuration that "0" is entered is not special. By writing this data in the address pointer ADP1 and referring to the content, the information necessary for encoding can be obtained. Each of the above processes can be executed in one machine cycle. Yes, processing can be performed faster than in the conventional example of Fig. 16. In Fig. 8, processes 502 and 504 are performed.
It is assumed that the upper word and the lower word can be accessed separately between the registers.

Next, a flow chart of FIG. 10 shows a processing example in which the upper and lower words of the register can be independently accessed only for the access between the register and the data RAM. In this flow chart, WRKA, WRKB, and WRKC are work areas set on the data RAM 3. Process 6
01 and processing 602, the pixels A and D are set to bit 1 respectively.
Move to position 6 and store in the work area. Processing 60
4, 605, the content of the register R0 becomes 701. By processing 606 and 607, R0 is 703
become that way. By the process 608, R0 becomes like 704. The process 609 and subsequent steps are the same as the process 505 and subsequent steps. Although the number of processes is larger than that of FIG. 8, the number of processing steps is smaller than that of the conventional example. In each of the embodiments, the bit judgment is not required, and the context data can be generated only by the shift operation.

Although the above embodiment is based on the reference pixel arrangement shown in FIG. 13, in an image having a high periodicity such as a dither image or a halftone dot image, the encoding performance can be improved by changing the arrangement of the reference pixels. . Here, the process of generating the context when the pixel D is moved to the encoded pixel on the Y line will be described. FIG. 11 is a processing flow chart showing this operation. Here, the pixel D is in the range of bits 18 to 39 of the register R3 in FIG. 4, and its bit position is represented by bn. Processing 1101 to 1106 are processing 501 to FIG.
Same as 506. By determining the value of bn in processing 1107 and rewriting b3 (position of D pixel) in processing 1108 and processing 1109, it is possible to efficiently generate the context even when the pixel D is moved within a certain range.

If the shift operation has a structure capable of shifting by connecting a plurality of registers, the above processing can be similarly executed by using a register or ALU having the same size as the word width of the image data. Also, the encoding method is not limited to the arithmetic code, and can be applied when the encoding process depends on the context Sn as in the above formula.

[0021]

As can be seen from the above description, the present invention does not require a dedicated circuit for generating a context,
This has an effect that a context can be efficiently generated by using a general-purpose arithmetic logic operation circuit (ALU). As a result, MPU (Micro
Processing Unit) and DSP (Dig)
The context signal generation processing can be executed at high speed by using the ital Signal Processor. Further, even when the encoding device is implemented by a dedicated LSI or the like, it can be efficiently executed by an ALU commonly used for other processing, and thus there is an effect that the circuit scale is reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a circuit that executes a process of generating a context in an encoding device of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a register 4 shown in FIG.

FIG. 3 is a diagram showing an internal configuration of a data RAM 3 shown in FIG.

FIG. 4 is a diagram showing a method of using a register in the present invention.

FIG. 5 is a flow chart showing the operation of one-line encoding processing according to the present invention.

6 is a diagram showing a state of a line end when the flow chart shown in FIG. 5 is executed.

FIG. 7 is a diagram showing a storage state of each register in an initial state.

FIG. 8 is a flowchart showing a first embodiment of context generation in the present invention.

9 is a diagram showing transition states of registers when the flow chart of FIG. 8 is executed.

FIG. 10 is a flowchart showing a second embodiment of context generation in the present invention.

FIG. 11 is a flowchart showing a third embodiment of context generation in the present invention.

FIG. 12 is a schematic configuration diagram of a binary image Markov model encoder using arithmetic codes.

FIG. 13 is a diagram showing an arrangement example of reference pixels for constructing a coded symbol and a Markov model.

FIG. 14 is a block diagram of dedicated hardware for generating a protect in a conventional encoding device.

FIG. 15 is a diagram showing the inside of a memory when a protect is generated by program processing in a conventional encoding device.

FIG. 16 is a flowchart of a case in which a context is generated by program processing in a conventional encoding device.

[Explanation of symbols]

 1 ALU 2 shifter 3 data RAM 4 register bank 5 address control unit 6 address control unit 7 micro program control unit

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Claims (6)

[Claims] 1. A memory for storing a predetermined number of lines of image data, and a plurality of memories each having a capacity of at least twice the word width of the memory + a predetermined number of bits or more, and inputting image data from the memory in word units. A context generation device comprising a register and shift means for generating a state separation signal for encoding processing by shifting image data in the register left and right in bit units. 2. A memory for storing a predetermined number of lines of image data, and a plurality of memories each having a capacity of at least twice the word width of the memory + a predetermined number of bits or more, and inputting image data from the memory in word units. A register, shift means for generating a state separation signal for encoding processing by shifting the image data in the register right and left in bit units, and clearing the register at the time of initial processing of each line and A context generation device having means for clearing data next to the last word of the image data stored in the memory. 3. A memory for storing a predetermined number of lines of image data, and a plurality of memories each having a capacity of at least twice the word width of this memory + a predetermined number of bits or more, and inputting image data from the memory in word units. A register, a shift means for generating a state separation signal for encoding processing by shifting the image data in the register right and left bit by bit, and a state before the change when the reference pixel arrangement is changed. A context generation device comprising a rewriting unit that generates a separation signal and rewrites only the bits whose arrangement has been changed. 4. The context generation device according to claim 3, wherein the pixel whose arrangement has been changed is made to exist on the same register as the pixel to be coded. 5. A memory for storing a predetermined number of lines of image data, a plurality of registers having a word width capacity of the memory, and a register group for inputting the image data in word units from the memory, and the register. A context generation device comprising shift means for generating a state separation signal for encoding processing by shifting image data in each register included in the group to the left and right in bit units. 6. A first memory for storing a predetermined number of lines of image data, and a capacity of at least twice the word width of this memory + a predetermined number of bits or more, and the image data is input in word units from the memory. A plurality of registers, shift means for generating a state separation signal for encoding processing by shifting image data in the registers to the left and right in bit units, and encoding according to each state separation signal. An encoding device comprising: means for outputting probability estimation data at time; and operation means for outputting code data by calculating encoded data of the image data and the probability estimation data.