JPH07203426A - Hierarchical coding and decoding device - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by simplifying horizontal and vertical resolution conversion. CONSTITUTION:A preliminary processing section 71 implements horizontal resolution conversion an original HDTV signal whose screen picture element number is MXN and whose valid picture element number is mXn to obtain an HDTV signal whose screen picture element number is KXL and whose valid picture element number is qXn (q<m). A down-sampling circuit 5 receives valid picture elements pXq being twice of an SDTV signal in horizontal and vertical directions and applies down-sampling to the signal to obtain the band HDTV signal. An UP-sampling circuit 11 recovers a low frequency band HDTV signal from the SDTV signal. A subtractor 12 subtracts the low frequency band signal from an output of the preliminary processing section 71. The low frequency band HDTV signal does not include components of pX(n-q) and the output of the subtractor 12 for this component is a full band HDTV signal. The original HDTV signal is recovered from the SDTV signal and the output of the subtractor 12. The preliminary processing section 71 and a post processing section 25 doe not require a vertical low pass filter, and then the circuit scale is reduced.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical coding / decoding apparatus, and more particularly to a hierarchical coding / decoding apparatus suitable for digital broadcasting and the like.

[0002]

2. Description of the Related Art In recent years, research on digital broadcasting has been conducted. The digital system has a steep threshold characteristic at the reception limit, and in an area where the reception state is poor, the amount of errors generated may be extremely increased, and reception may not be possible at all. Therefore, hierarchical coding for weighting video signals may be adopted so that necessary video information can be received without infinitely increasing the transmission rate. The video signal is hierarchically coded, a strong error correction code is added to the coded output of the higher priority layer, and the coded output of the lower priority layer is actively discarded.

For example, HDTV (High-Definition T
V) When transmitting a signal, this HDTV signal is
SDTV (Standard Definition) of CIR Recommendation 601
The encoded output up to the layer corresponding to TV) and the encoded output up to the layer corresponding to HDTV are separated and hierarchically encoded. The encoded output of each layer is multiplexed and transmitted. On the receiving side, by using a strong error correction code, the encoded output at least up to the hierarchy corresponding to SDTV can be surely decoded, and a monitor corresponding to SDTV, for example, a monitor for current NTSC broadcasting, can be used at the same level. To be displayed on a monitor with a resolution of. In addition, the HDTV image is displayed on the HDTV monitor by decoding the encoded output up to the hierarchy corresponding to HDTV.

FIG. 13 is a block diagram showing a conventional hierarchical coding / decoding apparatus for hierarchically coding and decoding such an HDTV signal. Further, FIG. 14 is an explanatory diagram for explaining the operation. In FIG. 14, halftone dots indicate the video signals in the entire band, diagonal diagonal lines to the right indicate horizontal and vertical low frequency video signals, and diagonal diagonal lines to the left indicate horizontal and vertical high frequency video signals.

The apparatus of FIG. 13 downsamples the HDTV signal by the hierarchical encoding unit 1 to obtain an encoded output corresponding to the SDTV signal. For example, in the hierarchical encoding unit 1, the number of horizontal pixels is P (= 1716) and the number of horizontal effective pixels is p (=
1440), the number of vertical lines is Q (= 1050), the number of vertical effective lines is q (= 960), and the frame frequency is f0.
(= 30 Hz) HDTV signal (eg, US ATV
(Adbanced Television) signal). The downsampling circuit 5 downsamples the HDTV signal to obtain an SDTV signal. Since the downsampling circuit 5 halves the horizontal and vertical bands and halves the horizontal and vertical pixel numbers, the SDTV signal from the downsampling circuit 5 has a horizontal pixel number of 858 and a horizontal effective pixel number. Is 720, the number of vertical lines is 525, the number of vertical effective lines is 480, and the frame frequency is 30 Hz.
It is based on CCIR Recommendation 601. This SDT
The V signal is a current NTSC television signal (horizontal pixel number 700, horizontal effective pixel number 640, vertical line number 52).
5, vertical effective lines 480, frame frequency 30
Hz).

By the way, it is conceivable to hierarchically encode an HDTV signal whose number of pixels is not an integral multiple of the number of pixels of the SDTV signal. The apparatus of FIG. 13 corresponds to this case, and for example, the number of horizontal pixels is M (= 2200) and the number of horizontal effective pixels is m (= 192) at the input terminal 4.
0), the number of vertical lines is N (= 1035), the number of vertical effective lines is n (= 1125), and the frame frequency is f0 (= 3).
An HDTV signal of 0 Hz (hereinafter referred to as an original HDTV signal) is supplied. The pre-processing unit 6 thins out the original HDTV signal in the horizontal and vertical directions and limits the band. As a result, the original HDTV signal having the number of pixels and the number of lines shown in FIG.
Is converted into the HDTV signal shown in FIG. 14B and given to the hierarchical encoding unit 1.

The hierarchical encoder 1 includes a downsampling circuit 5, an encoder 7, a buffer 8, a decoder 10, an upsampling circuit 11, a subtractor 12, an encoder 13 and a buffer 14.
And a multiplex circuit (hereinafter referred to as MPX) 9. FIG. 15 is a block diagram showing a specific configuration of the downsampling circuit.

The clocks φ1 and φ2 supplied to the downsampling circuit 5 are generated by the clock generating circuit 15. The clock generation circuit 15 generates clocks .phi.1 to .phi.4 having different frequencies based on the synchronizing signal input via the terminal 16. The horizontal low-pass filter 31 of the down-sampling circuit 5 is supplied with the HDTV signal shown in FIG. The horizontal low-pass filter 31 operates according to the clock φ1, passes the horizontal low band of the HDTV signal, and supplies it to the vertical low-pass filter 32. The vertical low-pass filter 32 operates at clock φ1 and
The vertical low frequency band of the TV signal is passed and output to the memories 33 and 34.

The output signal of the vertical low pass filter 32 is written in the memory 33 and the memory 34 at the clock φ1 and read at the clock φ2. Memory 33, memory 34 clock φ1
By the memory control circuit 35 operating in step 1, when one is in the read mode, the other is in the write mode. The memories 33 and 34 hold horizontal and vertical low-frequency HDTV signals. By setting the clock φ2 to a frequency of, for example, 1/2 times that of the clock φ1, the data held in the memories 33 and 34 is decimated to 1/2 and read. As a result, the SDTV signal shown in FIG. 14C is obtained at the output terminal 36. That is, this SDTV signal has 85 horizontal pixels.
8, the number of horizontal effective pixels is 720, the number of vertical lines is 525,
Vertical effective line number is 480, frame frequency is 30Hz
The horizontal and vertical bands are 1/2 of the HDTV signal.

This SDTV signal is given to the encoder 7.
The encoder 7 is controlled by the control signal output from the buffer 8 and operates with the clock φ 2 output from the clock generation circuit 15. The encoder 7 encodes the STDV signal and outputs it to the MPX 9 via the buffer 8 as a coded output of a layer with a high priority, and a decoder for creating a coded output of a layer with a low priority. Output to 10. The buffer 8 takes in the signal at the clock φ 2 output from the clock generation circuit 15 and outputs the encoded output of the SDTV signal at a constant rate based on the clock φ 3. In addition,
The encoder 7 is designed to add a strong error correction code to surely correct an error during transmission.

On the other hand, the upsampling circuit 11 is also supplied with clocks φ1 and φ2 from the clock generating circuit 15. Figure 1
6 is a block diagram showing a specific configuration of the upsampling circuit.

The SDTV signal is given to the memory 42 and the memory 43 via the terminal 41. The memory 42 and the memory 43 are configured such that when one of them is in the read mode, the other is in the write mode by the memory control circuit 44 which operates at the clock φ1. The memories 42 and 43 take in the data at the clock φ2 and output the data at the clock φ1. As described above, the frequency of the clock φ1 is twice the frequency of the clock φ2, and when the pixel data of the SDTV signal is read out, 0 data is inserted between the pixels and read out from the memories 42 and 43. It As a result, the SDTV signal is converted into a signal having twice the number of pixels. The outputs of the memories 42 and 43 are given to the vertical low-pass filter 45 which operates with the clock φ1 and band-limited to the vertical low band. Further, the output of the vertical low-pass filter 45 is given to the horizontal low-pass filter 46 operating at the clock φ1 to pass the horizontal low band.

That is, the SDTV signal is interpolated by the upsampling circuit 11, and the number of horizontal pixels is 1716 and the number of horizontal effective pixels is 144 from the upsampling circuit 11.
0, 1050 vertical lines, 96 vertical effective lines
0, the frame frequency is 30 Hz, and horizontal and vertical low frequency signals can be obtained. This signal has the same number of pixels as the HDTV signal as shown in FIG. 14 (e), and is a signal of horizontal and vertical low frequencies (hereinafter referred to as low frequency HDTV signal) as shown by the diagonally right diagonal line in the figure. is there. This low frequency HDTV signal is given to the subtractor 12.

The subtractor 12 receives the H of the entire band from the pre-processing unit 6.
The DTV signal (FIG. 14B) is also input. Subtractor
12 has a horizontal pixel number of 1716 and a horizontal effective pixel number of 14 by subtracting the low-frequency HDTV signal from the HDTV signal.
40, 1050 vertical lines, 9 vertical effective lines
60, a frame frequency of 30 Hz, and horizontal and vertical high frequency signals (hereinafter referred to as high frequency HDTV signals) (see FIG. 14).
(D)) is obtained.

The high frequency HDTV signal from the subtractor 12 is given to the encoder 13. The encoder 13 is controlled by the control signal output from the buffer 14 and operates at the clock φ 1 to encode the high frequency HDTV signal and output it to the buffer 14. The buffer 14 takes in the signal at the clock φ1 and outputs the signal at a constant rate based on the clock φ4. The output of the buffer 14 is given to the MPX9.

The MPX 9 multiplexes the coded output of the SDTV signal from the buffer 8 and the coded output of the high frequency HDTV signal from the buffer 14 and sends it to the transmission system 3. The signal from the transmission system 3 is input to the demultiplexing circuit (hereinafter referred to as DEMPX) 17 of the hierarchical decoding unit 2 and also to the clock recovery circuit 24. Clock recovery circuit 24
Are clocks φ0, φ1, φ2, φ3 from the input signal.
, Φ4 is played.

The DEMPX17 transmits the transmitted signal to a high frequency HD.
The encoded output of the TV signal and the encoded output of the SDTV signal are separated and output to the buffers 22 and 18, respectively. Buffer 18
Takes in the signal at the clock φ3 output from the clock regeneration circuit 24 and outputs the signal at the clock φ2. The encoded output of the SDTV signal from the buffer 18 is given to the decoder 19. The decoder 19 operates at the clock φ 2 and corrects the encoded output of the SDTV signal after error correction, and then decodes the SDTV signal and outputs it.
The SDTV signal shown in (c) is reproduced. By giving this SDTV signal to the SDTV monitor 27,
Current NTS with 480 effective scan lines on monitor 27
An SDTV image with the same resolution as the C video is displayed.

The SDTV signal from the decoder 19 is also provided to the upsampling circuit 20. The upsampling circuit 20 is the upsampling circuit 11 (FIG. 16) on the transmission side.
The configuration is similar to that of (1), and the signal is taken in by the clock φ2 output from the clock recovery circuit 24 and output by the clock φ1. That is, the upsampling circuit 20 doubles the number of pixels of the SDTV signal to obtain the low-frequency HDTV signal shown in FIG. This low frequency HDTV signal is an adder
Given to 21.

On the other hand, the buffer 22 has a clock recovery circuit 24.
The encoded output of the high frequency HDTV signal is taken in by the clock φ4 output from the and output at the clock φ1. Buffer 22
The encoded output of the high-frequency HDTV signal output from is supplied to the decoder 23. The decoder 23 operates at the clock φ1, decodes the encoded output of the input high frequency HDTV signal and outputs the high frequency HDTV signal shown in FIG. 14 (d) to the adder 21.

The adder 21 is a high frequency HDTV signal from the upsampling circuit 20 and a high frequency HDTV signal from the decoder 23.
By adding the signal and the signal, an HDTV signal in the entire band shown in FIG. 14B is obtained and output to the post processing unit 25. That is, the HDTV signal from the hierarchical decoding unit 2 has a horizontal pixel number P (= 1716) and a horizontal effective pixel number p (= 144).
0), the number of vertical lines is Q (= 1050), the number of vertical effective lines is q (= 960), and the frame frequency is f0 (= 30).
Hz).

The post-processing unit 25 performs the reverse process of the pre-processing unit 6 on the transmitting side. That is, the post processing unit 25 uses the HDT
14A, the number of horizontal pixels is 2200, the number of horizontal effective pixels is 1920, the number of vertical lines is 1035, and the number of vertical effective lines is 1125, as shown in FIG.
The original HDTV signal having a frame frequency of 30 Hz is reproduced. The original HDTV signal is supplied to the HDTV monitor 26. Thus, on the screen of the HDTV monitor 26, as shown in FIG.
The image of (a) is displayed.

By the way, the device of FIG. 13 has a simple integer ratio of the number of pixels to the number of pixels of the SDTV signal in order to simplify the configurations of the downsampling circuit 5 and the amplifier sampling circuits 11 and 20. HDTV signals are used as input / output. Therefore, it is necessary to convert the number of pixels by the pre-processing unit 6 and the post-processing unit 25. FIG. 17 is a block diagram showing a specific configuration of the pre-processing unit 6 and the post-processing unit 25. FIG. 17A shows the pre-processing unit,
FIG. 17B shows the post processing unit.

The original HDTV signal (FIG. 14 (a)) input to the pre-processing unit 6 is first a horizontal low-pass filter operating with the clock φ0 output from the clock generation circuit 15.
51 and then to a vertical low pass filter 52 operating with clock φ 0. The horizontal and vertical low pass filters 51 and 52 limit the horizontal and vertical bands. The output of the vertical low pass filter 52 is given to the memory 53 and the memory 54. The memory 53 and the memory 54 are controlled by the memory control circuit 55 operating at the clock φ0, and when one is in the read mode, the other is in the write mode. The memories 53 and 54 take in a signal using the clock φ0 and output a signal using the clock φ1.

FIG. 18 is a timing chart for explaining writing and reading of the memories 53 and 54. FIG.
18A shows the original HDTV signal from the vertical low-pass filter 52, and FIG. 18B shows the write control of the memory 53.
FIG. 18C shows the read control of the memory 53.
18D shows the write control of the memory 54, FIG. 18E shows the read control of the memory 54, and FIG. 18F shows the HDTV.
Shows the signal.

The period T1 in FIG. 18A corresponds to one frame or one field period of the original HDTV signal output from the vertical low pass filter 52, and the period T2 corresponds to one line period. The period T3 corresponds to a video signal period and the period T4 corresponds to a blanking period. The write control signals shown in FIGS. 18B and 18D are applied to the memories 53 and 54, respectively. The memories 53 and 54 are write-enabled by the write control signal at a high level (hereinafter referred to as “H”) to perform writing, and the original H for one frame or one field is written.
Store the DTV signal. That is, the original HDTV signal is as shown in FIG.
By the write control signal of 8 (b), the video signal period T3
During this period, the data is written in the memory 53 at the clock φ0. Similarly,
The memory 54 is written at the clock φ0 by the write control signal shown in FIG. The clock φ0 is a frequency based on the number of pixels of the original HDTV signal.

On the other hand, the memories 53 and 54 are respectively shown in FIG.
The read control signals shown in (c) and (e) are also given.
The memories 53 and 54 are read-enabled by the read control signal at a high level (hereinafter referred to as “H”) to perform reading, and the original H for one frame or one field stored.
Output a DTV signal. That is, the original HDTV signal written in the memories 53 and 54 is read at the clock φ1 during the period T6 by the read control signal of FIGS. 18 (c) and 18 (e). The period T6 corresponds to a video signal period for one line of the HDTV signal, and the period T7 corresponds to a blanking period.

In this case, the frequency of the clock φ1 is H
It is set based on the number of pixels of the DTV signal, and the original HD
Effective pixel in horizontal and vertical direction of TV signal (1920 × 1
Predetermined pixel data is thinned out from (035), and only effective pixels of horizontal pixel 1440 × vertical pixel 1050 are read out. Thus, the HDTV signal shown in FIG. 18 (f) appears at the output terminal 56. That is, the original HDTV shown in FIG.
The signal is converted into the HDTV signal shown in FIG.

In the post processing unit 25 shown in FIG. 17B, the HDTV signal from the hierarchical decoding unit 2 is input to the input terminal 60.
Is given to the memories 61 and 62 via. The memory 61 and the memory 62 are controlled by the memory control circuit 63 operating at the clock φ0, and when one is in the read mode, the other is in the write mode. The memories 61 and 62 read the HDTV signal at a clock φ1 based on the number of pixels of the HDTV signal and output the signals at a clock φ0 based on the number of pixels of the original HDTV signal.

FIG. 19 is a timing chart for explaining writing and reading in the memories 61 and 62. FIG. 19
FIG. 19A shows an HDTV signal to be input, and FIG.
19C shows a write control signal of the memory 61, FIG. 19C shows a read control signal of the memory 61, and FIG.
19 (e) shows the read control signal of the memory 62, and FIG. 19 (f) shows the original HDTV signal. Note that the period T1 corresponds to one frame or one field period and the period T2 corresponds to one line.
The period T3 corresponds to a video signal period and the period T4 corresponds to a blanking period.

The memory 61 is supplied with the write control signal of FIG. 19 (b) and the read control signal of FIG. 19 (c). The memory 61 is write-enabled when the write control signal is "H", and fetches the HDTV signal from the hierarchical decoding unit 2 at the clock φ1 during the write-enable period, that is, the period T3 corresponding to the video signal. In addition, in the memory 62, FIG.
The write control signal of (d) and the read control signal of FIG. The memory 62 is write-enabled by the control signal "H" for the writing of FIG.
Capture HDTV signal with. In this way, the HDTV signals for one frame or one field period are written alternately in the memories 61 and 62.

On the other hand, during the "H" period of the read control signal shown in FIGS. 19 (c) and 19 (e), the memories 61 and 62 are read enable. That is, the HDT written in the memories 61 and 62
The V signal is a video signal period of the original HDTV signal (see FIG. 19).
In periods T6 of (c) and (e), the data is read from the memories 61 and 62 at the clock φ0. As described above, the clock φ0 corresponds to the number of pixels of the original HDTV signal, and the memories 61 and 62 insert 0 data corresponding to the data thinned out in the pre-processing unit 6. As a result, the memory 61,
As shown in FIG. 19 (f), a signal having a horizontal and vertical effective pixel number of 1920 × 1035 is output from 62. The period T5 corresponds to one line period of the original HDTV signal, the period T6 corresponds to a video signal period, and the period T7 corresponds to a blanking period.

The outputs of the memories 61 and 62 are supplied to the horizontal low pass filter 64 and then to the vertical low pass filter 65. The horizontal low pass filter 64 and the vertical low pass filter 65 interpolate the outputs of the memories 61 and 62 by operating at the clock φ0 and limiting the band. Thus, the original HDTV signal (FIG. 14A) having the number of horizontal pixels of 2200, the number of horizontal effective pixels of 1920, the number of vertical lines of 1035, the number of vertical effective lines of 1125, and the frame frequency of 30 Hz appears at the output terminal 66. .

As described above, the pre-processing unit 6 and the post-processing unit 25 perform substantially the same processing as the down-sampling circuit 5 and the up-sampling circuits 11 and 20, respectively. However, in the pre-processing unit 6 and the post-processing unit 25, the number of pixels after horizontal and vertical resolution conversion by down-sampling processing and up-sampling processing is not a simple integer ratio with respect to the number of pixels before conversion. Therefore, there is a problem that a large-scale circuit must be used as the horizontal and vertical low pass filters of the pre-processing unit 6 and the post-processing unit 25.

[0034]

As described above, the conventional layered coding / decoding apparatus described above has a simple ratio of the resolution of a signal of a layer having a high priority to the resolution of a signal of a layer having a low priority. If the ratio is not an integer, horizontal and vertical resolution conversion is performed by pre-processing and post-processing, and there is a problem that the circuit scale is extremely increased.

It is an object of the present invention to provide a hierarchical coding / decoding device capable of significantly reducing the circuit scale by simplifying the horizontal and vertical resolution conversion without substantially degrading the image quality. To do.

[Structure of the Invention]

A hierarchical coding / decoding apparatus according to the present invention has a horizontal pixel number of K, a horizontal effective pixel number of m,
The number of vertical lines is L, and the number of vertical effective lines is n (K, m,
A television signal of L and n is a natural number, and p of horizontal effective pixels (p is a natural number of m or less) pixels and q of vertical effective lines (q is a natural number of n or less) lines. Down-sampling means for down-sampling the portion of q, first encoding means for encoding and transmitting the output of the down-sampling means, up-sampling means for up-sampling the output of the down-sampling means, and the television Subtracting means for obtaining a high-frequency component for the p × q portion of the television signal and obtaining a full-band component for the other portion by obtaining the difference between the television signal and the output of the up-sampling means,
Second encoding means for encoding and transmitting the output of the subtracting means is provided.

[0037]

In the present invention, the downsampling means is
Down-sample the p × q portion of the television signal. By making this p × q resolution correspond to the resolution of the SDTV image, the circuit scale of the downsampling means is reduced. The upsampling means obtains a low frequency television signal by upsampling the output of the downsampling means. The subtracting means subtracts the output of the amplifier sampling means from the television signal. High-frequency components of the television signal are obtained for portions other than p × q of the television signal. For the other part of the television signal, a full-band television signal is obtained. On the decoding side, a signal corresponding to the output of the downsampling means and the output of the subtraction means is obtained to display a television image with the number of effective pixels m × n.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a hierarchical coding / decoding apparatus according to the present invention. In FIG.
The same components as those in No. 3 are designated by the same reference numerals. In this embodiment, the number of horizontal pixels is 2200, and the number of horizontal effective pixels is 192.
0, 1125 vertical lines, 10 vertical effective lines
35, which can support hierarchical coding and decoding of HDTV signals having a frame frequency of 30 Hz.

At the input terminal 4, as the original HDTV signal,
H of horizontal pixel number M, horizontal effective pixel number m, vertical line number N, vertical effective line number n, frame frequency f0
Input DTV signal. For convenience of explanation, the number of horizontal pixels M = 2200 and the number of effective horizontal pixels m = 1 as in the conventional case.
920, the number of vertical lines N = 1125, the number of vertical effective lines n = 1035, and the frame frequency f0 = 30 Hz, and the signal of the CCRI recommendation 601 (horizontal pixel number U = 858, horizontal effective pixel number u = 720) as an SDTV signal. ,
Vertical line number V = 525, vertical effective line number v = 48
0 and the frame frequency is f0 = 30 Hz).

This original HDTV signal is given to the pre-processing section 71 via the input terminal 4. In the present embodiment, the pre-processing unit 71 is composed of a horizontal low pass filter 72, a memory 73, a memory 74 and a memory control circuit 75. The pre-processing unit 71 is adapted to perform horizontal resolution conversion to reduce only the number of horizontal pixels of the original HDTV signal.

The horizontal low-pass filter 72 is supplied with the clock φ 0 from the clock reproducing circuit 15. The clock reproducing circuit 15 is adapted to generate clocks φ0 to φ4 based on the synchronizing signal inputted from the terminal 16. The clock φ0 is set to a frequency corresponding to the number of pixels of the original image signal. The horizontal low-pass filter 72 operates according to the clock φ0 to limit the band of the original HDTV signal and store it in the memory 7
It is designed to output to 3,74.

The output of the horizontal low-pass filter 72 is the memory 73.
And the memory 74. The memories 73 and 74 are controlled by the memory control circuit 75. Memory control circuit 75
Operates with the clock φ 0 output from the clock generation circuit 15, and when one of the memories 73 and 74 is in the read mode, the other is in the write mode. The memories 73 and 74 are adapted to write the input signal using the clock φ0 in the write mode and read the signal stored in the read mode using the clock φ1.

FIG. 2 is a timing chart for explaining writing and reading of the memories 73 and 74 in FIG. 2A shows the original HDTV signal, and FIG. 2B shows the memory.
FIG. 2C shows the write control of the memory 73, FIG. 2C shows the read control of the memory 73, FIG. 2D shows the write control of the memory 74, and FIG. Two
(F) shows an HDTV signal. Period T1 in FIG.
Corresponds to one frame or one field period, and the period T2
Corresponds to one line period. The period T3 corresponds to a video signal period and the period T4 corresponds to a blanking period.

Memories 73 and 74 are shown in FIGS. 2B and 2D, respectively.
Write enable is enabled by the write control signal "H" shown in FIG. 2, and the read control signal "H" shown in FIGS.
Read enable is enabled.

The original HDTV signal shown in FIG. 2A is converted by the memory control circuit 75 into, for example, a memory during the period T1 of FIG.
Written in 73. The clock φ 0 corresponds to the number of pixels of the original HDTV signal, and as shown in FIG.
Stores all pixel data for one frame or one field of the original HDTV signal by using the clock φ0.
Similarly, during the reading period of the memory 73, the memory 74 stores all pixel data for one frame or one field of the original HDTV signal, as shown in FIG.

The data stored in the memories 73 and 74 are as shown in FIG.
Reading is performed during the "H" period of the read control signal shown in (c) and (e). During the "H" period T6 of the read control signal, the SDT
HD composed of twice the number of pixels horizontally and vertically as the V signal
TV signal (horizontal pixel number P = 1716, horizontal effective pixel number p
= 1440, the number of vertical lines Q = 1050, and the number of vertical effective lines q = 960).

From memories 73 and 74, clocks φ0 and φ1
Of the original HDTV signal based on the frequency ratio of m (192
0) × n (1035) effective pixels, p (144
0) × n (1035) pixel data is read. That is, the thinning out is performed in the horizontal direction by the reading of the memories 73 and 74, but not in the vertical direction. However, based on the frequency ratio of the clocks φ 0 and φ 1, the memories 73, 74
Can read only pixel data of 1050 lines in the vertical direction. Even in this case, all the data on the vertical effective lines (1035 lines) of the original HDTV signal are read out.

The output of the pre-processing unit 71 is HD after resolution conversion.
It is output to the hierarchical encoding unit 1 as a TV signal. Note that the period T5 corresponds to one line period of an HDTV signal, the period T6 corresponds to a video signal period, and the period T7 corresponds to a blanking period. Thus, the pre-processing unit 71 causes the number of horizontal pixels K = 171.
6, horizontal effective pixel number p = 1440, vertical line number L = 1
An HDTV signal having 050, the number of vertical effective lines n = 1035, and a frame frequency f0 = 30 Hz is obtained.

On the other hand, as described above, the pre-processing unit 6 of the conventional example has the HDTV signal (horizontal pixel number P = 1716, horizontal pixel number P = 1716, which is twice the number of pixels in the horizontal and vertical directions of the original HDTV signal) as the SDTV signal. (Number of horizontal effective pixels p = 1440, number of vertical lines Q = 1050, number of vertical effective lines q = 960)
Had been converted to.

That is, in the pre-processing unit 71 of the present embodiment, the horizontal resolution conversion processing is the same as in the conventional example,
The number of horizontal pixels of the converted HDTV signal is K = P = 1716
Therefore, the horizontal effective pixel number p is 1440. On the other hand, in the vertical direction, the original HDTV signal is read as it is, and the number of vertical lines of the converted HDTV signal is Q = K (=
1050), but the number of vertical effective lines is q (= 96).
It is n (= 1035) instead of 0). That is, the following expression (1) is established. Since the thinning is performed only in the horizontal direction, the converted image is a vertically long image.

K × L = P × Q, p × n <P × Q <m × n (1) The hierarchical encoding unit 1 has the same configuration as the conventional configuration shown in FIG. That is, the hierarchical encoding unit 1 determines the number of horizontal pixels P = 171.
6, horizontal effective pixel number p = 1440, vertical line number Q = 1
It has the ability to process HDTV signals of 050, the number of vertical effective lines q = 960, and the frame frequency f0. That is, the hierarchical encoding unit 1 uses the sampling frequency fs = P ×
It has the ability to process signals sampled at Q × f0 and processes signals with twice the horizontal and vertical resolution of SDTV signals.

The structure of the down-sampling circuit 5 of the hierarchical encoder 1 is the same as that of FIG. That is, the downsampling circuit 5 uses the clock φ 1 having a frequency based on the number of pixels of the input HDTV signal to input the HDTV signal.
It has a horizontal low-pass filter 31 and a vertical low-pass filter 32 that reduce the horizontal and vertical bands of the signal. Also,
The Dow sampling circuit 5 has memories 33 and 34, writes the HDTV signal in the memories 33 and 34 using the clock φ1, and clocks φ having a frequency based on the number of pixels of the SDTV signal.
2 has a memory control circuit 35 for reading from the memories 34, 35. As a result, the downsampling circuit 5 converts the HDTV signal into an SDTV signal and outputs it to the encoder 7.

That is, the memory of the downsampling circuit 5
33 and 34 hold all horizontal effective pixels p = 1440 of the input HDTV signal in the horizontal direction. On the other hand, the memory 33,
34, in the vertical direction, the number of vertical effective lines q out of the total number of vertical effective lines n = 1035 of the input HDTV signal.
= 960 is held. That is, the data of only the p × q portion which is twice the number of horizontal and vertical pixels of the SDTV signal is held. Therefore, for example, p above and below the input HDTV signal
The data of the × (n−q) portion is truncated when converted into the SDTV signal.

The memory control circuit 35 uses the number of horizontal effective pixels u (= 720 <of the data stored in the memories 33 and 34).
p), the data of the vertical effective line number v (= 480 <q) is read. By this thinning-out, the down-sampling circuit 5 causes the horizontal pixel number U = 858 and the horizontal effective pixel number u = 72.
0, vertical line number V = 525, vertical effective line number v = 4
80, SDTV signal of frame frequency f0 = 30 Hz is obtained.

The encoder 7 is controlled by the control signal output from the buffer 8 and operates with the clock φ 2 output from the clock generation circuit 15 to encode the SDTV signal. The encoded output of the encoder 7 is the buffer 8 and the decoder.
Given to 10. The buffer 8 takes in the encoded output of the SDTV signal at the clock φ 2 output from the clock generation circuit 15 and MPs the signal at a constant rate based on the clock φ 3.
Output to X9.

The decoder 10 operates with the clock φ 2 output from the clock generation circuit 15, decodes the encoded output of SDTV and outputs it to the upsampling circuit 11.
The configuration of the upsampling circuit 11 is the same as that in FIG.

The upsampling circuit 11 stores the SDTV signal from the decoder 10 in the memory by using the clock φ 2 having a frequency based on the number of pixels of the SDTV signal, and outputs the HDT signal to the HDT.
Data is read from the memory by using a clock φ1 having a frequency based on the number of pixels of the V signal. The upsampling circuit 11 interpolates the data read from the memory by band limiting horizontally and vertically. Thus, from the upsampling circuit 11, the horizontal pixel number K (> U) and the horizontal effective pixel number p
(> U), the number of vertical lines L (> V), the number of vertical effective lines q (> v), and the low frequency component of the HDTV signal having the frame frequency f0. The low frequency HDTV signal from the upsampling circuit 11 is given to the subtractor 12.

The subtractor 12 uses the HDTV from the pre-processing unit 71.
The signal is also given, and the subtractor 12 outputs the low frequency H from the HDTV signal.
By subtracting the DTV signal, the high frequency component of the HDTV signal is obtained and output to the encoder 13. As described above, the HDTV signal from the pre-processing unit 71 has the number of horizontal pixels K = 17.
16, horizontal effective pixel number p = 1440, vertical line number L =
1050, the number of vertical effective lines n = 1035, and the frame frequency f0 = 30 Hz, and the low-frequency HDTV signal from the upsampling circuit 11 has a horizontal pixel number K = 1716, a horizontal effective pixel number p = 1440, It is the low frequency component of the signal with the number of vertical lines L = 1050, the number of vertical effective lines q = 960, and the frame frequency f0 = 30 Hz. That is, the output of the subtractor 12 is the effective pixel p (=
1440) × n (1035), the p × q (960) portion becomes a high-frequency HDTV signal, and the remaining p
The portion of (1440) × (nq) (75) becomes the HDTV signal in the entire band including the low band.

The high band HDTV signal including the low band from the subtracter 12 is supplied to the encoder 13. The encoder 13 is a buffer
It is controlled by the control signal output from 14 and operates by the clock φ 1 output from the clock generation circuit 15 to encode the high frequency HDTV signal including the low frequency and output it to the buffer 14. The buffer 14 takes in the encoded output of the high frequency HDTV signal including the low frequency with the clock φ1 output from the clock generation circuit 15 and outputs the signal at a constant rate based on the clock φ4. The output of the buffer 14 is given to the MPX9.

The MPX 9 is a low frequency HDT from the buffer 8.
The encoded output of the V signal and the encoded output of the high frequency HDTV signal including the low frequency from the buffer 14 are multiplexed and sent to the transmission system 3. The output of the MPX 9 is input to the hierarchical decoding unit 2 and the clock recovery circuit 24 via the transmission system 3. The clock recovery circuit 24 uses clocks φ0, φ1, φ
Generates 2, φ3, and φ4.

The structure of the hierarchical decoding unit 2 is the same as the conventional one.

That is, the DEMPX 17 of the hierarchical decoding unit 2 is
The input signal is separated into an encoded output of a high frequency HDTV signal including a low frequency band and an encoded output of an SDTV signal. SDT
The encoded output of the V signal is given to the decoder 19 via the buffer 18. The buffer 18 takes in a signal at the clock φ3 output from the clock reproduction circuit 24 and outputs the signal at the clock φ2. The decoder 19 operates with the clock φ 2 output from the clock reproduction circuit 24 and decodes the encoded output of the SDTV signal. The decoded SDTV signal has horizontal pixel number U = 858, horizontal effective pixel number u = 720, vertical line number V = 525, vertical effective line number v = 480, and frame frequency f0 = 30 Hz. S from the decoder 19
The DTV signal is supplied to the upsampling circuit 20 and also to the vertical n → q conversion circuit 86.

The vertical n → q conversion circuit 86 operates with the clock φ 2 output from the clock recovery circuit 24, and the decoder 19
The scanning line number conversion for converting the n scanning lines into the q scanning lines is performed on the SDTV signal from. This allows vertical n
The output signal of the → q conversion circuit 86 is the number of horizontal pixels U = 858,
Horizontal effective pixel number u = 720, vertical line number V = 525,
An image extended in the vertical direction after being converted into an SDTV signal having a vertical effective line number v × q / n = 445 and a frame frequency f0 = 30 Hz returns to a normal image.

The output of the vertical n → q conversion circuit 86 is given to the SDTV monitor 27 and displayed on the display screen. In addition,
This SDTV image is an original HDTV image in which, for example, the upper and lower parts are slightly missing. When the SDTV monitor 27 can control vertical deflection, the vertical n → q conversion circuit 86 is omitted and the output of the decoder 19 is directly output to the SDTV monitor 27.
To display a normal image.

On the other hand, the upsampling circuit 20 has the same structure as the upsampling circuit 11 on the transmission side, and upsamples the input SDTV signal to thereby generate an HD having twice the number of pixels in the horizontal and vertical directions of the SDTV signal.
The low frequency component of the TV signal is reproduced. The output of the up-sampling circuit 20 includes horizontal pixel number K (= 1716> U), horizontal effective pixel number p (= 1440> u), and vertical line number L (=
1050> V), the number of vertical effective lines q (= 960>)
v), the low frequency component of the HDTV signal having the frame frequency f0 = 30 Hz. The output of the upsampling circuit 20 is given to the adder 21.

The buffer 22 also includes a clock recovery circuit 24.
High frequency HDTV including low frequency with clock φ4 output from
The coded output of the signal is taken in and the decoder 23
Output to. The decoder 23 operates with the clock φ1 output from the clock reproduction circuit 24 and decodes the input signal to reproduce the high frequency HDTV signal including the low frequency and give it to the adder 21.

The adder 21 adds the low frequency HDTV signal from the upsampling circuit 20 and the high frequency HDTV signal including the low frequency from the decoder 23. Upsampling circuit 20
The low-frequency HDTV signal from is a horizontal pixel number K = 1716, a horizontal effective pixel number p = 1440, and a vertical line number L = 105.
0, vertical effective line number q = 960, frame frequency f0
= 30 Hz low-frequency component signal, and for example, 75 lines above and below the HDTV signal are missing. Meanwhile, the decoder
High frequency HDTV signal including low frequency from 23 is horizontal pixel number K
= 1716, the number of horizontal effective pixels p = 1440, the number of vertical lines L = 1050, the number of vertical effective lines n = 1035, and the frame frequency f0 = 30 Hz.
Of n (1440 × 1035), p × q (1440 × 9
The portion 60) is the high frequency component of the HDTV signal, and the remaining portion of p × (n−q) (1440 × 75) is H of the entire band.
It is a DTV signal. Therefore, the addition result of the adder 21 becomes the HDTV signal of the entire band with the number of effective pixels p × n.

The HDTV signal from the hierarchical decoding unit 2 is given to the post processing unit 81. The post processing unit 81 has a memory 8
2, 83, memory control circuit 84 and horizontal low-pass filter 85
It is composed by. The post processing unit 81 performs the upsampling process on the HDTV signal to perform the original HDT.
It is designed to reproduce the V signal.

The HDTV signal is given to the memory 82 and the memory 83. Writing and reading of the memories 82 and 83 are controlled by the memory control circuit 84. The memory control circuit 84 operates by the clock φ0 output from the clock reproduction circuit 24 to set one of the memories 82 and 83 in the read mode and the other in the write mode. The memories 82 and 83 write the input signal in the write mode using the clock φ 1 and write the signal stored in the read mode in the clock φ 1.
It is designed to read by using 0.

FIG. 3 is a timing chart for explaining writing and reading of the memories 82 and 83 in FIG. FIG. 3A shows an HDTV signal, and FIG. 3B shows a memory 82.
3 (c) shows the read control of the memory 82, and FIG. 3 (d) shows the write control of the memory 83.
FIG. 3E shows the read control of the memory 83, and FIG.
Indicates the original HDTV signal. The period T1 in FIG. 3 is 1
It corresponds to a frame or one field period, and the period T2 is 1
It corresponds to the line period. The period T3 corresponds to a video signal period and the period T4 corresponds to a blanking period.

The memories 82 and 83 are shown in FIGS. 3B and 3D, respectively.
When the write control signal shown in FIG. 3 is "H", write enable is enabled, and the read control signal shown in FIGS. 3 (c) and 3 (e) is "H".
Read enable is enabled.

The HDTV signal shown in FIG. 3A is converted by the memory control circuit 84 into, for example, the memory 82 during the period T1 of FIG.
Written in. The clock φ 1 corresponds to the number of pixels of the HDTV signal, and as shown in FIG.
All the pixel data for one frame or one field of the HDTV signal is stored by using the clock φ1. Similarly, during the read period of the memory 82, as shown in FIG. 3D, the memory 83 stores all pixel data for one frame or one field of the HDTV signal.

The data stored in the memories 82 and 83 are as shown in FIG.
Reading is performed during the "H" period of the read control signal shown in (c) and (e). During the "H" period T6 of the read control signal, the original HD
TV signal (horizontal pixel number M = 2200, horizontal effective pixel number m
= 1920, the number of vertical lines N = 1125, and the number of vertical effective lines n = 1035).

From the memories 82 and 83, clocks φ0 and φ1
The effective pixel p of the HDTV signal based on the frequency ratio of
Reading is performed while 0 data is inserted in the pixel data of (1440) × n (1035). As a result, the data in the memories 82 and 83 are converted into m (1920) × n (1035) pixel data. The signals read from the memories 82 and 83 are applied to the horizontal low pass filter 85. The horizontal low pass filter 85 passes only the low frequency band. In this way, the horizontal interpolation is performed by reading the memories 82 and 83 and limiting the horizontal band.

The post processing unit 81 includes a horizontal low-pass filter 85.
Is output as the original HDTV signal. In addition, period T
Reference numeral 5 corresponds to one line period of the original HDTV signal, period T6 corresponds to a video signal period, and period T7 corresponds to a blanking period. Thus, the post processing unit 81 causes the number of horizontal pixels M = 220.
0, horizontal effective pixel number m = 1920, vertical line number N = 1
The original HDTV signal having 125, the number of vertical effective lines n = 1035, and the frame frequency f0 = 30 Hz is reproduced. This original HDTV signal is given to the HDTV monitor 26. H
The DTV monitor 26 has m × n effective pixels on the display screen.
(The original HDTV image of 1920 × 1035 is displayed.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory view of FIG. Figure 4 (a)
4B shows the original HDTV signal, FIG. 4B shows the HDTV signal from the pre-processing unit 71, FIG. 4C shows the HDTV signal having twice the horizontal and vertical resolution of the SDTV signal, and FIG. (D) is a high frequency HDT including the low frequency from the subtracter 12.
FIG. 4E shows the V signal, and the down sampling circuit 5 shown in FIG.
Alternatively, the SDTV signal from the decoder 19 is shown in FIG.
Indicates a low frequency HDTV signal from the upsampling circuits 11 and 20. In addition, the mesh lines in FIG. 4 indicate the components of the entire band, the diagonally right diagonal lines indicate the low frequency components, and the diagonal left diagonal lines indicate the high frequency components.

The number of horizontal pixels M = 220 shown in FIG.
0, horizontal effective pixel number m = 1920, vertical line number N = 1
The original HDTV signal having 125, the number of vertical effective lines n = 1035, and the frame frequency f0 = 30 Hz is given to the pre-processing unit 71 via the input terminal 4. The horizontal low-pass filter 72 of the pre-processing unit 71 limits the horizontal band of the original HDTV signal and outputs it to the memories 73 and 74. The memory control circuit 75 writes the original HDTV signal in the memories 73 and 74 using the clock φ0.

The memory control circuit 75 reads the data stored in the memories 73 and 74 by using the clock φ1. Clock φ
Horizontal decimation is performed based on the frequency ratio of 0 and φ1. That is, the memory control circuit 75 controls the original HDTV signal m × n (1920 × 1035) written in the memories 73 and 74.
Only the pixel data of the p × n (1440 × 1035) portion of the effective pixels of 1) are read out. As a result, FIG.
HDTV signal (horizontal pixel number K = 1716, horizontal effective pixel number p = 1440, vertical line number L = 1050, vertical effective line number n = 1035, frame frequency f0 = 3
0 Hz) is obtained. Resolution conversion is performed only in the horizontal direction,
Since the thinning is not performed in the vertical direction, the pre-processing unit 71
The HDTV signal from is a vertically long image as shown in FIG.

The downsampling circuit 5 of the hierarchical encoder 1 downsamples this HDTV signal. The downsampling circuit 5 has a capability of processing a signal having twice the resolution of the SDTV signal horizontally and vertically. That is, the memories 33 and 34 of the downsampling circuit 5
(See FIG. 15) is the HDTV signal (horizontal pixel number P = 1716, horizontal effective pixel number p = 1440, shown in FIG. 4C).
Number of vertical lines Q = 1050, number of vertical effective lines q = 96
0, frame frequency f0 = 30 Hz) low frequency component is stored.

K × L = P × Q, and the memories 33 and 34 are
The HDTV signal of the p × q portion except the portion corresponding to 1440 × 75 of the input HDTV signal is stored. The down-sampling circuit 5 reads out the HDTV signal stored in the memory at the clock φ 2 to reduce the horizontal and vertical resolutions by half to the SDTV signal (horizontal pixel number U = 858, The number of horizontal effective pixels u = 720, the number of vertical lines V = 525, the number of vertical effective lines v = 480, and the frame frequency f0 = 30 Hz), and the result is output to the encoder 7. The encoder 7 is a buffer 8
Controlled by the control signal output from SDTV
The signal is encoded and the encoded output is MP-processed via the buffer 8.
Output to X9.

On the other hand, the decoder 10 decodes the encoded output from the encoder 7 to reproduce the SDTV signal and outputs it to the upsampling circuit 11. Upsampling circuit 11
Is an upsampling process, that is, an interpolation process,
The SDTV signal is converted into a signal of horizontal pixel number K = 1716, horizontal effective pixel number p = 1440, vertical line number L = 1050, vertical effective line number q = 960, and frame frequency f0 = 30 Hz. This signal corresponds to the low frequency component of the HDTV signal, as shown in FIG.

Low-pass HD from upsampling circuit 11
The TV signal (effective pixel p × q) is given to the subtractor 12.
The subtractor 12 is also supplied from the pre-processing unit 71 with an HDTV signal in the entire band of p × n effective pixels shown in FIG. 4B.
The subtractor 12 subtracts the low-frequency HDTV signal from the HDTV signal of the entire band. With respect to the effective pixel p × q portion, the high-frequency HDTV signal (the left diagonally shaded area in FIG. 4D) is obtained by subtracting the HDTV signal of the entire band and the low-frequency HDTV signal. However, since the low-frequency HDTV signal does not have a px (nq) part, this part has a full-band HD
A TV signal (the shaded area in FIG. 4D) is obtained. Thus, the subtractor 12 outputs a high frequency HDTV signal including a low frequency band.

After the high frequency HDTV signal including the low frequency band is encoded by the encoder 13, the MPX is passed through the buffer 14.
Output to 9. The MPX 9 multiplexes the coded output of the SDTV signal and the coded output of the high frequency HDTV signal including the low frequency band, and sends the multiplexed signal to the transmission line 3.

The signal from the transmission system 3 is input to the hierarchical decoding unit 2. The DEMPX 17 of the hierarchical decoding unit 2 separates the coded output of the SDTV signal and the coded output of the high band HDTV signal including the low band. The encoded output of the SDTV signal is supplied to the decoder 19 via the buffer 18 and is decoded.
As a result, the SDTV signal shown in FIG. 4 (e) is reproduced.

Since this SDTV signal is a vertically long image, it is given to the vertical n → q conversion circuit 86 to restore the original normal image, and then given to the SDTV monitor 27. Thus, S
The number of effective pixels is u × v on the display screen of the DTV monitor 27.
A (720 × 480) SDTV image is displayed. This image corresponds to, for example, an HDTV image lacking 75 lines at the top and bottom, but the adverse visual effect is relatively small.

The SDTV signal from the decoder 19 is also given to the upsampling circuit 20. The upsampling circuit 20 performs the upsampling process, so that the upsampling circuit 20 of FIG.
Low-frequency HDTV signal (horizontal pixel number K = 1716, horizontal effective pixel number p = 1440, vertical line number L = 105
0, vertical effective line number q = 960, frame frequency f0
A low frequency component of the signal of 30 Hz). Low frequency HDT
The V signal is given to the adder 21.

On the other hand, the high frequency HDTV signal including the low frequency from the DEMPX 17 is given to the decoder 23 via the buffer 22. The decoder 23 uses the decoding process to generate a high band H including a low band.
The DTV signal (FIG. 4 (d)) is reproduced. The adder 21 adds the low-frequency HDTV signal and the high-frequency HDTV signal including the low-frequency signal to obtain the horizontal pixel number K = 171 shown in FIG. 4B.
6, horizontal effective pixel number p = 1440, vertical line number L = 1
050, vertical effective line number n = 1035, frame frequency f0 = 30 Hz, and the full band HDTV signal is reproduced,
Output to the post processing unit 81.

The post processing unit 81 controls writing and reading to and from the memories 82 and 83, thereby inputting H
The horizontal resolution of the DTV signal is converted. That is, writing to the memories 82 and 83 is performed using the clock φ1 and reading is performed using the clock φ0. At the time of reading, 0 data is inserted into the p × n (1440 × 1035) pixel data of the HDVT signal to form m × n (1920 × 1035) pixels. The horizontal low-pass filter 85 band-limits the data read from the memories 82 and 83. As a result, the pixels in the horizontal direction are interpolated, and the original HDTV signal (horizontal pixel number M = 2200, horizontal effective pixel number m = 1920, vertical line number N = 1125, vertical effective line number n) shown in FIG. = 103
5, the frame frequency f0 = 30 Hz) is obtained. By converting the horizontal resolution, the image returns to a normal image. Further, unlike the reproduced SDTV signal, the reproduced original HDTV signal has no image loss. Ex HD
The TV signal is given to the HDTV monitor 26 and the number of effective pixels is m ×
Display n original HDTV images.

As described above, in the present embodiment, the pre-processing unit 71 converts only the horizontal resolution. Therefore, although downsampling occurs in the vertical direction due to downsampling in hierarchical encoding, the screen quality as an SDTV image does not significantly deteriorate. Further, this lacking portion is transmitted as a high-range HDTV signal as a coded output of a layer with low priority, and the original HDTV image can be reproduced by adding the low-range HDTV signal on the receiving side. Pre-processing unit 71
The vertical low-pass filter can be omitted since the resolution conversion in the vertical direction is not performed in the above, and similarly, the vertical low-pass filter can be omitted in the post processing unit, and the circuit scale can be significantly reduced. You can

FIG. 5 is a block diagram showing another embodiment of the present invention. 5, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the horizontal low-pass filter can be omitted by performing only vertical resolution conversion in the pre-processing unit and the post-processing unit.

In this embodiment, a pre-processing unit 91 is used instead of the pre-processing unit 71, and a post-processing unit 101 is used instead of the post-processing unit 81.
1 in that a horizontal m → p conversion circuit 106 is used in place of the vertical n → q conversion circuit 86, and a clock generation circuit 90 is used in place of the clock generation circuit 15.

An original HDTV signal having the number of horizontal pixels M, the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, and the frame frequency f0 is input to the input terminal 4. This original HDTV signal is given to the pre-processing unit 91.
The pre-processing unit 91 includes a vertical low-pass filter 92 and memories 93 and 94.
And a memory control circuit 95. The clock generating circuit 90 is adapted to generate the clocks φ0 to φ4 based on the synchronizing signal input through the input terminal 16. The clocks φ0 to φ4 are based on the number of pixels of the original HDTV signal input through the input terminal 4, and the clocks φ0 to φ4 in the embodiment of FIG.
Different from 4.

The vertical low-pass filter 92 operates by the clock φ 0 from the clock generation circuit 90, limits the band of the original HDTV signal, and outputs it to the memories 93 and 94. Writing and reading of the memories 93 and 94 are controlled by the memory control circuit 95. The memory control circuit 95 operates by the clock φ0 output from the clock generation circuit 90, and when one of the memories 93 and 94 is in the read mode, the other is in the write mode. Memory 93, 94
Clocks the input signal in write mode φ0
Is used to read and write the signal stored in the read mode using the clock φ1.

FIG. 6 is a timing chart for explaining writing and reading in the memories 93 and 94 in FIG. FIG. 6A shows the original HDTV signal, and FIG. 6B shows the memory.
FIG. 6C shows write control of the memory 93, FIG. 6C shows read control of the memory 93, FIG. 6D shows write control of the memory 94, and FIG. 6E shows read control of the memory 94. 6
(F) shows an HDTV signal. Period T1 in FIG.
Corresponds to one frame or one field period, and the period T2
Corresponds to one line period. The period T3 corresponds to a video signal period and the period T4 corresponds to a blanking period.

The memories 93 and 94 are shown in FIGS. 6B and 6D, respectively.
When the write control signal shown in FIG. 6 is "H", write enable is enabled, and the read control signal shown in FIGS. 6C and 6E is "H".
Read enable is enabled.

The original HDTV signal shown in FIG. 6A is converted by the memory control circuit 95 into, for example, the memory during the period T1 of FIG.
Written in 93. The clock φ 0 corresponds to the number of pixels of the original HDTV signal, and as shown in FIG.
Stores all pixel data for one frame or one field of the original HDTV signal by using the clock φ0.
Similarly, during the read period of the memory 93, the memory 94 stores all pixel data for one frame or one field of the original HDTV signal, as shown in FIG. 6D.

The data stored in the memories 93 and 94 are as shown in FIG.
Reading is performed during the "H" period of the read control signal shown in (c) and (e). During the "H" period T6 of the read control signal, the SDT
HD composed of twice the number of pixels horizontally and vertically as the V signal
TV signal (corresponding to a video signal for one line in the number of horizontal pixels P, the number of horizontal effective pixels p, the number of vertical lines Q, and the number of vertical effective lines q).

Clocks φ0 and φ1 are output from the memories 93 and 94.
Based on the frequency ratio of, the m × q pixel data of the m × n effective pixels of the original HDTV signal is read. That is, the thinning out is performed in the vertical direction by reading the memories 93 and 94. Note that no thinning is performed in the horizontal direction.

The output of the pre-processing unit 91 is HD after resolution conversion.
It is output to the hierarchical encoding unit 1 as a TV signal. Note that the period T5 corresponds to one line period of an HDTV signal, the period T6 corresponds to a video signal period, and the period T7 corresponds to a blanking period. In this way, the pre-processing unit 71 obtains an HDTV signal having a horizontal pixel number K, a horizontal effective pixel number m, a vertical line number L, a vertical effective line number q, and a frame frequency f0.

On the other hand, as described above, the pre-processing unit 6 of the conventional example has the HDTV signal (horizontal pixel number P, horizontal effective number) in which the number of pixels in the horizontal and vertical directions of the original HDTV signal is twice that of the SDTV signal. The number of pixels is p, the number of vertical lines is Q, and the number of vertical effective lines is q).

That is, in the pre-processing unit 71 of this embodiment, the resolution conversion processing in the vertical direction is the same as in the conventional example,
The number of vertical pixels of the converted HDTV signal is L = Q, and the number of vertical effective pixels is q. On the other hand, in the horizontal direction, the original H
The DTV signal is read as it is, and the converted HDTV
The number of horizontal lines of the signal is K = P, but the number of horizontal effective lines is m instead of p. That is, the following expression (2) is established. Since the thinning is performed only in the vertical direction, the converted image becomes a vertically long image.

K × L = P × Q, m × q <P × Q <m × n (2) The HDTV signal from the hierarchical decoding unit 2 is the post-processing unit 101.
Given to. The post processing unit 101 includes the memories 102 and 103.
, Memory control circuit 104 and vertical low-pass filter 105
It is composed by. Post processing unit 101 is HDTV
Original HD by the upsampling process for the signal
It is designed to reproduce TV signals.

That is, the HDTV signal is given to the memories 102 and 103. Writing and reading of the memories 102 and 103 are controlled by the memory control circuit 104. The memory control circuit 104 operates by the clock φ 0 output from the clock reproduction circuit 24, and sets one of the memories 102 and 103 in the read mode and the other in the write mode. The memories 102 and 103 are adapted to write the input signal in the write mode by using the clock φ1 and read the stored signal in the read mode by using the clock φ0.

FIG. 7 is a timing chart for explaining writing and reading of the memories 102 and 103 in FIG. 7A shows an HDTV signal, FIG. 7B shows write control of the memory 102, and FIG. 7C shows memory 102.
7 (d) shows the write control of the memory 103, FIG. 7 (e) shows the read control of the memory 103, and FIG. 7 (f) shows the original HDTV signal. The period T1 in FIG. 7 corresponds to one frame or one field period, and the period T2 corresponds to one line period. Also, the period T
3 corresponds to the video signal period, and the period T4 corresponds to the blanking period.

The memories 102 and 103 are shown in FIG.
The write control signal "H" shown in (d) enables write enable, and the read control signal "H" shown in FIGS. 7 (c) and (e) enables read enable.

The HDTV signal shown in FIG. 7A is converted by the memory control circuit 104 into, for example, a memory during the period T1 of FIG.
Written at 102. The clock φ 1 corresponds to the number of pixels of the HDTV signal, and as shown in FIG.
2 stores all pixel data for one frame or one field of the HDTV signal by using the clock φ1.
Similarly, during the read-out period of the memory 102, as shown in FIG. 7D, the memory 103 displays one frame or one frame of the HDTV signal.
All pixel data for fields are stored.

The data stored in the memories 102 and 103 are
Reading is performed during the "H" period of the read control signal shown in FIGS. 7 (c) and 7 (e). The "H" period T6 of the read control signal corresponds to a video signal for one line in the original HDTV signal (the number of horizontal pixels M, the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n).

From the memories 102 and 103, clocks φ 0,
Based on the frequency ratio of φ1, reading is performed while inserting 0 data into the pixel data of the effective pixel m × q of the HDTV signal. As a result, the data in the memories 102 and 103 are converted into m × n pixel data. The signals read from the memories 102 and 103 are given to the vertical low pass filter 105. The vertical low pass filter 105 passes only the low frequency band. Thus, vertical interpolation is performed by reading the memories 102 and 103 and limiting the vertical band.

The post processing unit 101 is a vertical low pass filter.
The output of 105 is output as the original HDTV signal. Note that the period T5 corresponds to one line period of the original HDTV signal, the period T6 corresponds to a video signal period, and the period T7 corresponds to a blanking period.
Thus, the post processing unit 101 causes the number of horizontal pixels M,
The original HDTV signal having the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, and the frame frequency f0 is reproduced. This original HDTV signal is given to the HDTV monitor 26.

The horizontal m → p conversion circuit 106 operates with the clock φ2 output from the clock recovery circuit 24, and the decoder 1
For the SDTV signal from 9, the number of scanning lines is converted to convert m pixels into p pixels. By this, horizontal m →
The output signal of the p conversion circuit 106 is converted into an SDTV signal having the number of horizontal pixels U, the number of horizontal effective pixels u × p / m, the number of vertical lines V, the number of vertical effective lines v, and the frame frequency f0, and expanded in the horizontal direction. The image is restored to a normal image. It should be noted that this SDTV image is, for example, an image in which the left and right sides of the input HDTV image are slightly missing. When the SDTV monitor 27 can control the horizontal deflection, the horizontal m → p conversion circuit 106 is omitted, and the output of the decoder 19 is directly applied to the SDTV monitor 27 to display a normal image. You may show it.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory view of FIG. Figure 8 (a)
8B shows the original HDTV signal, FIG. 8B shows the HDTV signal from the pre-processing unit 91, FIG. 8C shows the HDTV signal having twice the horizontal and vertical resolution of the SDTV signal, and FIG. (D) is a high frequency HDT including the low frequency from the subtracter 12.
8E shows the V signal, and FIG.
Alternatively, the SDTV signal from the decoder 19 is shown in FIG.
Indicates a low frequency HDTV signal from the upsampling circuits 11 and 20. Further, the mesh lines in FIG. 8 indicate the components of the entire band, the diagonally right diagonal lines indicate the low frequency components, and the diagonal left diagonal lines indicate the high frequency components.

The original HDTV signal of which the number of horizontal pixels is M, the number of horizontal effective pixels is m, the number of vertical lines is N, the number of vertical effective lines is n, and the frame frequency is f0 shown in FIG. And is given to the pre-processing unit 91. The vertical low-pass filter 92 of the pre-processing unit 91 limits the vertical band of the original HDTV signal and outputs it to the memories 93 and 94. Memory control circuit 95
Uses the clock φ 0 to store the original HDTV in the memories 93 and 94.
Write a signal.

The memory control circuit 95 reads the data stored in the memories 93 and 94 by using the clock φ1. Clock φ
Vertical decimation is performed based on the frequency ratio of 0 and φ1. That is, the memory control circuit 95 uses m × n of m × n effective pixels of the original HDTV signal written in the memories 93 and 94.
Only the pixel data of the q portion is read. As a result, FIG.
The HDTV signal (the number of horizontal pixels K, the number of horizontal effective pixels m, the number of vertical lines L, the number of vertical effective lines q, and the frame frequency f0) shown in (b) is obtained. Since the resolution conversion is performed only in the vertical direction and is not decimated in the horizontal direction, the HDTV signal from the pre-processing unit 91 is as shown in FIG. 8B.
The image becomes landscape.

The downsampling circuit 5 of the hierarchical encoder 1 downsamples this HDTV signal. The downsampling circuit 5 has a capability of processing a signal having twice the resolution of the SDTV signal horizontally and vertically. That is, the memories 33 and 34 of the downsampling circuit 5
The low frequency components of the HDTV signal (horizontal pixel number P, horizontal effective pixel number p, vertical line number Q, vertical effective line number q, frame frequency f0) shown in FIG. .

K × L = P × Q, and the memories 33 and 34 are
The HDTV signal of the p × q portion except the portion corresponding to (m−p) × q of the input HDTV signal is stored. The down-sampling circuit 5 reads out the HDTV signal stored in the memory at the clock φ 2 to reduce the horizontal and vertical resolutions by half to the SDTV signal (horizontal pixel number U, horizontal effective number) shown in FIG. Pixel number u, vertical line number V, vertical effective line number v, frame frequency f
0) and output to the encoder 7. The encoder 7 is controlled by the control signal output from the buffer 8,
The SDTV signal is encoded and the encoded output is output to the MPX 9 via the buffer 8.

On the other hand, the decoder 10 decodes the encoded output from the encoder 7 to reproduce the SDTV signal and outputs it to the upsampling circuit 11. Upsampling circuit 11
Is an upsampling process, that is, an interpolation process,
The number of horizontal pixels is K, the number of horizontal effective pixels is p, the number of vertical lines is L, the number of vertical effective lines is q, and the frame frequency is f0.
Signal is converted to. This signal corresponds to the low frequency component of the HDTV signal, as shown in FIG.

Low-pass HD from upsampling circuit 11
The TV signal (effective pixel p × q) is given to the subtractor 12.
The subtractor 12 is also supplied from the pre-processing unit 91 with an HDTV signal in the entire band of m × q effective pixels shown in FIG. 8B.
The subtractor 12 subtracts the low-frequency HDTV signal from the HDTV signal of the entire band. With respect to the effective pixel p × q portion, a high-frequency HDTV signal (a diagonally shaded left portion in FIG. 8D) is obtained by subtracting the HDTV signal of the entire band and the low-frequency HDTV signal. However, since the low-frequency HDTV signal does not have a (mp) × q portion, this portion has a full-band HD
A TV signal (the shaded area in FIG. 8D) is obtained. Thus, the subtractor 12 outputs a high frequency HDTV signal including a low frequency band.

The high frequency HDTV signal including the low frequency is encoded by the encoder 13 and then MPX is passed through the buffer 14.
Output to 9. The MPX 9 multiplexes the coded output of the SDTV signal and the coded output of the high frequency HDTV signal including the low frequency band, and sends the multiplexed signal to the transmission line 3.

The signal from the transmission system 3 is input to the hierarchical decoding unit 2. The DEMPX 17 of the hierarchical decoding unit 2 separates the coded output of the SDTV signal and the coded output of the high band HDTV signal including the low band. The encoded output of the SDTV signal is given to the decoder 19 via the buffer 18 and decoded.
As a result, the SDTV signal shown in FIG. 8 (e) is reproduced.

Since this SDTV signal is a horizontally long image, it is given to the horizontal m → p conversion circuit 106 to restore the original normal image, and then given to the SDTV monitor 27. Thus
The number of effective pixels is ux on the display screen of the SDTV monitor 27.
SDTV image of v is displayed. This image is the original H
Although it corresponds to, for example, an image in which the left and right sides of the DTV image are slightly missing, the adverse visual effect is relatively small.

The SDTV signal from the decoder 19 is also given to the upsampling circuit 20. The upsampling circuit 20 performs the upsampling process, so that the upsampling circuit 20 shown in FIG.
The low-frequency HDTV signal (the number of horizontal pixels K, the number of horizontal effective pixels p, the number of vertical lines L, the number of vertical effective lines q, the low-frequency component of the signal of the frame frequency f0) shown in FIG. Low frequency HDT
The V signal is given to the adder 21.

On the other hand, the high frequency HDTV signal including the low frequency from the DEMPX 17 is given to the decoder 23 via the buffer 22. The decoder 23 uses the decoding process to generate a high band H including a low band.
The DTV signal (FIG. 8 (d)) is reproduced. The adder 21 adds the low-frequency HDTV signal and the high-frequency HDTV signal including the low frequency to obtain the number of horizontal pixels K, the number of horizontal effective pixels m, the number of vertical lines L, and the number of vertical effective lines shown in FIG. 8B. Play back a full band HDTV signal with a number q and a frame frequency f0,
Output to the post processing unit 101.

The post-processing section 101 controls the vertical resolution of the input HDTV signal by controlling writing and reading to and from the memories 102 and 103. That is, writing to the memories 102 and 103 is performed using the clock φ1 and reading is performed using the clock φ0. At the time of reading, 0 data is inserted into m × q pixel data of the HDVT signal to form m × n pixels. The vertical low pass filter 105 band-limits the data read from the memories 102 and 103. As a result, the pixels in the horizontal direction are interpolated, and the original HDTV signal (the number of horizontal pixels M, the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, the frame frequency f0) shown in FIG. 8A is obtained. can get. By converting the vertical resolution, the image returns to a normal image. Also, the reproduced original HDTV signal is different from the reproduced SDTV signal,
The image is not missing. The original HDTV signal is given to the HDTV monitor 26 to display the original HDTV image with the effective pixel number m × n.

As described above, in this embodiment, only the vertical resolution is converted in the pre-processing section 91. Therefore, the downsampling in the hierarchical coding causes a drop in the image in the horizontal direction, but the screen quality as an SDTV image does not significantly deteriorate. Further, this lacking portion is transmitted as a high-range HDTV signal as a coded output of a layer with low priority, and the original HDTV image can be reproduced by adding the low-range HDTV signal on the receiving side. Pre-processing unit 91
The horizontal low-pass filter can be omitted because the resolution conversion in the horizontal direction is not performed, and similarly, the horizontal low-pass filter can also be omitted in the post processing unit, which significantly reduces the circuit scale. You can

FIG. 9 is a block diagram showing another embodiment of the present invention. 9, the same components as those of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the horizontal low-pass filter can be omitted without performing resolution conversion in the horizontal and vertical directions in the pre-processing unit and the post-processing unit.

In this embodiment, a pre-processing unit 111 is used in place of the pre-processing unit 71 and a post-processing unit 1 is used in place of the post-processing unit 81.
21 and the clock generator circuit 110 is used instead of the clock generator circuit 15, which is a difference from the embodiment of FIG.

The original HDTV signal having the number of horizontal pixels M, the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, and the frame frequency f0 is input to the input terminal 4. This original HDTV signal is given to the pre-processing unit 111. The pre-processing unit 111 is composed of memories 112 and 113 and a memory control circuit 114. Clock generation circuit 90
Is based on the sync signal input via the input terminal 16,
Clocks φ0 to φ4 are generated. The clocks φ0 to φ4 are based on the number of pixels of the original HDTV signal input via the input terminal 4.
It differs from the clocks .phi.0 to .phi.4 in the embodiment of FIG.

Writing and reading of the memories 112 and 113 are controlled by the memory control circuit 114. Memory control circuit
114 is the clock φ output from the clock generation circuit 90.
It operates at 0, and when one of the memories 112 and 113 is set to the read mode, the other is set to the write mode. The memories 112 and 113 are adapted to write the input signal in the write mode by using the clock φ0 and read the stored signal in the read mode by using the clock φ1.

FIG. 10 is a timing chart for explaining the writing and reading of the memories 112 and 113 in FIG. FIG. 10A shows the original HDTV signal.
FIG. 10B shows the write control of the memory 112, and FIG.
Shows the read control of the memory 112, FIG. 10 (d) shows the write control of the memory 113, and FIG. 10 (e) shows the memory 113.
10 (f) shows the HDTV signal. The period T1 in FIG. 10 corresponds to one frame or one field period, and the period T2 corresponds to one line period. The period T3 corresponds to the video signal period, and the period T4
Corresponds to the blanking period.

The memories 112 and 113 are respectively shown in FIG.
The write control signal “H” shown in FIG. 10D enables write enable, and the read control signal “H” shown in FIGS. 10C and 10E enables read enable.

The original HDTV signal shown in FIG. 10A is written in the memory 112, for example, during the period T1 of FIG. 10 by the memory control circuit 114. The clock φ 0 corresponds to the number of pixels of the original HDTV signal, and as shown in FIG.
The memory 112 uses the clock φ0 to generate the original HDTV.
All pixel data for one frame or one field of the signal is stored. Similarly, during the reading period of the memory 112, as shown in FIG.
As shown in (d), the memory 113 stores 1 of the original HDTV signal.
All pixel data for a frame or one field is stored.

The data stored in the memories 112 and 113 are
Reading is performed during the "H" period of the read control signal shown in FIGS. During the "H" period T6 of the read control signal,
It corresponds to a video signal for one line in the HDTV signal (the number of horizontal pixels P, the number of horizontal effective pixels p, the number of vertical lines Q, the number of vertical effective lines q) that is composed of twice the number of pixels in the horizontal and vertical directions of the SDTV signal. .

From the memories 112 and 113, clocks φ 0,
Pixel data is read based on the frequency ratio of φ 1.
In this case, at least pixel data of m × n effective pixels of the original HDTV signal is read.

The output of the pre-processing unit 111 is H after resolution conversion.
It is output to the hierarchical encoding unit 1 as a DTV signal. In addition,
The period T5 corresponds to one line period of an HDTV signal, the period T6 corresponds to a video signal period, and the period T7 corresponds to a blanking period.
Thus, the pre-processing unit 71 causes the number of horizontal pixels K, the number of horizontal effective pixels m, the number of vertical lines L, the number of vertical effective lines n,
An HDTV signal having a frame frequency f0 can be obtained.

On the other hand, as described above, the pre-processing unit 6 of the conventional example has an HDTV signal (horizontal pixel number P, horizontal effective number) in which the number of pixels of the original HDTV signal in the horizontal and vertical directions is twice that of the SDTV signal. The number of pixels is p, the number of vertical lines is Q, and the number of vertical effective lines is q).

That is, in the pre-processing unit 111 of this embodiment, the original HDTV signal is read as it is without performing resolution conversion processing, and the number of horizontal and vertical effective lines of the converted HDTV signal is p and q. Not m and n. Even in this case, the number of horizontal pixels is K = P and the number of vertical lines is L =
Q. That is, the following expression (3) is established.

K × L = P × Q, m × n <P × Q (3) The HDTV signal from the hierarchical decoding unit 2 is post-processing unit 121.
Given to. The post processing unit 121 includes the memories 122 and 123.
And a memory control circuit 124. The post processing unit 121 reproduces the original HDTV signal by performing upsampling processing on the HDTV signal.

The HDTV signal is stored in the memory 122 and the memory 123.
Given to. The memories 122 and 123 are memory control circuits 124
Writing and reading are controlled by. The memory control circuit 124 operates by the clock φ0 output from the clock reproduction circuit 24, and sets one of the memories 122 and 123 in the read mode and the other in the write mode. The memories 122 and 123 are adapted to write the input signal in the write mode using the clock φ1 and read the signal stored in the read mode in the clock φ0.

FIG. 11 is a timing chart for explaining writing and reading of the memories 122 and 123 in FIG. FIG. 11 (a) shows an HDTV signal, and FIG. 11 (b).
Shows the write control of the memory 122, FIG. 11 (c) shows the read control of the memory 122, and FIG. 11 (d) shows the memory 123.
11 (e) shows the read control of the memory 123, and FIG. 11 (f) shows the original HDTV signal. The period T1 in FIG. 11 corresponds to one frame or one field period, and the period T2 corresponds to one line period.
The period T3 corresponds to a video signal period and the period T4 corresponds to a blanking period.

The memories 122 and 123 are respectively shown in FIG.
The write control signal "H" shown in FIG. 11D enables write enable, and the read control signal "H" shown in FIGS. 11C and 11E enables read enable.

The HDTV signal shown in FIG. 11A is written in the memory 122, for example, during the period T1 of FIG. 11 by the memory control circuit 124. The clock φ1 corresponds to the number of pixels of the HDTV signal, and the memory 122 stores all pixel data for one frame or one field of the HDTV signal by using the clock φ1, as shown in FIG. 11 (b). . Similarly, during the reading period of the memory 122, as shown in FIG.
As shown in (d), the memory 123 stores all pixel data for one frame or one field of the HDTV signal.

The data stored in the memories 122 and 123 are
Reading is performed during the "H" period of the read control signal shown in FIGS. During the "H" period T6 of the read control signal,
This corresponds to a video signal for one line in the original HDTV signal (horizontal pixel number M, horizontal effective pixel number m, vertical line number N, vertical effective line number n). From the memories 122 and 123, reading is performed based on the frequency ratio of the clocks φ0 and φ1 to obtain m × n pixel data.

The post processing unit 121 is a vertical low-pass filter.
The output of 105 is output as the original HDTV signal. Note that the period T5 corresponds to one line period of the original HDTV signal, the period T6 corresponds to a video signal period, and the period T7 corresponds to a blanking period.
Thus, the post processing unit 121 allows the number of horizontal pixels M,
The original HDTV signal having the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, and the frame frequency f0 is reproduced. This original HDTV signal is given to the HDTV monitor 26.

Next, the operation of the embodiment thus constructed will be described with reference to the explanatory view of FIG. 12
12A shows the original HDTV signal, FIG. 12B shows the HDTV signal from the pre-processing unit 111, and FIG.
HD with double the horizontal and vertical resolution of the DTV signal
12 (d) shows a TV signal, FIG. 12 (d) shows a high band HDTV signal including a low band from the subtracter 12, and FIG. 12 (e) shows an SDTV signal from the down-sampling circuit 5 or the decoder 19. 12 (f) shows the low-frequency HDTV signal from the upsampling circuits 11 and 20. In addition, the mesh lines in FIG. 12 indicate the components of the entire band, the diagonally right diagonal lines indicate the low frequency components, and the diagonal left diagonal lines indicate the high frequency components.

The original HDTV signal having the number of horizontal pixels M, the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, and the frame frequency f0 shown in FIG. Is supplied to. Memory control circuit 114
Uses the clock φ 0 to store the original HD in the memories 112 and 113.
Write TV signal.

The memory control circuit 114 reads the data stored in the memories 112 and 113 using the clock φ1. As a result, the HDTV signal (horizontal pixel number K, horizontal effective pixel number m, vertical line number L, vertical effective line number n, frame frequency f0) shown in FIG. 12B is obtained.

The downsampling circuit 5 of the hierarchical encoder 1 downsamples the HDTV signal. The downsampling circuit 5 has a capability of processing a signal having twice the resolution of the SDTV signal horizontally and vertically. That is, the memories 33 and 34 of the downsampling circuit 5
The HDTV signal (the number of horizontal pixels P, the number of horizontal effective pixels p, the number of vertical lines Q) shown in FIG.
The low-frequency component of the vertical effective line number q and the frame frequency f0) is stored.

K × L = P × Q, and the memories 33 and 34 are
(M−p) × q, p × (n− of the input HDTV signal
The HDTV signal of the p × q portion excluding the portion corresponding to (q) will be stored. The down sampling circuit 5 is
By reading out this HDTV signal stored in the memory at clock φ 2, the SDTV signal (horizontal pixel number U, horizontal effective pixel number u, vertical line U) shown in FIG. Number V, vertical effective line number v,
It is converted to a frame frequency f0) and output to the encoder 7. The encoder 7 is controlled by the control signal output from the buffer 8, encodes the SDTV signal, and outputs the encoded output to the MPX 9 via the buffer 8.

On the other hand, the decoder 10 decodes the encoded output from the encoder 7 to reproduce the SDTV signal and outputs it to the upsampling circuit 11. Upsampling circuit 11
Is an upsampling process, that is, an interpolation process,
The number of horizontal pixels is K, the number of horizontal effective pixels is p, the number of vertical lines is L, the number of vertical effective lines is q, and the frame frequency is f0.
Signal is converted to. This signal corresponds to the low frequency component of the HDTV signal, as shown in FIG.

Low-pass HD from upsampling circuit 11
The TV signal (effective pixel p × q) is given to the subtractor 12.
The pre-processing unit 111 also supplies the subtractor 12 with an HDTV signal in the entire band of m × n effective pixels shown in FIG. The subtractor 12 converts the HDTV signal of the entire band to the low band HDTV
Subtract the signal. With respect to the effective pixel p × q portion, the high-frequency HDTV signal is subtracted from the low-frequency HDTV signal in the entire band (the diagonally diagonally left portion in FIG. 12D).
Is obtained. However, the low-frequency HDTV signal is (mp) ×
Since it does not have a q, p × (n−q) portion, an HDTV signal in the entire band (the halftone dot portion in FIG. 12D) can be obtained for this portion. Thus, the subtractor 12 outputs a high frequency HDTV signal including a low frequency band.

After the high frequency HDTV signal including the low frequency band is encoded by the encoder 13, the MPX is passed through the buffer 14.
Output to 9. The MPX 9 multiplexes the coded output of the SDTV signal and the coded output of the high frequency HDTV signal including the low frequency band, and sends the multiplexed signal to the transmission line 3.

The signal from the transmission system 3 is input to the hierarchical decoding unit 2. The DEMPX 17 of the hierarchical decoding unit 2 separates the coded output of the SDTV signal and the coded output of the high band HDTV signal including the low band. The encoded output of the SDTV signal is given to the decoder 19 via the buffer 18 and decoded.
As a result, the SDTV signal shown in FIG. 12 (e) is reproduced.

This SDTV signal is given to the SDTV monitor 27. Thus, an SDTV image with an effective pixel number of u × v is displayed on the display screen of the SDTV monitor 27. It should be noted that this image corresponds to an input HDTV image, for example, which is slightly lacking in the upper and lower sides and the left and right sides, but has a relatively small visual adverse effect.

The SDTV signal from the decoder 19 is also given to the upsampling circuit 20. The upsampling circuit 20 performs the upsampling process to
The low-frequency HDTV signal shown in (f) (the number of horizontal pixels K, the number of horizontal effective pixels p, the number of vertical lines L, the number of vertical effective lines q, the low-frequency component of the signal of the frame frequency f0) is reproduced. The low-frequency HDTV signal is given to the adder 21.

On the other hand, the high frequency HDTV signal including the low frequency from the DEMPX 17 is given to the decoder 23 via the buffer 22. The decoder 23 uses the decoding process to generate a high band H including a low band.
The DTV signal (FIG. 12 (d)) is reproduced. The adder 21 adds the low-frequency HDTV signal and the high-frequency HDTV signal including the low frequency to obtain the number of horizontal pixels K, the number of horizontal effective pixels m, the number of vertical lines L, and the number of vertical effective lines shown in FIG. An HDTV signal of all bands having a number n and a frame frequency f0 is reproduced and output to the post processing unit 121.

Writing to the memories 122 and 123 of the post processing unit 121 is performed using the clock φ 1, and reading is performed using the clock φ 1.
Use 0. At the time of reading, m × n effective pixels of the HDVT signal are read. As a result, the original HDTV signal (the number of horizontal pixels M, the number of horizontal effective pixels m, the number of vertical lines N, the number of vertical effective lines n, the frame frequency f0 shown in FIG.
) Is obtained. Unlike the reproduced SDTV signal, the reproduced original HDTV signal has no image loss. Ex H
The DTV signal is supplied to the HDTV monitor 26 to display the original HDTV image with the effective pixel number m × n.

As described above, in this embodiment, the pre-processing section 111 does not perform resolution conversion in the horizontal and vertical directions. Therefore, the downsampling in the hierarchical coding causes a drop in the image in the horizontal and vertical directions, but the screen quality as an SDTV image is not significantly deteriorated. In addition, this lacking part is a high frequency HDT
It is transmitted as a higher-level encoded output together with the V signal, and the original HDTV image can be reproduced by adding it to the low-frequency HDTV signal on the receiving side. Pre-processing unit 11
Since horizontal and vertical resolution conversion is not performed in 1, the horizontal and vertical low-pass filters can be omitted, and similarly, the horizontal and vertical low-pass filters can also be omitted in the post processing unit. The circuit scale can be significantly reduced.

[0158]

As described above, according to the present invention, the circuit scale can be remarkably reduced by simplifying the horizontal and vertical resolution conversion.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a hierarchical encoding / decoding device according to the present invention.

FIG. 2 is a timing chart for explaining writing and reading of memories 73 and 74 in FIG.

FIG. 3 is a timing chart for explaining writing and reading of memories 82 and 83 in FIG.

FIG. 4 is an explanatory diagram for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

6 is a timing chart for explaining writing and reading of memories 93 and 94 in FIG.

7 is a timing chart for explaining writing and reading of memories 102 and 103 in FIG.

FIG. 8 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 9 is a block diagram showing another embodiment of the present invention.

10 is a timing chart for explaining writing and reading of the memories 112 and 113 in FIG.

FIG. 11 is a timing chart for explaining writing and reading in the memories 122 and 123 in FIG.

12 is an explanatory diagram for explaining the operation of the embodiment of FIG.

FIG. 13 is a block diagram showing a conventional hierarchical encoding / decoding device.

FIG. 14 is an explanatory diagram for explaining the operation of the conventional example.

FIG. 15 is a block diagram showing a specific configuration of a downsampling circuit.

FIG. 16 is a block diagram showing a specific configuration of an upsampling circuit.

17 is a pre-processing unit 6 and a post-processing unit 25 shown in FIG.
3 is a block diagram showing a specific configuration of FIG.

FIG. 18 is a timing chart for explaining writing and reading of the memories 53 and 54 in FIG.

FIG. 19 is a timing chart for explaining writing and reading of memories 61 and 62 in FIG.

[Explanation of symbols]

1 ... Hierarchical coding unit, 2 ... Hierarchical decoding unit, 71 ... Pre-processing unit, 73, 74, 82, 83 ... Memory, 75, 84 ... Memory control circuit

Claims (1)

[Claims] 1. The number of horizontal pixels is K, the number of horizontal effective pixels is m,
The number of vertical lines is L, and the number of vertical effective lines is n (K, m,
A television signal of L and n is a natural number, and p of horizontal effective pixels (p is a natural number of m or less) pixels and q of vertical effective lines (q is a natural number of n or less) lines. Down-sampling means for down-sampling the part of xq; first encoding means for encoding and transmitting the output of the down-sampling means; up-sampling means for up-sampling the output of the down-sampling means; A subtraction means for obtaining a high frequency component for the p × q portion of the television signal and a full band component for the other portion by obtaining the difference between the television signal and the output of the up-sampling means; A second coding means for coding and transmitting the output of the means, and a hierarchical coding / decoding device.