JPH072027B2 - Vibration wave motor speed control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a vibration wave motor, and more particularly to a speed control circuit for a vibration wave motor that drives a moving body with a progressive vibration wave.

<Prior Art> In a vibration wave motor (hereinafter referred to as SSM), the electricity of the electrostrictive element arranged on the vibrating body (stator) with a phase
Frequency voltages with different phase differences (90 °) are applied to the mechanical energy conversion elements to generate progressive vibration waves on the vibrating body, and the moving body is brought into frictional contact with the vibrating body. Is moved in.

A drive unit for applying the above-mentioned frequency voltage in the motor is configured as shown in FIG. 9 and has an amplifier 7, a coil 10 and an electrode 1.
The frequency voltage is applied to the electrostrictive element of the first group via -1, and there is a phase difference with respect to the electrostrictive element of the first group via the amplifier 8, the coil 11 and the electrode 1-2. A frequency voltage having a phase difference of 90 ° from the frequency voltage is applied to the second group of electrostrictive elements arranged. As a method of making the motor speed variable in the SSM according to the configuration, there is a method of adjusting the output voltage levels of the amplifiers 7 and 8. That is, there is a method in which the amplification factor of the amplifiers 7 and 8 can be changed or the power supply voltage itself can be changed, but for that purpose, it is necessary to provide a special additional circuit, and there is a drawback that the configuration becomes complicated.

As another method, it is possible to adjust the duty ratio of the frequency voltage applied to the electrostrictive element, but this method may cause the moving body to move intermittently.

There is also a method of shifting the frequency of the frequency voltage from the resonance frequency of the SSM. According to this method, the series resonance circuits of the coil 10 and the stator 1 and the coil 11 and the stator 1 shown in FIG. 9 resonate. The voltage applied to the offset electrodes 1-1 and 1-2 becomes larger than that of the point, and the stator 1 may be damaged.

<Purpose> The present invention has been made in view of the above matters, and as its configuration, applies frequency signals having different phases to the electromechanical energy conversion elements of the first and second groups arranged on the vibrating body. In the speed control circuit of the vibration wave motor that excites the vibration body to form a vibration wave in the vibration body to obtain the driving force, the oscillator that oscillates at a predetermined frequency and the frequency division that divides the output pulse from the oscillator A circuit, a shift register circuit having a plurality of stages for connecting an output terminal of the frequency dividing circuit to an input terminal and a clock terminal for connecting to the oscillator, and a selection unit for selecting an output stage of the shift register circuit, The shift register selected by the selecting means is applied to the electro-mechanical energy conversion element of the second group while applying the frequency-dividing circuit output to the electro-mechanical energy conversion element of the first group. Applying an output from the output stage of the shifter circuit, and adjusting the phase of the frequency signal applied to the electromechanical energy conversion elements of the first and second groups by selecting the output stage of the shift register circuit. Provides a speed control circuit for a vibration wave motor in which speed adjustment of the motor is stably and highly accurately performed.

<Embodiment> FIG. 1 is a configuration diagram showing an electrode shape of a stator of an SSM according to the present invention. In the figure, 1 indicates a stator, and two groups of polarized electrostrictive elements are arranged on the surface of the stator, and frequency voltages having 90 ° different phases are applied to the electrostrictive elements of each group. Drive electrodes 1-1 and 1-2 are arranged. Again 1-3
Is a monitor electrode which is disposed on the electrostrictive element which is electrically insulated from the drive electrodes 1-1 and 1-2 and which has been subjected to polarization processing, and which detects the vibration state of the stator by the output of the electrostrictive element. And 1-4 is a common electrode for each of the electrodes 1-1, 1-2 and 1-3.

FIG. 2 is a circuit diagram showing an SSM drive circuit according to the present invention.

In the figure, 1 is a stator on which an electrostrictive element is arranged,
1-1, 1-2, 1-3 are electrodes shown in the first figure, 10 and 11 are coils,
7 and 8 are amplifiers.

Reference numeral 17 is a comparator which is connected to the electrode 1-1 and shapes the sine wave of the electrode to convert it into a logic level pulse. Reference numeral 2 is a comparator for converting the output waveform (sine wave) of the monitor electrode into a logic level pulse. 12
Is a phase comparator which connects one input end thereof to the output of the comparator 2 and the other input end thereof to the inverter 18, for example, USP.
No. 4,291,274 and the like, and the detailed description thereof is omitted, but an output is generated only when the phase difference between the input signals is detected and the phase difference exists.

The block configuration and the input output characteristic of the comparator 12 are as shown in FIGS. 3 and 4, and the input pulse (rising signal) to the input end R is input before the rising signal to the input end S. In the case, the output is Vc only during the rising signal difference.
When the rising signal is input to the input terminal S, the output becomes an open state (high impedance state).

Further, when the input pulse (rising signal) to the input terminal S is inputted before the rising signal to the input terminal R, the rising signal period output becomes the ground level (hereinafter referred to as low level L).

Further, it is in an open state except when the output shows H or L. Therefore, when the phase difference is zero, the output is kept open.

A low-pass filter 4 smoothes the output of the comparator 12. Reference numeral 5 is a voltage controlled oscillator (VCO) that outputs a signal with a duty ratio of 50% at a frequency according to the input voltage, and its input is connected to the output of the low-pass filter 4. The input voltage and output frequency of the VCO 5 have a linear function relationship, and the higher the voltage, the higher the frequency output.

Reference numeral 19 is a frequency dividing circuit for dividing the output of the VCO 5 by 32, and the output of the frequency dividing circuit is applied to the electrode 1-1 via the amplifier 7 and the coil 10. The output of the frequency divider circuit 19 is an 8-stage shift register 20.
It is connected to the D input terminal of. The output of the VCO 5 is input as a clock pulse to the clock terminal of the register 20. Since the frequency of VCO5 with respect to the output pulse of the frequency divider circuit 19 is 32 times, D for the register 20
Since the relationship between the input and the clock pulse is also 32 times, the output Q _{1 to} Q ₈ of the shift register 20 is a pulse which is deviated (delayed) by 1125 ° from 0 ° to 90 ° with respect to the D input signal. Will be output. The oscillation frequency of VCO5 is SS
It is set to 32 times the resonance frequency of M. The outputs Q _{1 to} Q ₈ of the shift register 20 are connected to the terminals 30-1 to 30-8 of the speed selection switch 30, respectively, and the output of the register 20 selected via the switch 30 outputs the amplifier 8 and the coil 11. It is applied to the electrodes 1-2 through the electrodes.

25 is an 8-stage shift register, the output of the comparator 17 is input to the D input terminal of the register, and the output of the VCO 5 is input to the clock input, so the output terminal Q ₈ outputs D A pulse delayed by 90 ° with respect to the input signal to the input end is output. That is, since the output pulse of the frequency divider circuit 19 and the output pulse of the comparator 17 have the same phase relationship, the pulse is input as the D input and the output of the VCO 5 is input as the clock.
The output Q ₈ of the stage is a pulse delayed by 90 ° with respect to the D input signal, that is, the signal of the electrode 1-1. The output Q ₈ of the shift register 25 is input to the S input of the phase comparator 12 via the inverter 18. The electrode 1-
The positional relationship between the electrode 1 and the electrode 1-3 is 90 ° apart.

Next, the operation of the embodiment shown in FIG. 2 will be described.

When a power switch (not shown) is turned on, power is supplied to the circuit and VCO5 starts oscillating at a certain frequency. The output of the VCO 5 (Fig. 5 (a)) becomes the shift clock of the shift registers 20, 25, and at the same time, it is transmitted to the frequency dividing circuit 19, so that a pulse divided by 32 (Fig. 5 (b) is output as the frequency dividing circuit 19). The pulse is input to the amplifier 7. The pulse becomes a sine wave in the resonance circuit composed of the coil 10, the electrode 1-1, etc., and is applied to the drive electrode 1-1. A sine wave having the same phase and the same frequency as the pulse shown in b) is applied.

On the other hand, the output of the frequency dividing circuit 19 is transmitted to the D input terminal of the shift register 20, and so as the Shifutokurotsuku of the register 20 output pulse of VCO5 being applied, Q ₁ to Q ₈ output of the shift register 20 is first As shown in FIGS. 5 (c) to 5 (j), the output of the frequency dividing circuit 19 is delayed by one VCO output pulse. Since the divider circuit 19 divides the VCO output by 32 as described above, each output of the register 20 is delayed by 360 ° / 32 = 11.25 ° with respect to the output of the previous stage.
The output of the frequency divider circuit from output Q ₈ is also shown in Fig. 5 (b).
11.25 × 8 = pulse delayed by 90 °.

Assuming that the switch 30 is selectively connected to the contacts 30-8, pulse amplifier 8 outputs Q ₈ of the register 20 is applied as a sine wave to the electrodes 1-2 via the coil 11.
Therefore, in this state, 90 between the electrodes 1-1 and 1-2.
° Frequency voltages with different phases will be applied.

On the other hand, in the SSM, when the phase angle between the voltage applied to the electrostrictive element of the first group and the voltage applied to the electrostrictive element of the second group is 90 °, the electro-rotational conversion efficiency is highest and the phase nucleus is The narrower it becomes, the lower the efficiency becomes, and when it is O ′, the efficiency becomes 0, that is,
SSM stops.

Therefore, when the switch 30 is connected to the contact 30-8 as described above, the SSM rotates at maximum efficiency, and the switch 30 is connected to the contact 30-8.
7, 30-6, 30-5, 30-4, 30-3, 30-2, 30-1
By switching and connecting to, the rotation efficiency decreases and the rotation speed of the SSM decreases. With such a configuration, in the present invention, the rotation speed of the SSM can be made variable by connecting the switch 30 and any of the contacts 30-1 to 30-8.

With the above operation, the rotation speed of the SSM is adjusted, and in the present embodiment, the frequency control is performed so that the SSM is always driven at the resonance rotation speed.

The frequency control operation will be described below.

Generally, in SSM, the drive electrode 1-
1 or 1-2 and the monitor electrode 1-3 have a specific relationship between the phase of the drive signal to the electrode 1-1 or 1-2 and the phase of the signal from the monitor electrode 1-3, that is, between the electrodes. The positional phase relationship of the above and the phase relationship of the signals at the electrodes show the same phase difference relationship, and in order to drive the SSM in resonance, if the above phase relationship is held, resonance drive can always be performed. In this embodiment, the electrodes 1-1 and 1-3 are arranged so as to be offset by 90 °, so that the waveforms of the electrodes 1-1 and 1-3 are also shifted by 90 ° in this embodiment. With such control, resonance drive can be performed.

In this embodiment, the comparator 12 has electrodes 1-3.
Then, the phase of the waveform at the electrode 1-1 is detected, and the phase is controlled so as to be always shifted by 90 °.

Hereinafter, this operation will be described in detail. The output of the electrodes 1-3 is converted into a pulse by the comparator 2 and transmitted to the R input of the comparator 12. On the other hand, the waveform of the electrode 1-1 is converted into a pulse by the comparator 17, and the register 25
Is transmitted to the D input of. Since the shift clock pulse of the register 25 is the output of the VCO 5, the output Q ₈ of the shift register 25 is a pulse delayed by 90 ° in phase from the waveform of the electrode 1-1.

The pulse from the output Q _{8 of the} register 25 is the inverter 18
It is inverted by and is transmitted to the S input of phase comparator 12. As described above, the pulse 2 of the output Q ₈ of the register 25 becomes a pulse delayed by 90 ° as shown in FIG. 6 (b) when the pulse applied to the amplifier 7 is shown in FIG. 6 (a). Since it is inverted and transmitted to the S input of the comparator 12, the pulse to the S input of the comparator 12 is the sixth pulse.
As shown in FIG. 6 (c), the pulse is advanced by 90 ° with respect to the pulse in FIG. 6 (a).

Therefore, if the phase of the pulse to the S input of the comparator 12 and the phase of the pulse to the R input of the comparator 12 match, there is a 90 ° phase difference between the electrode 1-3 and the electrode 1-1. Therefore, the resonance state is detected. Further, the comparator 12 holds the output in the open state if the input signal phases to the input terminals R and S match each other, so that the VCO 5 continues to hold the oscillation state and is driven at the resonance frequency. Continue to be done.

Further, when the SSM is not in the resonance state, the signal from the electrode 1-3 is shifted from the signal of the electrode 1-1 by 90 ° to the front and back. Therefore, in this case, the pulse phases to the R and S input terminals of the comparator 12 do not match, and, for example, as shown in FIG. 4, the rising signal of the pulse to the R input terminal of the comparator 12 is sent to the S input terminal. When the pulse rising signal is generated earlier, the output of the rising signal difference comparator 12 becomes H, and conversely, the rising signal to the S input terminal is generated before the rising signal to the R input terminal. When it is, the output of the rising signal difference comparator 12 becomes L. Therefore, when the pulse of the comparator 2, that is, the phase of the waveform from the electrode 1-3 is advanced with respect to the phase of the pulse from the inverter 18, that is, the phase difference between the waveforms of the electrodes 1-1 and 1-3. Becomes 90 ° or more, the output of the comparator 12 becomes H for the phase difference period, and the H is input to VOC5 via the low-pass filter 4, the input voltage to VOC5 increases, and the oscillation frequency of VOC5 increases correspondingly. . Oscillation frequency of VOC5, that is, electrodes 1-1,
As the drive frequency to 1-2 becomes higher, the signal input to the electrode 1-1 has a characteristic of changing in the phase advancing direction than the signal generated at the electrode 1-3. 1
The phase difference between 1 and 3 is controlled in the 90 ° direction.

On the contrary, when the phase difference between the electrodes 1-1 and 1-3 is within 90 °, the rising signal to the S input terminal of the comparator 12 is generated earlier than the rising signal to the R input terminal. For,
The output of the phase difference comparator 12 becomes L, and the oscillation frequency of VCO5 decreases, so the drive frequency to the electrodes 1-1 and 1-2 also decreases, and the phase of the waveform of electrodes 1-1 and 1-3 increases. The phase difference between the electrodes 1-1 and 1-3 shifts to the 90 ° direction.

In this way, the phase difference between the waveforms of the electrodes 1-1 and 1-3 is detected, the drive frequency of the SSM is controlled so that this phase difference is always 90 °, and the drive control of the SSM is always in the resonance state. Becomes

FIG. 7 is a circuit diagram showing a second embodiment of the present invention. 7th
In the figure, the same symbols are attached to the same components as in the second embodiment.

In FIG, 21 receives the output Q ₁ to Q ₈ of the shift register 20 to the input D ₀ to D _7, the control terminals A, B, among the input D ₀ to D ₇ in response to the code input signal to the C It is a multiplexer that selects one and sends the output of register 20 applied to the selected input. The multiplexer 21 is configured to selectively select the output of the latter stage of the register 20 as the binary signal as the input code to the terminals A, B and C increases.

Reference numeral 41 is a pulse oscillating circuit having a variable resistor 50 for setting the motor rotation speed, and the frequency of the output pulse thereof is variable based on the resistance value.

43 is a moving body that is rotationally driven by progressive vibration waves generated in the stator of the SSM, and 44 is a pulse plate that rotates with the rotation of the moving body. To be done. 45 is a reflector including a light-emitting source and a transistor, which forms an output each time the translucent pattern passes through the reflector 45 by the rotation of the pulse plate 44, and outputs a number of signals corresponding to the rotation speed of the pulse plate. Form. 42 is a comparator for converting the signal from the reflector 45 into a pulse, 24 is a phase comparator having inputs Rin and Sin, and the phase comparator is a rising signal to the input Rin as shown in FIG. Is supplied earlier than the rising signal to the input Sin, the phase difference period output R ₀ of the rising signal is set to L, and conversely, the rising signal to the input Sin is more than the rising signal to the input Rin. Output the phase difference period of the rising signal when supplied first
S ₀ is taken as L.

An up-down counter 22 is connected to the outputs R ₀ and S ₀ of the phase comparator through OR gates 33 and 34, and operates in response to a rising signal at the input.

Reference numeral 31 is an AND gate that receives the outputs Q _{0 to} Q ₂ of the counter 22, 32 is an inverting input AND gate, 35 and 36 are inverters, and 37 and 38 are light emitting diodes.

Next, the operation of the embodiment shown in FIG. 7 will be described.

When a power switch (not shown) is turned on, a predetermined value is set in the counter 22 by a power up operation circuit (not shown) and the multiplexer 21 is set to the register 20.
The pulse from the predetermined output terminal of is selected and transmitted to the amplifier 8.

Further, when the power is turned on, the circuit is in an operating state, and as described in the embodiment of FIG. 2, as a drive signal to the drive electrodes 1-1 and 1-2, at the resonance frequency, the frequency dividing circuit 19 is operated. A sine wave having a phase relationship between the output and the output pulse of the multiplexer 21 is applied to rotate the SSM. The rotation of the SSM is detected by the reflector 45, and a pulse having a frequency corresponding to the rotation speed is transmitted to the input Sin of the comparator 24 via the comparator 42. On the other hand, a set speed value is set in the resistor 50, and a pulse having a frequency corresponding to the set value is sent from the pulse oscillation circuit 41 and input to Rin of the comparator 24.
Here, the case where the rotation speed of the SSM is slower than the set value will be described.

In this case, the frequency of the pulse from the comparator 42 is lower than the frequency of the pulse from the pulse oscillation circuit,
Input to comparator 24 Pulse to Rin is input Sin
More than the pulse to the resulting comparator
24 sends out the outputs R ₀ to L, causing the counter 22 to count up, so that the multiplexer 22 causes the register 20 to count.
The pulse from the output terminal of the latter stage is selected and transmitted to the amplifier 8. Therefore, the SSM increases the rotation speed. In this way, when the frequency of the pulse from the reflector 45 and the frequency of the pulse from the pulse oscillation circuit 41 match in the course of the increase in the rotation speed of the SSM, the phase of the pulse to the input Rin, Sin to the comparator 24 Since the outputs match, the outputs R ₀ and S ₀ of the comparator 24 are in the open state and the counter
22 is held in that setting state, the pulse from the output end of the Gilester 20 selected at that time is continuously applied to the amplifier 8, and the SSM is rotationally controlled at the speed set by the resistor 50.

On the contrary, when the rotation speed of the SSM is faster than the set value, the output S of the comparator 24 outputs L, so that the counter 22 is down-counted and the output end of the previous stage of the register 25 is selected. When the rotation speed decreases, and the speed matches the set value, the counter 22 stops counting down, and thereafter the rotation is controlled in that state.

Incidentally, in the above rotation speed control, when all the outputs H from the outputs Q _{0 to} Q ₂ of the counter 22, that is, the register
When the output Q _{8 of} 20 is selected and the SSM is driven at the highest speed, H is sent from the AND gate 31 and the light emitting diode 37.
Is turned on to warn of this, and the up input of the counter 22 is held at H so that the counter 22 is not affected by the output of the comparator 24 thereafter.

On the contrary, when all the outputs Q ₀ -Q ₂ of the counter 22 become L, H is sent from the NAND gate 32 and the light emitting diode 38
Is turned on to warn of this, and the down input of the counter 23 is held at H so that the counter 22 is not affected by the output of the comparator 24 thereafter.

As described above, according to the present invention, the frequency signal applied to the first electro-mechanical energy conversion element in the SSM is obtained by dividing the oscillator output by the frequency dividing circuit, and the frequency dividing circuit output is output by the oscillator. Is used as a clock to shift in a shift register, an output stage of this register is selected, and an output from this output stage is applied to the second electro-mechanical energy conversion element, thereby being applied to each energy conversion element. Since the phase difference of the frequency signal is adjusted and the rotation speed is controlled, the present invention has the effect of rotating at any rotation speed with high accuracy.

Although in the embodiment, the electrostrictive element is polarized and then formed on the stator, individual electrostrictive elements may be provided on the stator. Further, an electromechanical energy conversion element such as a piezoelectric element may be used as the electrostrictive element.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an electrode shape of a stator of a vibration wave motor according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a drive circuit for the vibration wave motor according to the present invention, and FIG. 2 is a block diagram showing the block configuration of the illustrated comparator 12,
FIG. 4 is a waveform diagram showing the input / output characteristics of the comparator 12 shown in FIG. 3, and FIGS. 5 (a) to 5 (j) are VCO5 shown in FIG.
Waveform diagrams showing the output waveforms of the frequency divider circuit 19 and the shift register 20, FIGS. 6 (a) to 6 (d) are waveform diagrams for explaining the operation of the drive circuit of FIG. 2, and FIG. 7 is related to the present invention. FIG. 8 is a circuit diagram showing another embodiment of the drive circuit of the vibration wave motor, FIG. 8 is a waveform diagram for explaining the operation of the comparator 24 shown in FIG. 7, and FIG. 9 is a configuration of the drive section of the vibration wave motor. It is a circuit diagram showing. 5 …… VCO 19 …… divider circuit 20,25 …… shift register 30 …… switch 7,8 …… amplifier 1-1,1-2 …… electrode 1 …… stator

Claims (1)

[Claims] 1. Electricity of first and second groups arranged on a vibrating body.
Oscillation at a predetermined frequency in a speed control circuit of a vibration wave motor that applies frequency signals of different phases to the mechanical energy conversion element to excite the vibration body and generate a vibration wave in the vibration body to obtain a driving force. An oscillator, a frequency dividing circuit for dividing an output pulse from the oscillator, a plurality of stages of shift register circuits for connecting an output terminal of the frequency dividing circuit to an input terminal and a clock terminal for the oscillator, and the shift circuit. Selecting means for selecting the output stage of the register circuit, and applying the frequency divider circuit output to the first group of electro-mechanical energy conversion elements, and to the second group of electro-mechanical energy conversion elements. The output from the output stage of the shift register circuit selected by the selecting means is applied, and the electric power of the first and second groups is selected by selecting the output stage of the shift register circuit. A speed control circuit for a vibration wave motor, characterized by adjusting the phase of a frequency signal applied to a mechanical energy conversion element.