JPH07202583A - Cmos protection circuit - Google Patents

Abstract

PURPOSE:To provide the CMOS protection circuit corresponding to the CMOS circuit according to the mixing of plural power voltages. CONSTITUTION:A Nch MOS transistor 5 whose drain and gate are connected to the input terminal and whose source is connected to the power supply is provided as a transistor for protection circuit. For example, even when input waveform with 5V is inputted for the CMOS LSI of the power supply voltage 3V, no constant current flows from the input terminal to the power supply. The input capacity component is increased by the effect of the Nch MOS transistor 5, the wave height value of the static destruction voltage is reduced. There is a current path from the input terminal to the power supply, and the breakdown strength for the static destruction is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a CMOS protection circuit.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional CMOS protection circuit is a power supply side protection circuit in which a gate and a source of a Pch MOS transistor 3 are connected, a source is connected to a power supply and a drain is connected to an input terminal. is there. However, as in recent years, CMOS is used with a plurality of power supply voltages mixed.
In the environment where LSI is used, when an input waveform with a potential higher than the power supply voltage is input to the input terminal, Pch M
Since a current constantly flows through the OS transistor 3 and power consumption increases, the characteristics of the CMOS circuit are impaired.

Further, in the circuit of FIG. 3, since the Pch MOS transistor 3 is removed from the protection circuit, the structure is such that a steady current does not flow. Therefore, there is no protection circuit on the power supply side and electrostatic breakdown occurs. Is weak against.

[0004]

In the circuit of FIG. 2, when a CMOS LSI is used in an environment in which a plurality of power supply voltages are mixed, when the input voltage is higher than the power supply voltage, Pch M
Since a constant current flows through the OS transistor 3, there is a problem that the characteristic of the CMOS circuit, which is low power consumption, is lost. Further, the circuit of FIG. 3 has a problem that it is vulnerable to electrostatic breakdown because there is no protection circuit on the power supply side.

[0005]

In order to solve the above problems, a gate and a drain are connected, and a drain of an Nch MOS transistor whose source is connected to a power supply is connected to an input terminal to form a CMOS protection circuit.

[0006]

FIG. 1 shows an embodiment of the present invention. As a transistor for the protection circuit, an Nch MOS transistor 5 having a gate and a drain at input ends and a source connected to a power supply is provided. Compared with FIG. 2, for example, C with a power supply voltage of 3V
Even if a 5V input waveform is input to the MOS LSI, a steady current does not flow from the input terminal side to the power supply side. When compared with FIG. 3, Nch
Since the input capacitance component increases due to the effect of the MOS transistor 5, the peak value of the electrostatic breakdown voltage decreases, and the current path from the input terminal to the power supply side also exists, so that the breakdown voltage against electrostatic breakdown improves.

[0007]

As described above, the present invention is a CMOS protection circuit compatible with an environment in which a plurality of voltage power supplies coexist.
This is effective in improving the breakdown voltage against electrostatic breakdown without impairing the characteristics of the MOS circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional CMOS protection circuit in a single power supply environment.

FIG. 3 is a diagram showing a conventional CMOS protection circuit compatible with a mixed power supply environment.

[Explanation of symbols]

 1 Pch MOS transistor 2 Nch MOS transistor 3 Pch MOS transistor 4 Nch MOS transistor 5 Nch MOS transistor

Claims (2)

[Claims] 1. An Nch MOS having a gate and a drain connected to an input terminal of a CMOS circuit and a source connected to a power supply.
A CMOS protection circuit in which a transistor is provided as an input buffer of a CMOS circuit. 2. The CMOS protection circuit according to claim 1, wherein the input terminal is provided with a protection circuit on the ground power supply side.