JPH07202582A - Differential amplifier - Google Patents

Abstract

PURPOSE:To reduce the noise to be generated when a transistor is connected to the front stage of a differential amplifier part by negative-feedbacking the output signal of the differential amplifier part to the other transistor. CONSTITUTION:An output signal S4 of a differential input stage 5A which is obtained by inputting an input signal S1 to the stage 5A is inputted to a differential amplifier stage 3. A differential amplifier circuit 5 feedbacks an output signal S5 through the stage 5A to the stage 3 and gives the DC voltage component different from the DC voltage component of the input signal S1 to the output signal S5. Thus, the input signal S1 is inputted to a transistor Q1 in the stage 5A and the output signal S4 of a transistor Q2 negatively feeding back the signal S5 in the feedback loop of the stage 3. Then, the output signal S5 of the stage 3 is negatively fed back and the noise to be generated can be reduced more.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 8 and 9) Problem to be Solved by the Invention (FIG. 10) Means for Solving the Problem (FIGS. 1 and 5) Action (FIG. 1) Embodiment (FIG. 1) ~ Figure 7) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit, and can be applied to, for example, one formed on an integrated circuit chip.

[0003]

2. Description of the Related Art Conventionally, in this type of differential amplifier circuit, in order to give a DC voltage component different from a DC voltage component of an input signal to an output signal, it is considered that an emitter follower is connected to a stage before the differential amplifier stage. There is.

As shown in FIG. 8, in the differential amplifier circuit 1, an input signal S1 is applied to the base of a PNP transistor Q ₁ whose collector is connected to the ground line GND. In the transistor Q ₁ , the emitter is connected to the power source V _CC via the current source 2.
And the output signal S2 of the emitter is input to the inverting input terminal P ₁ of the differential amplifier stage 3. Output signal S of the differential amplification stage 3
3 is directly fed back from the output terminal P ₃ to the non-inverting input terminal P ₂ .

Next, the input signal S1 is input with the ground line GND as a reference, and the output signal S3 is supplied with the ground line GND.
The differential amplifier circuit 4 shown in FIG. 9 is used in the case where a constant DC voltage component with reference to is output. In the differential amplifier circuit 4, the output terminal P ₃ of the configuration of the differential amplifier circuit 1 is not directly connected to the non-inverting input terminal P ₂ , but the resistor R is used.
It is connected to the non-inverting input terminal P ₂ via ₁ . The middle point of connection between the resistor R ₁ and the non-inverting input terminal P ₂ is connected to the ground line GND via the resistor R ₂ .

Incidentally, the emitter area of the transistor Q ₁ is the same as the emitter area of each transistor in the differential amplifier stage 3. The DC voltage component V _DC of the output signal S3 at this time is determined according to the ratio of the resistors R ₁ and R ₂ , and

[Equation 1] It is represented by.

[0007]

However, when the direct voltage component shifting emitter follower is connected to the preceding stage of the differential amplifier stage 3 as in the above-mentioned configuration, there is a problem that noise increases due to the emitter follower.

Considering, for example, noise generated in the differential amplifier circuit 4 in terms of signal flow, as shown in FIG. 10, the input voltage V _IN of the input signal S1 is the noise voltage V _{N (Q1)} generated in the transistor Q _1. Is added, and a feedback voltage V _{A obtained} by multiplying the output voltage V _OUT of the output signal S3 by a feedback amount β is subtracted.
The feedback amount β is

[Equation 2] Required by.

Further, the noise voltage V _{N (OP)} generated in the input differential pair transistors of the differential amplifier stage 3 is added to this voltage.
Is added and amplified by the open loop gain A of the differential amplifier stage 3 to become the output voltage V _OUT . This gives

[Equation 3] And the following equation,

[Equation 4] To get The output voltage V _OUT is calculated by the following equation from the equations (3) and (4):

[Equation 5] It is represented by.

[0010] By now by emitter area of the transistor Q ₁ is the same as the emitter area of each of the transistors in the differential amplifier stage 3, the transistors of the input differential pair of transistors Q ₁ and the differential amplifier stage 3 If the generated noise voltages V _{N (Q1)} and V _{N (OP)} are all equal and their values are V _N , the noise voltage V _{N (Q1)} is

[Equation 6] Becomes

Similarly, the noise voltage V _{N (OP)} is expressed by the following equation, because the input differential pair transistors are arranged in the differential amplification stage 3.

[Equation 7] And the equation (5) is

[Equation 8] Can be expressed as

As a result, the output voltage V _OUT is expressed by equation (6)
From equation (8),

[Equation 9] Becomes In the equation (9), the first term is the signal component and the second term is the noise component, and it is necessary to suppress the noise component expressed by the second term as much as possible.

The present invention has been made in consideration of the above points, and proposes a differential amplifier circuit capable of further reducing the noise generated when a transistor is connected to the preceding stage of the differential amplifier section as compared with the conventional case. It is what

[0014]

In order to solve such a problem, in the present invention, a transistor differential pair Q ₁ and Q _{2 is used.}
Input section 5 having a transistor Q ₁ and an input signal S 1 is input to _one transistor Q ₁ of the transistor differential pair Q ₁ and Q _2.
A and the other transistor Q ₂ of the transistor differential pair Q ₁ and Q ₂ is supplied with a predetermined current by the current adjusting means R ₃ and the output signal S4 obtained from the other transistor Q ₂ is supplied to the differential input terminal P ₁ and it provided the differential amplifier 3 for amplifying inputted to one input terminal P ₂ of P _2, by connexion output signal to the negative feedback of the output signal S5 of the differential amplifier 3 to the other transistor Q ₂ Negative feedback control of S5.

[0015] In the present invention, it includes a transistor differential pair Q ₃ and Q _4, transistor differential pair Q ₃ and Q
_The differential input section 8A in which the input signal S1 is input to one of the _four transistors Q ₃ and the transistor differential pair Q ₃ and Q ₄
Of the other transistor Q ₄ to the current adjusting means one input P ₂ of by the R ₃ by supplying a connexion predetermined current the other transistor Q differential input the output signal S6 obtained from ₄ P ₁ and P ₂
To the differential amplifier 3 for amplifying the differential signal, and the output signal S7 of the differential amplifier 3 is input, and the component adjustment signal S8 of the output signal S7 having the frequency component adjusted according to the frequency of the frequency component of the output signal S7. Frequency component adjusting means R ₁ and R for outputting
_2, R _5, R _6, provided with C ₁ and C _2, for negative feedback controlling the output signal S7 by connexion differential amplifier 3 to negative feedback component adjustment signal S8 to the other transistor Q _4.

[0016]

The input signal S1 is applied to _one transistor Q ₁ of the transistor differential pair Q ₁ and Q ₂ arranged in the differential input section 5A.
Is input to the differential amplification section 3 and the output signal S5 of the differential amplification section 3 is negatively fed back into the feedback loop of the differential amplification section 3 and the output signal S4 of the other transistor Q ₂ is input to the differential amplification section 3. By performing the negative feedback control of the output signal S5 of the differential amplifier 3, the generated noise can be further reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 8 are designated by the same reference numerals, 5 indicates a differential amplifier circuit formed on the integrated circuit as a whole, and an input signal S1 is input to the differential input stage 5A. The output signal S4 of the differential input stage 5A thus obtained is input to the differential amplification stage 3. Further, the differential amplifier circuit 5 includes the differential amplifier stage 3
Output signal S5 of the differential amplifier stage 3 via the differential input stage 5A.
By feeding back to the output signal S5, a DC voltage component different from the DC voltage component of the input signal S1 is given to the output signal S5.

The differential input stage 5A comprises a PNP type transistor Q ₁ and an NPN type transistor Q ₂ whose emitters are commonly connected, and the input signal S1 is applied to the base of the transistor Q ₁ whose collector is connected to the ground line GND. Is entered. The collector of the transistor Q ₂ is connected to the power supply V _CC via the resistor R ₃ , and the output signal S4 of the collector is output.
Is input to the non-inverting input terminal P ₂ of the differential amplifier stage 3.

The differential amplifier stage 3 has a power source V _CC as compared with the power source V _CC.
A voltage lower by ₀ minutes is applied to the inverting input terminal P ₁ , and the output signal S5 is directly input to the base of the transistor Q ₂ .

In FIG. 2 in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, 6 indicates a differential amplifier circuit formed on the integrated circuit as a whole, and the input signal S1 indicates the ground line GND. It is input to the base of the transistor Q ₁ as a reference, and outputs an output signal S5 having different DC voltage component and a DC voltage component of the input signal S1 based on the ground line GND.

In the differential amplifier circuit 6, the output terminal P ₃ of the differential amplifier circuit 5 is not directly connected to the base of the transistor Q ₂ , but the transistor Q is connected via the resistor R _1.
2 connected to the base. Further, the connection midpoint between the resistor R ₁ and the base of the transistor Q ₂ is connected to the ground line GND via the resistor R ₂ . Also in the differential amplifier circuit 6, the DC voltage component V _DC expressed by the equation (1) is applied to the output terminal P ₃ . Incidentally, the transistors Q ₁ and Q
The emitter area of ₂ is the same as the emitter area of the transistors in the differential amplifier stage 3.

As in the conventional case, for example, the differential amplifier circuit 6
Considering the noise generated in Fig. 3 by the signal flow,
As shown in, the input voltage V _IN of the input signal S1 is the feedback voltage V _{A obtained} by multiplying the output voltage V _OUT of the output signal S5 by the feedback amount β.
And the noise voltage V _{N (Q1, Q2)} generated in the transistors Q ₁ and Q ₂ is added. Further, this voltage is amplified by the gain A ₁ times of the differential amplifier composed of the transistors Q ₁ and Q ₂ and the resistor R ₃ , and the noise voltage V generated in the input differential pair transistor of the differential amplification stage 3 is generated. _{N (OP)} can be added. Further, this voltage is amplified by the open loop gain A ₂ times of the differential amplifier stage 3 and becomes the output voltage V _OUT .

This gives the following equation:

[Equation 10] And the following equation,

[Equation 11] To get The output voltage V _OUT is calculated by the following equation from the equations (10) and (11):

[Equation 12] It is represented by.

Since the emitter areas of the transistors Q ₁ and Q ₂ are the same as the emitter areas of the transistors in the differential amplification stage 3, the input differential of the transistors Q ₁ and Q ₂ and the differential amplification stage 3 is determined. Assuming that the noise voltages generated in the pair of transistors are all equal, and the value is V _N , the noise voltage V _{N (Q1, Q2)} is the square root of the square sum of the noise voltages of the transistors Q ₁ and Q ₂ , that is,

[Equation 13] Becomes

Similarly, the noise voltage V _{N (OP)} is expressed by the following equation, because the input differential pair transistor is arranged in the differential amplification stage 3.

[Equation 14] Then, the equation (12) is also the following equation,

[Equation 15] Can be expressed as As a result, the output voltage V _OUT is expressed by equation (13)
From equation (15),

[Equation 16] Becomes

Assuming that A ₁ is sufficiently large, the output voltage V _OUT can be expressed by the following equation:

[Equation 17] Becomes

With the above structure, the output voltage V of the embodiment is
Noise component of equation (17) representing _OUT and conventional output voltage V
Comparing with the noise component of equation (9) representing _OUT , the following equation,

[Equation 18] Becomes That is, it can be seen that the noise component is reduced by 1.76 [dB].

According to the above configuration, the input signal S1 is input to the transistor Q ₁ in the differential input stage 5A and is put in the feedback loop of the differential amplification stage 3 to output the output signal S of the differential amplification stage 3.
5 is negatively fed back, and the output signal S4 of the transistor Q ₂ is input to the differential amplification stage 3 to perform negative feedback control of the output signal S5 of the differential amplification stage 3 to further reduce the generated noise (here, It can be reduced by about 1.8 [dB]).

In the conventional differential amplifier circuits 1 and 4, a total of three transistors, the transistor Q ₁ and the input differential pair transistor of the differential amplifier stage 3, are involved in noise generation. On the other hand, in the differential amplifier circuits 5 and 6, a total of two transistors Q ₁ and Q ₂ are involved in noise generation.

Therefore, it is not necessary to increase the emitter area of the transistors Q ₁ and Q ₂ when lowering the noise level, and accordingly, the chip area can be small when formed on an integrated circuit. Further, since the transistors Q ₁ and Q ₂ can use vertical structure transistors, they can also be used as low noise transistors such as a double base.

In the above embodiment, the case where the transistor Q ₂ is connected to the power supply V _CC via the resistor R ₃ has been described, but the present invention is not limited to this, and the differential amplification shown in FIG. The current source 2 may be connected instead of the resistor R ₃ as in the circuit 7. Also in this case, the same effect as described above can be obtained.

Further, in the above-described embodiment, the emitter areas of the transistors Q ₁ and Q _{2 in} the preceding stage are the same as the emitter areas of the respective transistors in the differential amplifier stage 3, and the feedback circuit includes resistors R ₁ and R 2. _Although the case where the feedback amount β is constant regardless of the frequency component has been described above, the present invention is not limited to this, and the emitter area of the transistor at the preceding stage which becomes a noise source is within the differential amplification stage 3. The present invention can also be applied to the case where the transistor is formed to have a predetermined size of the emitter area of each transistor, and the case where the feedback circuit adjusts the frequency component of the output signal of the differential amplification stage to perform feedback.

As shown in FIG. 5, in the reproduction equalizer amplifier circuit 8 formed on the integrated circuit, a differential input stage 8A is arranged in place of the differential input stage 5A in the configuration of the differential amplifier circuit 6. Therefore, the output signal S6 of the differential input stage 8A obtained by inputting the input signal S1 to the differential input stage 8A is input to the differential amplification stage 3.

Further, the reproduction equalizer amplifier circuit 8 outputs the output signal S7 of the differential amplifier stage 3 to the feedback circuit composed of the resistors R ₁ , R ₂ , R ₅ , R ₆ and the capacitors C ₁ , C ₂ and the differential input stage 8A.
The DC voltage component different from the DC voltage component of the input signal S1 is applied to the output signal S7 by being fed back to the differential amplification stage 3 via the. That is, the reproduction equalizer amplifier circuit 8
In the configuration of the differential amplifier circuit 6, the feedback resistor R
_In addition to ₁ , a series circuit consisting of a resistor R ₅ and a capacitor C ₁ is connected in parallel with the resistor R ₁ . In addition to the resistor R ₂ , a series circuit including a resistor R ₆ and a capacitor C ₂ is connected in parallel with the resistor R ₂ . Thus the feedback signal S8 output signal S7 frequency component is adjusted is adapted to be input to the base of the transistor Q _4.

The differential input stage 8A comprises a PNP type transistor Q ₃ and an NPN type transistor Q ₄ whose emitters are commonly connected, and the input signal S1 is applied to the base of the transistor Q ₃ whose collector is connected to the ground line GND. Is entered. The base of the transistor Q ₃ is connected to the ground line GND via the resistor R ₄ . Transistor Q
_The collector ₄ is connected to the power supply V _CC via the resistor R _3, and inputs the collector output signal S6 to the non-inverting input terminal P ₂ of the differential amplification stage 3.

The emitter areas of the transistors Q ₃ and Q ₄ are formed N times and M times the emitter areas of the transistors in the differential amplification stage 3, respectively. Thus the transistors Q ₃ and Q ₄ noise transistor Q ₁
And Q ₂ noises V _{N (Q1)} and V _{N (Q2)} are 1 / N and 1 / M, respectively, and transistors Q ₃ and Q ₄
The total noise V _{N (Q3, Q4)} of

[Formula 19] Becomes Since the emitter areas of the transistors Q ₁ and Q ₂ are the same as the emitter areas of the transistors in the differential amplification stage 3,

[Equation 20] Then, from equations (19) and (20),

[Equation 21] Becomes Thus the transistors Q ₃ and Q total noise V _N at _{4 (Q3, Q4)} is further can be seen to decrease.

Since the reproduction equalizer amplifier circuit 8 has a high gain, the DC voltage component of the output signal S7 is shifted so that the waveform of the output signal S7 is not crushed. Set the base-emitter voltage of transistors Q ₃ and Q ₄ to V
_{Assuming BE (Q3)} and V _{BE (Q4)} , the shift amount of the DC voltage component due to the resistors R ₁ and R _{2 is given} by

[Equation 22] Becomes

The output signal S7 is a frequency component of the middle band is Shiyoto capacitor C _2. This allows resistors R ₂ and R
_If the parallel resistance of ₆ is R ₂ // R ₆ , the gain G _{MID at the} middle frequency is

[Equation 23] Becomes

The output signal S7 has its high frequency components shorted by the capacitor C ₁ . This causes resistors R ₁ and R
_If the parallel resistance of ₅ is R ₁ // R ₅ , the gain G _{HIGH at} high frequency is

[Equation 24] Becomes The rough shape of this frequency characteristic curve is as shown in FIG.

Further, in the above embodiment, the case where the collector of the transistor Q ₁ is connected to the ground line GND and the output signal S4 of the collector of the transistor Q ₂ is input to the non-inverting input terminal P ₂ of the differential amplifier stage 3 Although described, the present invention is not limited to this, and is also applied to a case where the input position of the input signal S1 to the differential input stage 5A and the output position of the output signal to the differential amplification stage are reversed as shown in FIG. it can.

That is, in the differential amplifier circuit 9, the collector of the transistor Q ₂ of the differential input stage 5A is connected to the power supply V _CC , and the input signal S1 is input to the base. The collector of the transistor Q ₁ is connected to the ground line GND via the resistor R _3, and the output signal S9 of the collector is input to the non-inverting input terminal P 2 of the differential amplification stage 3. Differential amplification stage 3
Is the power source V at the inverting input terminal P ₁ compared to the ground line GND.
_A high voltage is applied for ₀ minutes, and the output signal S of the output terminal P ₃
10 is directly fed back to the base of the transistor Q ₁ .

Further, in the above-described embodiment, the case where the differential amplifier circuits 5 and 6 are formed on the chip of the integrated circuit has been described, but the present invention is not limited to this, and the differential amplifier circuits are separate elements. It can also be applied to the case where it is configured by etc.

Further, in the above-mentioned embodiment, the output signal S4 (or S6 or S9) of the differential input stage 5A is input to the non-inverting input terminal P _{2 so} that the non-inverting output signal S is output from the differential amplifying stage 3.
5 (or S7 or S10) is output, but the present invention is not limited to this, and the output signal of the differential input stage is input to the inverting input terminal and the inverted output signal is output from the differential amplification stage. It can also be applied in cases.

Further, in the above-described embodiment, the differential input stage 5A is composed of the PNP type transistor Q ₁ and the NPN type transistor Q ₂ whose emitters are commonly connected, and the transistor Q ₁ or the transistor Q _{2 is connected} to the differential amplifying stage. However, the present invention is not limited to this, and the differential input stage is a transistor differential pair of PNP types or a transistor differential pair of NPN types. Input the input signal to one of the transistors, put it in the feedback loop of the differential amplifier, and feed back the output signal of the differential amplifier to the differential amplifier. It can also be applied to the case where negative feedback control is performed on the output signal of the differential amplifier.

[0046]

As described above, according to the present invention, the input signal is input to one of the transistors of the transistor differential pair arranged in the differential input section, and the input signal is input to the feedback loop of the differential amplifying section. The noise generated is further reduced by inputting the output signal of the other transistor, which is the negative feedback of the output signal of the dynamic amplification unit, to the negative amplification control of the output signal of the differential amplification unit. The obtained differential amplifier circuit can be realized.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a differential amplifier circuit according to the present invention.

FIG. 2 is a connection diagram for explaining a differential amplifier circuit according to an embodiment.

FIG. 3 is a signal flow chart showing the flow of the signal.

FIG. 4 is a connection diagram showing a differential amplifier circuit according to another embodiment.

FIG. 5 is a connection diagram for explaining a reproduction equalizer amplifier circuit according to another embodiment.

FIG. 6 is a characteristic curve diagram showing the frequency characteristic of the gain of the output signal.

FIG. 7 is a connection diagram showing a differential amplifier circuit according to another embodiment.

FIG. 8 is a connection diagram for explaining a conventional differential amplifier circuit.

FIG. 9 is a connection diagram for explaining a conventional differential amplifier circuit.

FIG. 10 is a signal flow chart showing the flow of the signal.

[Explanation of symbols]

1, 4 to 9 ... Differential amplifier circuit, 2 ... Current source, 3 ... Differential amplifier stage, 5A, 8A ... Differential input stage.

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[Procedure amendment]

[Submission date] March 18, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 10

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

As shown in FIG. 8, in the differential amplifier circuit 1, the input signal S1 is applied to the base of a PNP transistor Q ₁ whose collector is connected to the ground line GND. The transistor Q ₁ has a power supply V
_It is connected to _CC and inputs the output signal S2 of the emitter to the non-inverting input terminal P ₁ of the differential amplifier stage 3. The output signal S3 of the differential amplifier stage 3 is directly fed back from the output end P ₃ to the inverting input end P ₂ .

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

Next, the input signal S1 is input with the ground line GND as a reference, and the output signal S3 is supplied with the ground line GND.
The differential amplifier circuit 4 shown in FIG. 9 is used in the case where a constant DC voltage component with reference to is output. In the differential amplifier circuit 4, in the configuration of the differential amplifier circuit 1, the output terminal P ₃ is directly connected to the inverting input terminal P ₂ and the resistance R ₁ is replaced.
Is connected to the inverting input terminal P ₂ via. Also the resistance R
_The midpoint of connection between ₁ and the inverting input terminal P ₂ is connected to the ground line GND via the resistor R ₂ .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

Incidentally, the emitter area of the transistor Q ₁ is the same as that of the transistor of the input differential pair of the differential amplifier stage 3. The DC voltage component V _DC of the output signal S3 at this time is determined according to the ratio of the resistors R ₁ and R ₂ , and

[Equation 1] It is represented by.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010] Here, by the emitter area of the transistor Q ₁ is the same as the emitter area of the transistor of the input differential pair of the differential amplifier stage 3, the input differential pair of transistors Q ₁ and the differential amplifier stage 3 If the noise voltages V _{N (Q1)} and V _{N (OP)} generated in the transistor are all equal and the value is V _N , the noise voltage V
_{N (Q1)} is the following equation,

[Equation 6] Becomes

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014]

In order to solve such a problem, in the present invention, a transistor differential pair Q ₁ and Q _{2 is used.}
And a differential input section 5 in which the input signal S1 is input to _one transistor Q ₁ of the transistor differential pair Q ₁ and Q _2.
A and the transistor differential pair Q ₁ and Q ₂ of the other transistor Q ₂ to the current adjustment means by the R ₃ by supplying a connexion predetermined current differential input the output signal S4 obtained from the other transistor Q ₂ P ₁ , And a differential amplifier 3 that is input to _one input terminal P ₁ of P ₂ and amplifies, and outputs the output signal S 5 of the differential amplifier 3 by negatively feeding it back to the other transistor Q ₂ . Negative feedback control of S5.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

[0015] In the present invention, it includes a transistor differential pair _{Q 3} and _{Q 4,} transistor differential pair _{Q 3} and Q
A differential input section 8A to be inputted an input signal S1 to the one transistor _{Q 3} of _4, the transistor differential pair _{Q 3} and _{Q 4}
Of the other transistor Q ₄ to the current adjusting means one input terminal P ₁ of by the R ₃ by supplying a connexion predetermined current the other transistor Q differential input the output signal S6 obtained from ₄ P ₁ and P ₂
To the differential amplifier 3 for amplifying the differential signal, and the output signal S7 of the differential amplifier 3 is input, and the component adjustment signal S8 of the output signal S7 having the frequency component adjusted according to the frequency of the frequency component of the output signal S7. Frequency component adjusting means R ₁ and R for outputting
₂ , R ₅ , R ₆ , C ₁ and C ₂ are provided, and the component adjustment signal S8 is negatively fed back to the other transistor Q ₄ to control the output signal S7 of the differential amplifier 3 in a negative feedback manner.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

The differential input stage 5A comprises a PNP type transistor Q ₁ and an NPN type transistor Q ₂ whose emitters are commonly connected, and the input signal S1 is applied to the base of the transistor Q ₁ whose collector is connected to the ground line GND. Is entered. The collector of the transistor Q ₂ is connected to the power supply V _CC via the resistor R ₃ , and the output signal S of the collector is output.
4 is input to the non-inverting input terminal P ₁ of the differential amplification stage 3.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

In the differential amplifier stage 3, a voltage lower than the power source V _CC by the power source V ₀ is applied to the inverting input terminal P ₂ , and the output signal S5 is directly input to the base of the transistor Q ₂ .

[Procedure Amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

In the differential amplifier circuit 6, the output terminal P ₃ of the configuration of the differential amplifier circuit 5 is not directly connected to the base of the transistor Q ₂ , but the transistor Q is connected via the resistor R _1.
It is connected to the base of ₂ . The midpoint of connection between the resistor R ₁ and the base of the transistor Q ₂ is connected to the ground line GND via the resistor R ₂ . Also in this differential amplifier circuit 6, _VDC = [(R ₁ + R ₂ ) / R is applied to the output terminal P _3.
2 ] × (V _{BE (Q1)} ) + V _{BE (Q2)} is given as the DC voltage component V _DC . Incidentally, the emitter areas of the transistors Q ₁ and Q ₂ are the same as the emitter areas of the transistors of the input differential pair of the differential amplifier stage 3.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

Since the emitter areas of the transistors Q ₁ and Q ₂ are the same as the emitter areas of the transistors of the input differential pair of the differential amplifier stage 3, the transistor Q ₁ and Q _{2 have} the same emitter area.
₁ , Q ₂ and the noise voltage generated in the transistors of the input differential pair of the differential amplification stage 3 are all equal, and the value is V _N , the noise voltage V _{N (Q1, Q2)} is the transistor Q ₁ , Square root of sum of squared noise voltage of Q ₂ , that is,

[Equation 13] Becomes

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

As a result, the number of transistors for increasing the emitter area when lowering the noise level is small, and accordingly, the chip area can be small when forming on an integrated circuit. Further, since the transistors Q ₁ and Q ₂ can use vertical structure transistors, low noise transistors such as a double base can also be used.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

Further, the reproduction equalizer amplifier circuit 8 outputs the output signal S7 of the differential amplifier stage 3 to the feedback circuit composed of the resistors R ₁ , R ₂ , R ₅ , R ₆ and the capacitors C ₁ , C ₂ and the differential input stage 8A.
The DC voltage component different from the DC voltage component of the input signal S1 is applied to the output signal S7 by being fed back to the differential amplification stage 3 via the. That is, the reproduction equalizer amplifier circuit 8
In the configuration of the differential amplifier circuit 6, the feedback resistor R
₁ , a series circuit including a resistor R ₅ and a capacitor C ₁ is connected in parallel with the resistor R ₁ . In addition to the resistor R ₂ , a series circuit including a resistor R ₆ and a capacitor C ₂ is connected in parallel with the resistor R ₂ . Thus the feedback signal S8 output signal S7 frequency component is adjusted is summer as input to the base of the transistor Q _4.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The differential input stage 8A comprises a PNP type transistor Q ₃ and an NPN type transistor Q ₄ whose emitters are commonly connected, and the input signal S1 is applied to the base of the transistor Q ₃ whose collector is connected to the ground line GND. Is entered. The base of the transistor Q ₃ is connected to the ground line GND via the resistor R ₄ . Transistor Q
_A collector ₄ of which the collector is connected to the power supply V _CC via the resistor R ₃ inputs the output signal S 6 of the collector to the non-inverting input terminal P ₁ of the differential amplification stage 3.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

The emitter areas of the transistors Q ₃ and Q ₄ are N times and M times larger than the emitter area of a normal transistor, respectively. As a result, the noises of the transistors Q ₃ and Q ₄ become 1 / √N and 1 / √M, respectively, compared to the noises V _{N (Q1)} ) and V _{N (Q2)} of the transistors Q ₁ and Q ₂ , respectively, and the transistor Q ₃ And the total noise V _{N of} Q _{4 (Q3, Q4)} is

[Formula 19] Becomes Here, the noises generated in the transistors Q ₁ and Q ₂ are equal,

[Equation 20] Then, from the expressions (19) and (20), the following expression,

[Equation 21] Becomes Thus the transistors _{Q 3} and _Q total noise _{V N} at _{4 (Q3, Q4)} is further can be seen to decrease.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

The input of the reproduction equalizer amplifier circuit 8 is the GND reference, but the output has the DC voltage component shifted so that the waveform of the output signal S7 is not collapsed. Set the base-emitter voltage of transistors Q ₃ and Q ₄ to V
_{Assuming BE (Q3)} and V _{BE (Q4)} , the shift amount of the DC voltage component due to the resistors R ₁ and R _{2 is given} by the following equation:

[Equation 22] Becomes

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

Further, in the above-mentioned embodiment, when the collector of the transistor Q ₁ is connected to the ground line GND and the output signal S4 of the collector of the transistor Q ₂ is inputted to the non-inverting input terminal P ₁ of the differential amplification stage 3. However, the present invention is not limited to this, and as shown in FIG. 7, even when the input position of the input signal S1 to the differential input stage 5A and the output position of the output signal to the differential amplification stage are reversed. Applicable.

[Procedure 18]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

That is, in the differential amplifier circuit 9, the collector of the transistor Q ₂ of the differential input stage 5A is the power source V _CC.
And the input signal S1 is input to the base. The collector of the transistor Q ₁ is connected to the ground line GND via the resistor R _3, and the output signal S 9 of the collector is input to the non-inverting input terminal P ₁ of the differential amplification stage 3. In the differential amplifier stage 3, a voltage higher than the power source V ₀ is applied to the inverting input terminal P ₂ as compared with the ground line GND, and the output signal S10 of the output terminal P ₃ is directly fed back to the base of the transistor Q _1. There is.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Delete

[Procedure amendment 20]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Delete

[Procedure correction 21]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure correction 22]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure amendment 23]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure correction 24]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure correction 25]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

[Procedure Amendment 26]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

[Procedure Amendment 27]

[Document name to be corrected] Drawing

[Correction target item name] Figure 9

[Correction method] Change

[Correction content]

[Figure 9]

Claims (11)

[Claims] 1. A differential input section having a transistor differential pair, wherein an input signal is input to one of the transistors of the transistor differential pair, and a current adjusting means for the other transistor of the transistor differential pair. A differential amplifying unit for amplifying an output signal obtained from the other transistor by applying a predetermined current to one of the differential input ends of the differential input unit and amplifying the output signal of the differential amplifying unit. Differential feedback control of the output signal by performing negative feedback to the transistor of FIG. 2. The differential amplifier circuit according to claim 1, wherein the output signal of the differential amplifier section is directly negatively fed back to the other transistor. 3. The differential amplifier circuit according to claim 1, wherein the output signal of the differential amplifier section is negatively fed back to the other transistor via feedback adjusting means for adjusting the output signal. . 4. The differential amplifier circuit according to claim 3, wherein the feedback adjusting means is a resistor. 5. A differential input section having a transistor differential pair, wherein an input signal is input to one transistor of the transistor differential pair, and a current adjusting means for the other transistor of the transistor differential pair. Then, a predetermined current is supplied to the other transistor to input and amplify the output signal obtained from the other transistor to one input end of the differential input end, and the output signal of the differential amplification part is input. Frequency component adjusting means for outputting a component adjusting signal of the output signal, the frequency adjusting component adjusting the frequency component according to the frequency of the frequency component of the output signal, and by negatively feeding back the component adjusting signal to the other transistor. A differential amplifier circuit characterized by negatively controlling the output signal of the differential amplifier section. 6. The differential amplifier circuit according to claim 5, wherein the frequency component adjusting means comprises a resistor and a capacitor. 7. The transistor differential pair comprises an NPN type transistor and a PNP type transistor in which an emitter is commonly connected, and claim 1, 1 or 2, 3 or 4 or 4. The differential amplifier circuit according to claim 5 or 6. 8. The difference according to claim 1, 1 or 2, 3 or 4, 5 or 6 or 7, wherein the current adjusting means is a resistor. Dynamic amplification circuit. 9. The current adjusting means comprises a current source, as claimed in claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7. Differential amplifier circuit. 10. An emitter area of the transistor differential pair and an emitter area of the transistor of the differential amplifier section have a predetermined area ratio, claim 1 or claim 2 or claim 3 or. The differential amplifier circuit according to claim 4, claim 5, claim 6, claim 7, claim 8, or claim 9. 11. The differential input section and / or the differential amplifier section and / or the feedback adjusting means and / or the frequency component adjusting means and / or the current adjusting means are formed on the same semiconductor chip. Claim 1 or Claim 2
Alternatively, the differential amplifier circuit according to claim 3 or claim 4 or claim 5 or claim 6 or claim 7 or claim 8 or claim 9 or claim 10.