JPH07202192A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To form a BF2-implanted polysilicon gate electrode which is never depleted but protected against an impurity punch-through phenomenon. CONSTITUTION:Provided that a polysilicon film for a gate electrode is as thick as 200 to 350nm, BF2 are ion-implanted 2X10<15> to 3X10<15>/cm<2> in doses into the polysilicon film with an implantation energy of 20 to 50KeV, and the polysilicon film is thermally treated at temperature of 800 to 850 deg.C to serve as a gate electrode polysilicon film of a PMOS semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and more particularly to a MOS having a fine pattern called submicron or less or half micron or less.
The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In general, the number of steps in a semiconductor integrated circuit device process tends to increase as miniaturization progresses. Further, in the process of the MOS type semiconductor device, various problems such as a short channel effect and a hot carrier effect occur as miniaturization progresses.

In a CMOS device having an N-channel MOS transistor and a P-channel MOS transistor formed on the same substrate, an N ⁺ polysilicon gate electrode is widely used as a polysilicon gate electrode. This is a silicon gate electrode in which phosphorus glass is deposited on a polysilicon film and phosphorus is diffused into the polysilicon film by heat treatment to reduce the resistance. In such a CMOS device, the N channel side is often a surface channel type and the P channel side is a buried channel type in many cases.

However, when the miniaturization progresses and the process becomes submicron or less or half micron or less, it becomes difficult to suppress the short channel effect in the buried type structure.
The P-channel type is inevitably shifting to the surface type. In that case, a new P ⁺ polysilicon gate electrode for P channel type (reduction of resistance of the polysilicon gate electrode by acceptor injection) or a connection between the N ⁺ polysilicon gate electrode and the P ⁺ polysilicon gate electrode The number of processes is increasing due to the need to adopt a salicide structure.

In adopting the P ⁺ polysilicon gate electrode and the N ⁺ polysilicon gate electrode, the resistance of the gate electrode must generally be reduced by ion implantation of impurities. In this case, there is a problem that the threshold voltage or the flat band voltage is changed or the breakdown voltage is deteriorated due to the penetration of implanted impurities into the substrate channel portion (hereinafter referred to as impurity penetration). Further, when the resistance of the gate electrode is not sufficiently lowered and the gate is depleted, it causes an obstacle to high-speed operation. Impurity penetration and resistance reduction of the gate electrode are in a contradictory relationship.If the ion implantation conditions are set so as to suppress impurity penetration, resistance reduction of the gate electrode is apt to be insufficient, and conversely the gate electrode is sufficiently reduced. Impurity penetration is likely to occur if the ion implantation conditions are set so as to reduce the resistance. Therefore, it is necessary to study in detail the setting of the gate electrode formation conditions such as the polysilicon thickness of the gate electrode, the implantation energy of impurities, the dose amount, and the heat treatment for activation and diffusion of the implanted impurities. Come on.

In a PMOS semiconductor device, B is used as implanted ions.
When F ₂ is used, it has been reported that the fluorine segregated in the oxide film at the time of activation promotes the penetration of boron into the channel portion of the substrate (hereinafter referred to as F enhanced diffusion) (Fluorine Effect). on Boron Diffusion of P ⁺ Gate D
evices; IEDM89, pp.447-450 (1989 IEEE)). Therefore, PMOS FE with P ⁺ polysilicon gate electrode
Forming T is believed to be more difficult than forming NMOSFETs with N ⁺ gate electrodes.

In order to prevent the penetration of impurities and widen the process margin, some methods have been proposed, such as providing a barrier layer on the gate and suppressing accelerated diffusion of boron by fluorine using a nitride film. (Japanese Patent Laid-Open No. 1-173
713, JP-A-1-187971, JP-A-1-220438, and JP-A-2-78229). However, such a proposed method cannot avoid further increase or complication of the manufacturing process, and this leads to new problems such as increase of threshold voltage due to increase of interface state density due to stress. Fluctuations may occur.

In order to suppress the short channel effect, it is not enough to shift the device structure from the buried type to the surface type.
It is also necessary to consider making the junction depth of the source / drain regions shallower to increase the breakdown voltage. In order to suppress an increase in the number of steps associated with miniaturization, there is a demand to simultaneously perform ion implantation into a polysilicon gate electrode and formation of source / drain regions by ion implantation.
The shallow junction in the drain region and the suppression of depletion of the gate electrode are contradictory requirements. If the ion implantation conditions are set so as to make the junction of the source / drain regions shallow, depletion of the gate electrode is likely to occur, and conversely, if the ion implantation conditions are set so that depletion of the gate electrode is sufficiently avoided,
There is a relation that the junction of the drain region becomes deep.

As described above, it is necessary to determine a gate electrode forming condition that suppresses boron penetration and enables formation of a gate electrode without depletion, and further, formation of a gate electrode without depletion and a shallow source / drain region. It is desired to find a process condition that enables bonding at the same time.

[0010]

First object of the present invention is to solve the above, by defining the conditions for forming the BF ₂ implanted polysilicon gate electrode, does not occur with penetration depletion and impurity of the gate electrode BF ₂ implanted poly It is possible to form a silicon gate electrode, improve the quality of the gate electrode, and improve the yield. A second object of the present invention is BF ₂
Implanted polysilicon gate electrode formation and depth 200 nm
A source / drain region having a shallow junction can be formed at the same time by the same ion implantation process, so that the number of processes can be reduced and the manufacturing process can be simplified.

[0011]

In order to form a BF ₂ -implanted polysilicon gate electrode in which depletion of the gate electrode and penetration of impurities do not occur, when the thickness of the polysilicon film for the gate electrode is 200 nm or less, Is an implantation energy of 20 to 50 KeV and a dose of 1 × 10 ^{15 in the} polysilicon film.
BF ₂ is ion-implanted at ˜3 × 10 ¹⁵ / cm ² , and then 8
Heat treatment is performed at 00 to 850 ° C. to form a polysilicon film for a gate electrode of a PMOS semiconductor device.

The thickness of the polysilicon film for the gate electrode is 2
In the case of 00 to 350 nm, the implantation energy into the polysilicon film is 20 to 50 KeV and the dose amount is 2 × 10 ^{15 to} 3 ×.
BF ₂ is ion-implanted at 10 ¹⁵ / cm ² , and then 800-
Heat treatment is performed at 950 ° C. to form a polysilicon film for a gate electrode of the PMOS semiconductor device.

The thickness of the polysilicon film for the gate electrode is 3
When the thickness is 50 nm or more, BF ₂ is ion-implanted into the polysilicon film at an implantation energy of 30 KeV or more and a dose amount of 3 × 10 ¹⁵ / cm ² or more, and then heat-treated at 850 ° C. or more to be used for the gate electrode of the PMOS semiconductor device. It is a polysilicon film.

When lowering the resistance of the gate electrode and forming the source / drain regions at the same time, the film thickness is 200 to 350 nm on the silicon substrate via the gate oxide film.
After depositing the polysilicon film of, and patterning the polysilicon film into the shape of the gate electrode, the implantation energy of 20 to
30 KeV, dose 2 × 10 ^{15 to} 3 × 10 ¹⁵ / cm ²
Then, BF ₂ is simultaneously ion-implanted into the polysilicon film and the silicon substrate, and then heat treatment is performed at 800 to 850 ° C.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of forming an implanted polysilicon gate electrode in a PMOS semiconductor device will be described with reference to FIGS. The sample preparation conditions are as follows. Substrate: P type 20 Ωcm-silicon wafer Impurity density 6 × 10 ¹⁵ / cm ³ Oxide film thickness: 120Å (wet oxide film) Polysilicon film thickness: 2000Å, 3500Å Other parameters are shown in the figure . In the figure, B
F2 refers to BF ₂ , and a display such as 3E15 means 3 × 10 ¹⁵ . Tact is the activation temperature, Tpol
y is the thickness of the polysilicon film, and Tox is the thickness of the gate oxide film.

1 and 2 show film thicknesses of 2000Å and 3500Å
For the polysilicon film of, the dose amount is 3 × 10 ¹⁵ / c
m ² shows the dependence of various amounts of MOS capacitors on the implantation energy when the heat treatment for activation is performed at 850 ° C. for 30 minutes. FIG. 1A shows the storage capacity, FIG.
2B is the result of measuring the substrate impurity concentration (boron), FIG. 2A is the flat band voltage, and FIG. 2B is the threshold voltage with respect to the implantation energy. The broken line in the figure is a theoretical value when neither gate depletion nor impurity penetration occurs. In general, if higher than this broken line, it indicates that there is an impurity B (boron) penetration, and if lower than this broken line, it indicates that gate depletion has occurred.
However, only the presence or absence of gate depletion can be evaluated in the measurement of the storage capacity in FIG. 1A, and only the punch-through can be evaluated in the measurement of the substrate impurity concentration in FIG. 1B.

From the results shown in FIGS. 1 and 2, it can be seen that no boron penetration occurs when the implantation energy is 50 KeV or less. More specifically, even with a polysilicon film having a film thickness of 2000 Å, if the implantation energy is 50 KeV or less, there is no boron penetration during implantation due to channeling or the like, and under moderate activation conditions, there is also no penetration after activation. Absent. It is also found that the gate depletion does not occur when the implantation energy is 20 KeV or more. That is, under an appropriate impurity boron concentration and an appropriate activation condition, the implanted impurity boron diffuses into the polysilicon film almost uniformly, so that gate depletion can be prevented. Figure 3 shows an injection energy of 30K.
3 shows the boron concentration profile in the depth direction in the polysilicon film and the substrate for eV and 50 KeV. The above results obtained from FIGS. 1 and 2 can be confirmed by FIG.

Therefore, under an appropriate activation condition of an activation temperature of 850 ° C. for about 30 minutes, the MOS characteristics do not show a significant dependence on the implantation energy, and gate depletion can be prevented at 20 KeV or more, and 50 KeV or more. The penetration of boron into the substrate can be suppressed below.

4 and 5 show film thicknesses of 2000Å and 3500Å
The activation temperature dependence of various MOS capacitor amounts was shown when BF ₂ ions were implanted into the polysilicon film of No. 1 with implantation energy of 30 KeV and doses of 1 × 10 ¹⁵ / cm ² and 3 × 10 ¹⁵ / cm ² . It is a thing. The activation time was fixed at 30 minutes. FIG. 4A shows the storage capacity, and FIG.
5B is a substrate impurity (boron) concentration, FIG. 5A is a flat band voltage, and FIG. 5B is a threshold voltage.
The results are obtained by measuring the relationship with the activation temperature.

From the results shown in FIGS. 4 and 5, it is understood that when the polysilicon film thickness is 2000 liters and the dose amount is 3 × 10 ¹⁵ / cm ² , a slight boron penetration occurs when the activation temperature reaches 900 ° C. Further, when the activation temperature is 800 ° C., the gate depletion occurs at the polysilicon film thickness of 3500Å regardless of the dose amount, but at the polysilicon film thickness of 2000Å, the dose amount is 1 × 10 ¹⁵ / cm ² and a slight depletion occurs. It is the extent to which the change occurs. The reason for such a rapid change at 800 ° C. indicates that this temperature is the critical point at which the abrupt diffusion of the impurity boron occurs. Therefore, at a temperature of 800 ° C. or higher, it can be said that the implanted impurities diffuse almost uniformly into the polysilicon film and show no dependency on the implantation energy, that is, the implantation energy has almost no influence on the gate formation conditions. Therefore, when the activation temperature is 850 ° C., if the dose amount is 3 × 10 ¹⁵ / cm ² or more, depletion does not occur even if the polysilicon film thickness is 3500Å. Further, in this case, it is considered that the impurity boron is diffused almost uniformly, so that it is 2 when the polysilicon film thickness is 2000 Å.
× 10 ¹⁵ / cm ² (≈3 × 10 ¹⁵ / cm ² × 2000/3
It can be estimated that the depletion of the gate electrode does not occur if it is 500) or more.

FIG. 6 shows the sample immediately after BF ₂ injection, and 750
It shows the profile of the boron concentration in the depth direction after the heat treatment at 30 ° C., 800 ° C., 850 ° C., and 900 ° C. for 30 minutes. The results obtained from FIGS. 4 and 5 can also be confirmed by the boron concentration profile of FIG.

From the above results, the following conclusions can be drawn. In order to make it possible to form a gate electrode having a polysilicon film thickness of 200 nm or less and having no boron penetration through the substrate by BF ₂ ion implantation, the implantation energy is 50
KeV or less, a dose amount of 3 × 10 ¹⁵ / cm ² or less, and subsequent heat treatment (activation) may be performed at 850 ° C. or less.

In order to make it possible to form a gate electrode having a polysilicon film thickness of 200 nm or less by BF ₂ ion implantation, which has a sufficiently low resistance so that gate depletion does not occur, and which is free from boron penetration into the substrate. 20 injection energy
˜50 KeV, dose amount 1 × 10 ¹⁵ ˜3 × 10 ¹⁵ / c
m ² and subsequent heat treatment (activation) 800 to 850
It may be performed at ℃.

In order to make it possible to form a gate electrode having a polysilicon film thickness of 200 nm or more and having a sufficiently low resistance so that gate depletion does not occur by BF ₂ ion implantation,
Implant energy is 20 KeV or more, Dose is 2 × 10
¹⁵ / cm ² or more, and subsequent heat treatment (activation) of 80
It may be performed at 0 ° C or higher.

In order to make it possible to form a gate electrode having a polysilicon film thickness of 350 nm or more and no boron penetration through the substrate by BF ₂ ion implantation, the implantation energy is 50 K.
eV or less, a dose amount of 3 × 10 ¹⁵ / cm ² , and subsequent heat treatment (activation) may be performed at 900 ° C. or less.

By implanting BF ₂ ions, it is possible to form a gate electrode having a polysilicon film thickness of 250 to 350 nm, a sufficiently low resistance so as not to cause gate depletion, and having no B penetration into the substrate. The implantation energy is 20 to 50 KeV and the dose is 2 to 3 × 10 ¹⁵ / cm 2.
² and subsequent heat treatment (activation) at 800-900 ° C
You can do it in.

In order to make it possible to form a gate electrode having a polysilicon film thickness of 350 nm or more and a sufficiently low resistance so that gate depletion does not occur by BF ₂ ion implantation,
Implant energy is 30 KeV or more, Dose is 3 × 10
¹⁵ / cm ² or more, and the subsequent heat treatment (activation) to 85
It may be performed at 0 ° C or higher.

In the PMOSFET, the depth is 200 nm
Conditions were set for the purpose of forming source / drain regions having a shallow junction and forming a polysilicon gate electrode having a film thickness of ₂₀₀ to 350 nm by simultaneous ion implantation of BF ₂ below. Table 1 shows the relationship between the junction depth of the source / drain regions and the implantation conditions obtained by SIMS analysis (secondary ion mass spectrometry). The junction depth of the source / drain region is the depth at which the boron concentration is 1 × 10 ¹⁷ / cm ⁹ .

[0029]

[Table 1]

The heat treatment condition at this time is 850 ° C. for 30 minutes. In order to obtain a junction depth of 200 nm or less, the implantation energy is 20 to 30 KeV and the dose is 1 ×.
It should be 10 ¹⁵ / cm ^{2 to} 3 × 10 ¹⁵ / cm ² .
The heat treatment conditions may be set to 850 ° C. (30 minutes) or less.

As a result, the implantation energy is 20 to 30K.
eV, dose amount 2 × 10 ¹⁵ / cm ^{2 to} 3 × 10 ¹⁵ / c
Adjust the heat treatment (activation) within the range of m ² to 800 to 85
By carrying out at 0 ° C., formation of source / drain regions having a shallow junction with a depth of 200 nm or less and formation of a gate electrode free of gate depletion and boron penetration at a polysilicon film thickness of 200 to 350 nm are performed simultaneously. It becomes possible by injection.

[0032]

In the PMOS semiconductor device having the P ⁺ polysilicon gate electrode manufactured by the method of the present invention, gate depletion and boron penetration into the substrate are suppressed.
There are few fluctuations and variations in threshold voltage and flat band voltage, there is no obstacle to high-speed operation, and reliability such as breakdown voltage is good. In addition, since the junction depth of the source / drain regions can be made shallow, punch-through (short channel effect) resistance is also excellent. Since the source / drain regions can be formed and the resistance of the polysilicon gate can be lowered by simultaneous ion implantation, the manufacturing process can be simplified and the yield can be improved.

[Brief description of drawings]

FIG. 1A is a diagram showing a relationship between a storage capacity of a MOS capacitor and implantation energy, and FIG. 1B is a diagram showing a relation between a substrate impurity concentration (boron) and implantation energy.

FIG. 2A is a diagram showing a relation between a flat band voltage of a MOS capacitor and implantation energy, and FIG. 2B is a diagram showing a relation between threshold voltage and implantation energy.

FIG. 3 is a diagram showing a boron concentration profile in a depth direction in a polysilicon film and a substrate.

FIG. 4A is a diagram showing the relationship between the storage capacitance of a MOS capacitor and the activation temperature, and FIG. 4B is a diagram showing the relationship between the substrate impurity concentration (boron) and the activation temperature.

5A is a diagram showing a relationship between a flat band voltage and an activation temperature of a MOS capacitor, and FIG. 5B is a diagram showing a relationship between a threshold voltage and an activation temperature.

FIG. 6 is a diagram showing activation temperature dependence of a profile of boron concentration in the depth direction.

Claims (4)

[Claims] 1. A polysilicon film having a thickness of 200 nm or less is deposited on a silicon substrate through a gate oxide film, and before or after patterning into a gate electrode shape, an implantation energy of 20 to 50 KeV, Dose 1
BF ₂ is ion-implanted at × 10 ^{15 to} 3 × 10 ¹⁵ / cm ² ,
A method of manufacturing a MOS type semiconductor device, comprising a step of performing a heat treatment at 800 to 850 ° C. thereafter to form a polysilicon film for a gate electrode of a PMOS semiconductor device. 2. A polysilicon film having a thickness of 200 to 350 nm is deposited on a silicon substrate via a gate oxide film,
Before or after patterning into a gate electrode shape, BF ₂ is ion-implanted into the polysilicon film at an implantation energy of 20 to 50 KeV and a dose of 2 × 10 ^{15 to} 3 × 10 ¹⁵ / cm ² , and then at 800 to 950 ° C. Heat treated and PMOS
A method of manufacturing a MOS type semiconductor device, comprising a step of forming a polysilicon film for a gate electrode of a semiconductor device. 3. A polysilicon film having a film thickness of 350 nm or more is deposited on a silicon substrate through a gate oxide film, and before or after patterning into a gate electrode shape, an implantation energy of 30 KeV or more and a dose are applied to the polysilicon film. Quantity 3 x
BF ₂ is ion-implanted at 10 ¹⁵ / cm ² or more, and then 85
A method of manufacturing a MOS semiconductor device, comprising the step of performing a heat treatment at 0 ° C. or higher to form a polysilicon film for a gate electrode of a PMOS semiconductor device. 4. A polysilicon film having a thickness of 200 to 350 nm is deposited on a silicon substrate via a gate oxide film,
After patterning the polysilicon film into a gate electrode shape, implantation energy is 20 to 30 KeV and a dose is 2 × 1.
BF ₂ is simultaneously ion-implanted into the polysilicon film and the silicon substrate at 0 ^{15 to} 3 × 10 ¹⁵ / cm ² , and then 80
A method for manufacturing a MOS type semiconductor device, which comprises the step of simultaneously reducing the resistance of a gate electrode and forming a source / drain region by performing heat treatment at 0 to 850 ° C.