JPH07201745A - Semiconductor wafer and its manufacture - Google Patents

Semiconductor wafer and its manufacture

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Publication number
JPH07201745A
JPH07201745A JP33698493A JP33698493A JPH07201745A JP H07201745 A JPH07201745 A JP H07201745A JP 33698493 A JP33698493 A JP 33698493A JP 33698493 A JP33698493 A JP 33698493A JP H07201745 A JPH07201745 A JP H07201745A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
gan
crystal
type
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33698493A
Other languages
Japanese (ja)
Inventor
Harunori Sakaguchi
春典 坂口
Ryuichi Nakazono
隆一 中園
Tsunehiro Unno
恒弘 海野
Shoji Kuma
彰二 隈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP33698493A priority Critical patent/JPH07201745A/en
Publication of JPH07201745A publication Critical patent/JPH07201745A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To notably improve the purity and crystallizability of GaN epitaxial crystal while manufacturing high concentration p type GaN in as grown state by tilting the deposited surface of (0001) surfaced sapphire substrate. CONSTITUTION:Fine oblique (0001) surfaced sapphire single crystal substrate 4 can be formed by mirror polishing the (0001) surface of tilted by several degrees in (21*1*0) direction or (011*0) direction. At this time, numerous steps 6 exist on the fine oblique (0001) surface 5. Accordingly, the step flow mode deposition of GaN epitaxial crystal 2 using the step end as the cardinal point can be easily attained thereby enabling the crystalline defects to be notably diminished.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、サファイア結晶基板上
にGa、Al、In等の窒化物薄膜結晶を形成した半導
体ウェハ及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer in which a nitride thin film crystal of Ga, Al, In or the like is formed on a sapphire crystal substrate and a method for manufacturing the semiconductor wafer.

【0002】[0002]

【従来の技術】GaN及びその関連化合物によるLE
D、LDやHEMTなどの素子の実現が期待されてい
る。
LE based on GaN and related compounds
It is expected that devices such as D, LD and HEMT will be realized.

【0003】GaN、AlN、InNはサファイア単結
晶のC−面、即ち(0001)面の鏡面に研磨された面
上にエピタキシャル成長されている。
GaN, AlN and InN are epitaxially grown on the C-face of a sapphire single crystal, that is, on the mirror-polished face of the (0001) face.

【0004】エピタキシャル成長は主に気相成長により
行なわれている。特に有機金属気相エピタキシー(MO
VPE)法が多く用いられているが、化学気相エピタキ
シー(VPE)法、分子線エピタキシー(MBE)法
や、これらに光励起やプラズマを用いたものも用いられ
ている。
Epitaxial growth is mainly carried out by vapor phase growth. In particular, metalorganic vapor phase epitaxy (MO
Although the VPE) method is often used, a chemical vapor phase epitaxy (VPE) method, a molecular beam epitaxy (MBE) method, or a method using photoexcitation or plasma for these methods is also used.

【0005】MOVPE法では、前述のサファイア単結
晶基板を水素もしくは窒素雰囲気中で1000℃程度に
加熱し、トリメチルガリウム(TMG)とアンモニア
(NH3 )のガスを流すことにより、GaNのエピタキ
シャル薄膜を成長している。
In the MOVPE method, the sapphire single crystal substrate described above is heated to about 1000 ° C. in a hydrogen or nitrogen atmosphere, and a gas of trimethylgallium (TMG) and ammonia (NH 3 ) is flowed to form an epitaxial thin film of GaN. Growing.

【0006】AlNやInNの場合は、各々TMGの代
りにトリメチルアルミニウム(TMA)やトリメチルイ
ンジウム(TMI)を流して成長する。
In the case of AlN or InN, trimethylaluminum (TMA) or trimethylindium (TMI) is made to flow instead of TMG for growth.

【0007】従来、サファイア基板上に、AlNやGa
Nの100〜1000A程度の薄膜を600℃程度の低
温で成長する。これを1000℃程度に加熱して熱処理
し、その後その温度でGaNを成長することにより、G
aN層の品質が向上することが報告されており、キャリ
ア濃度が4×1016〜2×1017cm-3程度のn型のアン
ドープGaNエピタキシャル結晶が得られている(公知
例1、2)。
Conventionally, AlN or Ga is formed on a sapphire substrate.
A thin film of N of about 100 to 1000 A is grown at a low temperature of about 600 ° C. This is heated to about 1000 ° C. and heat-treated, and then GaN is grown at that temperature to obtain G
It has been reported that the quality of the aN layer is improved, and an n-type undoped GaN epitaxial crystal having a carrier concentration of about 4 × 10 16 to 2 × 10 17 cm −3 has been obtained (known examples 1 and 2). .

【0008】また、亜鉛(Zn)やマグネシウム(M
g)を添加したGaNを電子線で照射処理することや
(公知例1、3)、不活性ガス中でアニールすることに
より(公知例4)1×1017〜6×1018cm-3のキャリ
ア濃度のp型GaNエピタキシャル結晶が得られてい
る。
Further, zinc (Zn) and magnesium (M
g) added GaN is irradiated with an electron beam (known examples 1 and 3) or annealed in an inert gas (known example 4) to obtain 1 × 10 17 to 6 × 10 18 cm −3 A p-type GaN epitaxial crystal having a carrier concentration has been obtained.

【0009】公知例1:「高輝度青色発光のための電子
材料技術、田口編、P51〜58,1991年12月発
行(サイエンスフォーラム社)」 公知例2:S.NAKAMURA:J.J.A.P.V
OL30,No10A,1991,ppL1705〜L
1707 公知例3:S.NAKAMURA:J.J.A.P.V
OL30,No10A,1991,ppL1708〜L
1711 公知例4:S.NAKAMURA:J.J.A.P.v
ol31,(1992)pp1258〜11266 P
art1,No. 5A
Publicly known example 1: "Electronic material technology for high-intensity blue light emission, edited by Taguchi, P51-58, December 1991 (Science Forum)" Publicly known example 2: S.I. NAKAMURA: J. J. A. P. V
OL30, No10A, 1991, ppL1705-L
1707 Known Example 3: S. NAKAMURA: J. J. A. P. V
OL30, No10A, 1991, ppL1708 to L
1711 Known Example 4: S. NAKAMURA: J. J. A. P. v
ol31, (1992) pp1258-11266 P
art1, No. 5A

【0010】[0010]

【発明が解決しようとする課題】前述した従来方法で成
長したGaN結晶は、低温成長バッファ層を介在させて
もまだ純度や結晶性が不十分である。
The GaN crystal grown by the above-mentioned conventional method is still insufficient in purity and crystallinity even if a low temperature growth buffer layer is interposed.

【0011】また、高濃度のn型GaN(ここで高濃度
とはキャリア濃度が1×1018cm-3以上をいう)エピタ
キシャル結晶は、Siドープなどにより容易に得られて
いるのに対して、高濃度のp型GaNエピタキシャル結
晶は電子線照射や成長後の熱処理によって一部実験的に
得られているものの、これらの後処理なしにいわゆるア
ズグロウン(as grown)の状態で容易に得られるまでに
は致っていない。
On the other hand, high-concentration n-type GaN (here, high-concentration means a carrier concentration of 1 × 10 18 cm −3 or more) epitaxial crystal is easily obtained by Si doping or the like. Although high-concentration p-type GaN epitaxial crystals have been experimentally obtained in part by electron beam irradiation and post-growth heat treatment, until they are easily obtained in the so-called as-grown state without these post-treatments. I have not caught up with.

【0012】本発明者等は、従来は基板の成長面につい
ては全く未検討で、傾斜していない(0001)面サフ
ァイア基板のみを用いて専らエピタキシャル成長法の改
良及び成長結晶の後処理により品質の改善を行なってい
た点に着目し、観点を変えて基板の成長面について鋭意
検討したところ、成長面を傾斜させると大幅な品質向上
がはかれるという知見を得た。
The inventors of the present invention have not yet studied the growth surface of the substrate, and the quality of the substrate has been improved only by using the non-tilted (0001) plane sapphire substrate to improve the epitaxial growth method and post-process the grown crystal. Focusing on the point that the improvement was made, and from a different viewpoint, the inventors conducted a diligent examination of the growth surface of the substrate. As a result, they found that tilting the growth surface significantly improves the quality.

【0013】したがって本発明の目的は、成長面を傾斜
することによって、上述した従来技術の問題点を解決
し、純度及び結晶性が大幅に向上し、かつ高濃度p型ド
ーピングが可能となるGaN及び関連化合物(AlN、
InN及びこれらとGaNの混晶)の半導体ウェハ及び
その製造方法を提供することにある。
Therefore, the object of the present invention is to solve the above-mentioned problems of the prior art by tilting the growth surface, to greatly improve the purity and crystallinity, and to enable high-concentration p-type doping. And related compounds (AlN,
It is to provide a semiconductor wafer of InN and a mixed crystal of these and GaN) and a method for manufacturing the same.

【0014】[0014]

【課題を解決するための手段】本発明は、GaN等をエ
ピタキシャル成長させる基板としてサファイア単結晶基
板の(0001)面を所定晶軸方向に傾けて鏡面研磨し
た、いわゆる微傾斜面の基板を用いている。この微傾斜
(0001)面上にGaN等をエピタキシャル成長させ
ることにより高品質な高濃度p型GaN及び関連化合物
のエピタキシャル結晶を実現したものである。
The present invention uses, as a substrate for epitaxially growing GaN or the like, a so-called slightly inclined surface substrate obtained by mirror-polishing a (0001) surface of a sapphire single crystal substrate with a predetermined crystal axis tilted. There is. By epitaxially growing GaN or the like on this slightly inclined (0001) plane, a high-quality epitaxial crystal of high-concentration p-type GaN and related compounds is realized.

【0015】すなわち、本発明の半導体ウェハは、(0
001)面を<21* 1* 0>方向もしくは<011*
0>方向に微傾斜した鏡面を有するサファイア結晶基板
の微傾斜(0001)面上に、窒化ガリウム(Ga
N)、窒化アルミニウム(AlN)、窒化インジウム
(InN)、またはこれらの混晶のp型、n型、または
i型薄膜の単層もしくは多層の結晶が積層されているも
のである。
That is, the semiconductor wafer of the present invention is (0
001) plane in <21 * 1 * 0> direction or <011 *
On the slightly inclined (0001) plane of the sapphire crystal substrate having a mirror surface slightly inclined in the 0> direction, gallium nitride (Ga
N), aluminum nitride (AlN), indium nitride (InN), or a mixed crystal of p-type, n-type, or i-type thin film in a single-layer or multi-layer structure.

【0016】また本発明の半導体ウェハは、(000
1)面を<21* 1* 0>方向もしくは<011* 0>
方向に微傾斜した鏡面を有するサファイア結晶基板の微
傾斜(0001)面上に、GaNバッファ層、p型Ga
N層、n型GaN層が順次積層して、青色発光ダイオー
ド用ウェハとしたものである。
The semiconductor wafer of the present invention is (000
1) Face in <21 * 1 * 0> direction or <011 * 0>
On the sapphire (0001) plane of the sapphire crystal substrate having a mirror surface slightly inclined in the direction, a GaN buffer layer and a p-type Ga
A N-type layer and an n-type GaN layer are sequentially laminated to form a blue light emitting diode wafer.

【0017】また、本発明の半導体ウェハの製造方法
は、サファイア単結晶基板の(0001)面を微傾斜し
たまま鏡面研磨し、その上にウェハの単層もしくは多層
構造のエピタキシャル層を成長するようにしたものであ
る。
Further, in the method for manufacturing a semiconductor wafer of the present invention, the (0001) plane of the sapphire single crystal substrate is mirror-polished with a slight inclination, and a single layer or a multi-layered epitaxial layer of the wafer is grown thereon. It is the one.

【0018】また、本発明の半導体ウェハの製造方法
は、サファイア結晶基板上にバッファ層を成長し、その
上にp型GaN層、n型GaN層を成長してpn構造の
GaNエピタキシャル結晶を気相成長する工程を有する
半導体ウェハの製造方法において、サファイア結晶基板
に、(0001)面を<21* 1* 0>方向もしくは<
011* 0>方向に微傾斜した面を鏡面とするサファイ
ア結晶基板を用いたものである。
Further, according to the method of manufacturing a semiconductor wafer of the present invention, a buffer layer is grown on a sapphire crystal substrate, a p-type GaN layer and an n-type GaN layer are grown thereon, and a pn-structure GaN epitaxial crystal is grown. In a method of manufacturing a semiconductor wafer having a phase growth step, a (0001) plane is formed on a sapphire crystal substrate in a <21 * 1 * 0> direction or in a <21 * 1 * 0> direction.
This is a sapphire crystal substrate having a mirror surface of a surface slightly inclined in the 011 * 0> direction.

【0019】これら半導体ウェハ、及び半導体ウェハの
製造方法において、微傾斜角度は2°〜10°のいずれ
かであることが好ましい。
In these semiconductor wafers and the semiconductor wafer manufacturing method, it is preferable that the slight inclination angle is 2 ° to 10 °.

【0020】ものである。It is something.

【0021】[0021]

【作用】従来の(0001)面サファイア基板上に成長
したGaNエピタキシャル結晶には、窒素の抜けた空孔
や他の結晶欠陥が多く存在し、これがアンドープGaN
の純度が良くない原因や、p型GaNが容易に得られな
い原因の一つとなっていると考えられる。
In the conventional GaN epitaxial crystal grown on the (0001) plane sapphire substrate, there are many vacancies from which nitrogen is removed and other crystal defects, which are undoped GaN.
It is considered that this is one of the reasons why the purity is poor and that p-type GaN cannot be easily obtained.

【0022】これらの結晶欠陥は結晶のエピタキシャル
成長中に発生すると考えられる。すなわち、GaN/サ
ファイア系結晶ではサファイア基板とGaN結晶の格子
定数等の物性がかなり異なるいわゆるヘテロエピタキシ
ャル成長のため、図3に示すように、(0001)面サ
ファイア単結晶基板1上の(0001)面3に成長する
GaNエピタキシャル結晶2は島状の三次元成長をしや
すく、これが前記の欠陥を発生しやすくしていると考え
られる。
It is considered that these crystal defects occur during the epitaxial growth of crystals. That is, in the GaN / sapphire crystal, since the so-called heteroepitaxial growth in which the sapphire substrate and the GaN crystal have considerably different physical properties such as lattice constants, as shown in FIG. 3, the (0001) plane sapphire single crystal substrate 1 has a (0001) plane. It is considered that the GaN epitaxial crystal 2 that grows in No. 3 easily undergoes island-shaped three-dimensional growth, which easily causes the above defects.

【0023】これに対して、GaAs基板上のGaAs
エピタキシャル成長のような同種基板上に成長するホモ
エピタキシャルでは、エピタキシャル成長モードが二次
元成長となるため、結晶欠陥が非常に低減される。
On the other hand, GaAs on the GaAs substrate
In homoepitaxial growth, such as epitaxial growth, on the same type of substrate, the epitaxial growth mode is two-dimensional growth, so crystal defects are greatly reduced.

【0024】ところで、前述した低温成長AlNバッフ
ァや低温成長GaNバッファはこの二次元成長を促進す
る効果があると考えられるがまだ不十分である。二次元
成長を実現するためには成長モードをステップフローモ
ードにすることが有効である。
By the way, the above-mentioned low temperature grown AlN buffer and low temperature grown GaN buffer are considered to have the effect of promoting this two-dimensional growth, but they are still insufficient. In order to realize the two-dimensional growth, it is effective to set the growth mode to the step flow mode.

【0025】この点で、図1に示すように、本発明の微
傾斜(0001)面サファイア単結晶基板4を用いる
と、微傾斜(0001)面5に多くのステップ6が存在
するため、このステップ端を基点としたGaNエピタキ
シャル結晶2のステップフローモード成長が容易に実現
する。
At this point, as shown in FIG. 1, when the slightly inclined (0001) plane sapphire single crystal substrate 4 of the present invention is used, many steps 6 are present in the slightly inclined (0001) plane 5, so that Step flow mode growth of the GaN epitaxial crystal 2 based on the step edge is easily realized.

【0026】したがって、二次元成長による良質なGa
N及び関連化合物結晶を得ることができる。また、高濃
度のp型GaNエピタキシャル結晶を電子線照射や成長
後の熱処理などの後処理なしにアズグロウンの状態で容
易に得られる一方、n型GaNエピタキシャル結晶の濃
度もより高めることができる。
Therefore, good quality Ga due to two-dimensional growth is obtained.
Crystals of N and related compounds can be obtained. Further, a high-concentration p-type GaN epitaxial crystal can be easily obtained in an as-grown state without post-treatment such as electron beam irradiation or heat treatment after growth, while the concentration of the n-type GaN epitaxial crystal can be further increased.

【0027】[0027]

【実施例】以下、本発明の半導体ウェハを、サファイア
単結晶基板上の微傾斜面にAl、Ga等の窒化物薄膜結
晶を気相形成した実施例について説明する。
EXAMPLES Examples of the semiconductor wafer of the present invention in which a nitride thin film crystal of Al, Ga or the like is vapor-phase formed on a sapphire single crystal substrate on a slightly inclined surface will be described below.

【0028】<実施例1> (0001)面を<21* 1* 0>方向に2°傾けて鏡
面研磨したサファイア単結晶基板をMOVPE装置の反
応炉中のグラファイトサセプタ上にセットし、高純度水
素を十分流して炉内をパージした。
<Example 1> A sapphire single crystal substrate mirror-polished with a (0001) plane tilted in the <21 * 1 * 0> direction by 2 ° was set on a graphite susceptor in a reaction furnace of a MOVPE apparatus to obtain high purity. The inside of the furnace was purged by sufficiently flowing hydrogen.

【0029】次に、水素ガスを炉内に流しながらサセプ
タを加熱して基板を1000℃以上に加熱し、10分以
上保持した。その後、基板温度を600℃にし、TMA
とNH3 を炉内に流していわゆる低温成長のAlNバッ
ファ層を50nm成長した。
Next, the substrate was heated to 1000 ° C. or higher by heating the susceptor while flowing hydrogen gas into the furnace, and held for 10 minutes or longer. After that, the substrate temperature is set to 600 ° C. and TMA
And NH 3 were flown into the furnace to grow a so-called low temperature grown AlN buffer layer with a thickness of 50 nm.

【0030】そして、TMAの炉内への供給を止め、水
素とNH3 を流したまま基板を1030℃に加熱し、そ
の後TMGを炉内に流してGaNを5μm 成長した。こ
のアンドープGaNエピタキシャル結晶の電気特性をホ
ール効果法により測定したところ、n型でキャリア濃度
が5×1015cm-3程度であり、従来に比べ大幅な純度向
上が認められた。
Then, the supply of TMA to the furnace was stopped, the substrate was heated to 1030 ° C. with hydrogen and NH 3 flowing, and then TMG was flown into the furnace to grow GaN to a thickness of 5 μm. When the electrical characteristics of this undoped GaN epitaxial crystal were measured by the Hall effect method, it was found to be n-type and the carrier concentration was about 5 × 10 15 cm −3, showing a significant improvement in purity as compared with the conventional one.

【0031】なお、成長時の水素、NH3 、TMG、T
MAの流量は各々、10l/min、5l/min、3
cc/min、0.8cc/minである。
During the growth, hydrogen, NH 3 , TMG, T
MA flow rate is 10 l / min, 5 l / min, 3
cc / min and 0.8 cc / min.

【0032】<実施例2> (0001)面を<21* 1* 0>方向へ5°及び10
°傾けたサファイア基板を用いて実施例1と同様なエピ
タキシャル成長を評価を行なったところ、同様なキャリ
ア濃度のアンドープGaN結晶が得られた。キャリア濃
度は傾斜角度が大きいほど小さくなる傾向が見られた。
<Embodiment 2> The (0001) plane is oriented in the <21 * 1 * 0> direction by 5 ° and 10 °.
When the same epitaxial growth as in Example 1 was evaluated using a tilted sapphire substrate, an undoped GaN crystal with a similar carrier concentration was obtained. The carrier concentration tended to decrease as the tilt angle increased.

【0033】<実施例3> (0001)面を<011* 0>方向へ2°、5°10
°と傾けたサファイア基板を用いて実施例1と同様なエ
ピタキシャル成長を行なったところ実施例1、2と同様
な結果が得られた。
<Embodiment 3> The (0001) plane is oriented in the <011 * 0> direction by 2 °, 5 ° 10
When the same epitaxial growth as in Example 1 was performed using a sapphire substrate tilted at an angle of 0, the same results as in Examples 1 and 2 were obtained.

【0034】<実施例4>実施例1で用いたAlNバッ
ファ層の代りにGaNバッファ層を600℃で20nm
成長し、その他の条件は実施例1と全く同じ条件でアン
ドープGaN結晶を成長した。アンドープGaNエピタ
キシャル結晶のキャリア濃度はn型で1×1015cm-3
度であり、実施例1より高純度の結晶が得られた。
Example 4 A GaN buffer layer was used instead of the AlN buffer layer used in Example 1 at 600 ° C. for 20 nm.
An undoped GaN crystal was grown under the same conditions as in Example 1 except for the growth. The carrier concentration of the undoped GaN epitaxial crystal was about 1 × 10 15 cm −3 in n-type, and a crystal of higher purity than that of Example 1 was obtained.

【0035】<実施例5>本実施例は、図2に示すLE
D用pn接合GaNエピタキシャル結晶ウェハの例であ
る。(0001)面を<21* 1* 0>方向に2°傾け
た面を鏡面とする微傾斜(0001)面サファイア単結
晶基板4を用いてpn構造のGaNエピタキシャル結晶
7、8、9をMOVPE法により成長した。
<Embodiment 5> This embodiment is an LE shown in FIG.
It is an example of a pn junction GaN epitaxial crystal wafer for D. MOVPE was performed on GaN epitaxial crystals 7, 8 and 9 having a pn structure by using a slightly inclined (0001) plane sapphire single crystal substrate 4 having a plane obtained by tilting the (0001) plane by 2 ° in the <21 * 1 * 0> direction. Grew up by law.

【0036】実施例1と同様に基板4を1050℃で水
素ガスを流しながら加熱し、表面清浄化を行なった。次
に500℃に基板温度を下げて水素とTMGとNH3
流し低温度成長GaNバッファ層7を25nm成長し
た。次に水素とNH3 を流しながら基板温度を1030
℃に上げ水素とTMGとNH3 とビスシクロペンタジエ
チルマグネシウム(CP2 Mg)を流してp型GaN層
8を2μm 成長した。
In the same manner as in Example 1, the substrate 4 was heated at 1050 ° C. while flowing hydrogen gas to clean the surface. Next, the substrate temperature was lowered to 500 ° C. and hydrogen, TMG and NH 3 were flown to grow the low temperature growth GaN buffer layer 7 to 25 nm. Next, while flowing hydrogen and NH 3 , the substrate temperature is adjusted to 1030
The temperature was raised to ℃ and hydrogen, TMG, NH 3 and biscyclopentadiethyl magnesium (CP 2 Mg) were flown to grow the p-type GaN layer 8 to 2 μm.

【0037】引き続き水素とTMGとNH3 とジシラン
(Si2 6 )を流し、n型GaN層9を2μm 成長し
た。その後NH3 と水素を流しながら結晶を冷却し60
0℃〜800℃になった時点で水素とNH3 を流すのを
停止し、代りに高純度N2 ガスを流して室温まで冷却し
た。
Subsequently, hydrogen, TMG, NH 3 and disilane (Si 2 H 6 ) were flown to grow the n-type GaN layer 9 to a thickness of 2 μm. Then, cool the crystal while flowing NH 3 and hydrogen 60
When the temperature reached 0 ° C. to 800 ° C., the flow of hydrogen and NH 3 was stopped, and instead, high-purity N 2 gas was flowed to cool to room temperature.

【0038】ここで、水素、NH3 、TMG、CP2
g、Si2 6 、N2 の各々の流量は、20l/mi
n、5l/min、1cc/min、2cc/min、
1×10-4cc/min、20l/minである。
Here, hydrogen, NH 3 , TMG, CP 2 M
The flow rate of g, Si 2 H 6 , and N 2 is 20 l / mi.
n, 5 l / min, 1 cc / min, 2 cc / min,
1 × 10 −4 cc / min and 20 l / min.

【0039】成長した結晶のキャリア濃度はn型GaN
層9がジシランによるSiドープで5×1019cm-3、p
型GaN層8がアズグロウン状態で1×1019cm-3であ
り、ともに1×1018cm-3を超えるはるかに高い高キャ
リア濃度のp型GaN層、n型GaN層が得られた。
The carrier concentration of the grown crystal is n-type GaN.
Layer 9 is Si-doped with disilane, 5 × 10 19 cm −3 , p
The type GaN layer 8 was 1 × 10 19 cm −3 in the as-grown state, and both p-type GaN layer and n-type GaN layer having a much higher carrier concentration exceeding 1 × 10 18 cm −3 were obtained.

【0040】<実施例6>実施例5の成長、評価を、<
21* 1* 0>方向へ5°、10°と各々傾けた基板や
<011* 0>方向へ2°、5°、10°と傾けた基板
についても行なったところ、実施例5と同様な結果を得
た。
<Example 6> The growth and evaluation of Example 5 are described below.
The same results as in Example 5 were obtained when the substrate was tilted 5 ° and 10 ° in the 21 * 1 * 0> direction and the substrate was tilted 2 °, 5 ° and 10 ° in the <011 * 0> direction. I got the result.

【0041】<他の実施例>なお、微傾斜(0001)
面サファイア単結晶基板上に成長できる結晶としては、
AlNやGaNの他にInN及びこれらの混晶やこれら
を含む多層構造エピタキシャル結晶がある。
<Other Embodiments> Incidentally, a slight inclination (0001)
As a crystal that can be grown on a plane sapphire single crystal substrate,
In addition to AlN and GaN, there are InN, a mixed crystal of these, and a multilayer structure epitaxial crystal containing these.

【0042】また、エピタキシャル成長法は、MOVP
Eの他にMBEやプラズマCVDなど他の気相成長法を
用いることもできる。
The epitaxial growth method uses MOVP.
Other than E, other vapor phase growth methods such as MBE and plasma CVD can be used.

【0043】さらに、サファイア基板に代えてシリコン
カーバイド(SiC)やシリコン基板などを用いたGa
N及び関連化合物のエピタキシャル成長においても本発
明の微傾斜面上成長は可能であり、エピタキシャル結晶
の品質を向上させることができる。
Further, in place of the sapphire substrate, Ga using silicon carbide (SiC) or a silicon substrate is used.
Even in the epitaxial growth of N and related compounds, the growth on the slightly inclined surface of the present invention is possible, and the quality of the epitaxial crystal can be improved.

【0044】[0044]

【発明の効果】【The invention's effect】

(1) 請求項1に記載の半導体ウェハによれば、結晶欠陥
の少ない高品質なGaN及び関連化合物エピタキシャル
結晶を実現できる。
(1) According to the semiconductor wafer of the first aspect, it is possible to realize a high-quality GaN and related compound epitaxial crystal with few crystal defects.

【0045】(2) 請求項2に記載の半導体ウェハによれ
ば、より高輝度の青色発光ダイオードを作ることができ
る。
(2) According to the semiconductor wafer of the second aspect, a blue light emitting diode with higher brightness can be manufactured.

【0046】(3) 請求項3に記載の半導体ウェハの製造
方法によれば、サファイア基板上に結晶欠陥の少ない高
品質な半導体エピタキシャル層を形成できる。
(3) According to the semiconductor wafer manufacturing method of the third aspect, a high-quality semiconductor epitaxial layer with few crystal defects can be formed on the sapphire substrate.

【0047】(4) 請求項4に記載の半導体ウェハの製造
方法によれば、アズグロウンの状態で高濃度のp型Ga
Nを容易に実現できる。
(4) According to the method of manufacturing a semiconductor wafer of claim 4, p-type Ga having a high concentration in an as-grown state is obtained.
N can be easily realized.

【0048】(5) 請求項5に記載の発明によれば、微傾
斜角を最適な値に規定したので、結晶欠陥のより少ない
高品質なGaN及び関連化合物エピタキシャル結晶を実
現できる。
(5) According to the invention described in claim 5, since the fine tilt angle is defined to be an optimum value, a high-quality GaN and related compound epitaxial crystal with fewer crystal defects can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体ウェハの実施例を説明するため
の微傾斜(0001)面サファイア基板上のGaNエピ
タキシャル結晶の二次元成長モード(ステップフローモ
ード)を示す基板成長断面模式図。
FIG. 1 is a schematic substrate growth cross-sectional view showing a two-dimensional growth mode (step flow mode) of a GaN epitaxial crystal on a slightly inclined (0001) plane sapphire substrate for explaining an embodiment of a semiconductor wafer of the present invention.

【図2】本発明の半導体ウェハの実施例を説明するため
のLED用pn接合GaNエピタキシャル結晶ウェハの
一例の断面図。
FIG. 2 is a cross-sectional view of an example of a pn junction GaN epitaxial crystal wafer for LEDs for explaining an example of a semiconductor wafer of the present invention.

【図3】従来の(0001)面サファイア基板上のGa
Nエピタキシャル結晶の三次元成長モードを示す基板成
長断面模式図。
FIG. 3 shows Ga on a conventional (0001) plane sapphire substrate.
FIG. 3 is a schematic diagram of a substrate growth cross section showing a three-dimensional growth mode of an N epitaxial crystal.

【符号の説明】[Explanation of symbols]

2 GaNエピタキシャル結晶 4 微傾斜(0001)面サファイア単結晶基板 5 微傾斜(0001)面 6 ステップ 7 低温成長GaNバッファ層 8 p型GaN層 9 n型GaN層 2 GaN epitaxial crystal 4 Slightly (0001) plane Sapphire single crystal substrate 5 Slightly (0001) plane 6 Step 7 Low temperature growth GaN buffer layer 8 p-type GaN layer 9 n-type GaN layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 隈 彰二 茨城県土浦市木田余町3550番地 日立電線 株式会社アドバンスリサーチセンタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoji Kuma 3550, Kidayomachi, Tsuchiura City, Ibaraki Prefecture Hitachi Cable Ltd. Advanced Research Center

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】(0001)面を<21* 1* 0>(以
下、1* は上にバーの付いた1を意味する。)方向もし
くは<011* 0>方向に微傾斜した鏡面を有するサフ
ァイア結晶基板の微傾斜(0001)面上に、窒化ガリ
ウム(GaN)、窒化アルミニウム(AlN)、窒化イ
ンジウム(InN)、またはこれらの混晶のp型、n
型、またはi型薄膜の単層もしくは多層の結晶が積層さ
れている半導体ウェハ。
1. A mirror surface having a (0001) plane slightly inclined in the <21 * 1 * 0> (hereinafter, 1 * means 1 with a bar above) or <011 * 0> direction. Gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or a mixed crystal of p-type and n-type on the sapphire crystal substrate on the slightly inclined (0001) plane.
Type or i-type thin film single or multi-layered semiconductor wafer is laminated.
【請求項2】(0001)面を<21* 1* 0>方向も
しくは<011* 0>方向に微傾斜した鏡面を有するサ
ファイア結晶基板の微傾斜(0001)面上に、GaN
バッファ層、p型GaN層、n型GaN層が積層されて
いる半導体ウェハ。
2. A sapphire crystal substrate having a mirror surface in which the (0001) plane is slightly tilted in the <21 * 1 * 0> direction or the <011 * 0> direction is provided with GaN.
A semiconductor wafer in which a buffer layer, a p-type GaN layer, and an n-type GaN layer are stacked.
【請求項3】サファイア結晶基板の(0001)面を微
傾斜したまま鏡面研磨し、その上に半導体の単層もしく
は多層構造のエピタキシャル層を成長することを特徴と
する半導体ウェハの製造方法。
3. A method for manufacturing a semiconductor wafer, which comprises mirror-polishing a (0001) plane of a sapphire crystal substrate while slightly tilting it, and growing an epitaxial layer having a semiconductor single layer or a multi-layer structure thereon.
【請求項4】サファイア結晶基板上にバッファ層を成長
し、その上にp型GaN層、n型GaN層を成長してp
n構造のGaNエピタキシャル結晶を気相成長する工程
を有する半導体ウェハの製造方法において、 上記サファイア結晶基板に、(0001)面を<21*
1* 0>方向もしくは<011* 0>方向に微傾斜した
面を鏡面とするサファイア結晶基板を用いたことを特徴
とする半導体ウェハの製造方法。
4. A buffer layer is grown on a sapphire crystal substrate, and a p-type GaN layer and an n-type GaN layer are grown thereon to form a p-type GaN layer.
A method of manufacturing a semiconductor wafer having a step of vapor-phase growing an n-structure GaN epitaxial crystal, wherein a (0001) plane is <21 * on the sapphire crystal substrate.
A method of manufacturing a semiconductor wafer, which uses a sapphire crystal substrate having a mirror surface of a surface slightly inclined in the 1 * 0> direction or the <011 * 0> direction.
【請求項5】上記微傾斜角度が2°〜10°のいずれか
である請求項1もしくは2に記載の半導体ウェハ、また
は請求項3もしくは4に記載の半導体ウェハの製造方
法。
5. The semiconductor wafer according to claim 1 or 2, or the semiconductor wafer manufacturing method according to claim 3 or 4, wherein the fine tilt angle is in the range of 2 ° to 10 °.
JP33698493A 1993-12-28 1993-12-28 Semiconductor wafer and its manufacture Pending JPH07201745A (en)

Priority Applications (1)

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Publication Number Publication Date
JPH07201745A true JPH07201745A (en) 1995-08-04

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