JPH07201651A - Multilayer capacitor - Google Patents

Abstract

PURPOSE:To obtain a high capacity low ESL multilayer capacitor which can be packaged easily by forming outer electrodes at parts on the opposite sides of a laminate comprising dielectric plates and inner electrodes, connecting the inner electrodes and the outer electrodes through a plurality of columnar connecting members, and disposing the connecting members at such positions as the electromagnetic field is offset by the currents flowing through the inner electrodes. CONSTITUTION:Outer electrodes 16 and 56 are formed at least parts on the opposite sides of a laminate comprising dielectric plates 11-51 and inner electrodes 12-42. The inner electrodes 12, 32 and the outer electrodes 16 having an identical polarity are interconnected through a plurality of columnar terminals 13 while the inner electrodes 22, 42 and the outer electrodes 56 having identical polarity are interconnected through a plurality of columnar terminals 14. The columnar terminals 13, 14 are disposed at such positions as the electromagnetic fields produced by the currents flowing through the inner electrodes 12-42 are offset each other. Since the current flowing through the inner electrodes can be dispersed in all directions, the current path can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a multilayer capacitor,
More specifically, the present invention relates to a low-inductance multilayer capacitor that can effectively remove switching noise of a logic circuit in a high frequency region.

[0002]

2. Description of the Related Art With the recent increase in capacity, speed and density of electronic circuits, there is a demand for higher capacity and higher frequency of capacitors. A monolithic ceramic capacitor is one of the capacitors that can meet such requirements. Among them, the chip-type monolithic ceramic capacitor of the type shown in FIG. 7 is widely used because it can realize a large capacity and can be easily mounted on a package or the like.

Reference numeral 71 in the drawing denotes a dielectric, and between the laminated dielectrics 71, an internal electrode 72 formed on substantially the entire surface excluding the left end and an internal electrode 73 formed on almost the entire surface excluding the right end. Are formed on alternate layers and these dielectrics 7
1, the internal electrode 72 and the internal electrode 73 form a laminated body 74. In addition, an external electrode 75 to which one end of the internal electrode 72 is connected and an external electrode 76 to which one end of the internal electrode 73 is connected are formed at both ends of the laminated body 74.
The multilayer chip capacitor 70 is configured by including the multilayer body 74 and the external electrodes 75 and 76.

In the chip type monolithic ceramic capacitor 70 thus constructed, the internal electrode 72 and the internal electrode 73 are formed.
Capacitance is formed on the laminated surfaces facing each other, and the sum of the respective capacitance values becomes the total capacitance value of the chip type monolithic ceramic capacitor 70, and a large capacitance can be obtained even with a small size.

Generally, a capacitor is ideally a capacitive element, but in reality, it has a dielectric loss of a dielectric material and a resistance and an inductance of an electrode.
It is represented by the equivalent circuit as shown in, and its behavior greatly changes depending on the frequency used. FIG. 9 shows an example
Capacitance C = 1nF, Equivalent series resistance ESR (Equivalent Ser
ies Resistance) = 0.1Ω, impedance of capacitor with equivalent series inductance ESL = 1 nH | Z
It shows the frequency characteristic of |. Here, the solid line represents the actual frequency characteristic, and the dotted line represents the ideal frequency characteristic of a capacitor having no dielectric loss or electrode resistance, that is, the inductance (ω _L ) component and capacitance component (1 / ωc) of the capacitor.
The frequency characteristics of are shown. As is clear from FIG. 9, the impedance of an actual capacitor starts to shift from around 40 MHz, which indicates that the apparent capacitance is changing. Resonance is generated at 160 MHz, and the inductor behaves as an inductor at frequencies higher than that. A typical application of the capacitor is a bypass capacitor that cuts the noise of the circuit. With the above-mentioned capacitor, the impedance becomes high when the noise frequency becomes 300 MHz or more, so that the noise in the high frequency region can be effectively eliminated. There was a problem that it became difficult to remove.

In order to solve such a problem, it is necessary to increase the self-resonant frequency f _O of the capacitor. In general,
The capacitor's f _O is

[0007]

[Equation 1]

It is represented by Therefore, to increase f _O , E
SL or C must be small. But,
As described above, C tends to increase with the increase in the capacity of the circuit in recent years, and C cannot be reduced, and ESL
It is important to reduce

In the chip type monolithic ceramic capacitor 70, as shown in FIG. 10, current flows from one end of the external electrode 76 in the same direction in all the internal electrodes 72, 73 sandwiching the dielectric 71, and the electromagnetic waves generated by the current flow. The fields are not offset, and the ESL value is approximately the following formula,

[0010]

[Equation 2]

It is represented by As a result, the mutual inductance has a positive and large value, and the ESL value cannot be reduced. For example, if the external electrode 76 width a = 0.5 mm, the capacitor 70 height c = 0.5 mm, the capacitor 70 length d = 1 mm, and μ ₀ : permeability, ESL is about 1.3.
It becomes a large value of nH.

The switching noise is noise generated by a current (charging / discharging current) flowing through the power supply line of the system due to the switching of the logic circuit, and is proportional to the inductance of the current path. At this time, the capacitor acts as a supply source of charging / discharging current. At present, switching noise in this logic circuit has become a serious problem with the increase in speed of electronic circuits, and in order to suppress the switching noise, it is desired to increase the capacity and the inductance of the capacitor.

In the chip type monolithic ceramic capacitor 70 whose capacity has already been increased, in order to further suppress the switching noise, the ESL of the capacitor itself should be reduced, and between the LSI chip and the like when mounted and the capacitor. It is important to minimize the inductance of. Therefore, as a method of reducing the inductance between the LSI chip and the chip type multilayer ceramic capacitor 70, a method of providing a large number of short current paths between them has been considered.

Generally, in a high-speed and large-capacity LSI, 50
When 100 to 100 power supply lines are provided and the chip type monolithic ceramic capacitor 70 is mounted on a package in which such an LSI is mounted (see FIG. 11), LS
The I chip 57 is tightly connected to the ground layer 83 of the package 81 with a conductive material, and the ground layer pads (not shown) of the LSI chip 57 include wires 82, ground pads 84, via holes 85, ground layers 83, and via holes 86. The external electrodes 75 are connected to the chip type monolithic ceramic capacitor 70 via the capacitor connection pads 75a. Therefore, LS
There are many current paths from the I-chip 57 to the ground layer 83, and the inductance is small. However, since the external electrode 75 of the chip type monolithic ceramic capacitor 70 is small and a large number of the current paths must be integrated and then connected, the number of via holes 86 is usually one, and as a result, Has a problem that the inductance between the LSI chip 57 and the chip type multilayer ceramic capacitor 70 cannot be reduced. Also in the power supply line, although a large number of current paths are secured up to the wire 87, the power supply pad 88, the via hole 89, and the power supply layer 90, the number of via holes 91 is one, and the same problem as in the case of the ground line occurs. there were.

On the other hand, in order to reduce the ESL of the capacitor itself, a chip type multilayer capacitor has been proposed in which the internal electrodes are arranged so that the directions of the currents flowing through the vertically adjacent internal electrodes are substantially opposite to each other. (Tokuhei 4-7
No. 0764).

[0016]

[Problems to be Solved by the Invention]
In the chip type multilayer capacitor described in Japanese Patent Publication No. 0764, the internal electrodes are configured such that the directions of the currents flowing through the internal electrodes are substantially opposite to each other, so that the electromagnetic field due to the currents is canceled and the capacitors themselves. ES of
Although L is reduced, the area of the external electrode is small due to its structure, and therefore, when mounted on a package or the like, an LSI
Even if a large number of current paths are prepared on the chip side, it is still necessary to aggregate them and connect them to the chip type multilayer capacitor, and it is difficult to reduce the inductance between the LSI chip and the capacitor. There was a problem.

The present invention has been made in view of the above problems, and has a large capacity and a low ESL, is easy to be mounted on a package, etc., and has a small inductance with an LSI chip, etc. It is intended to provide a multilayer capacitor.

[0018]

Means for Solving the Problems In order to achieve the above-mentioned problems, a multilayer capacitor according to the present invention is a multilayer capacitor in which a plurality of dielectric layers and internal electrodes are alternately stacked. External electrodes are formed on at least a part of both main surfaces of the front and back of the laminated body,
The internal electrodes and the external electrodes having the same polarity are connected to each other by a plurality of columnar connecting members, and the columnar connecting members are arranged at locations where electromagnetic fields due to currents flowing through the internal electrodes cancel each other out. Is characterized by.

[0019]

In a multilayer capacitor, normally, the external electrodes are connected to the internal electrodes of every other layer so that the internal electrodes are alternately connected to the power line, the ground line, the power line, the ground line, ... , A capacitance is formed between the adjacent internal electrodes.

According to the multilayer capacitor having the above structure,
The external electrodes are formed on at least a part of both front and back main surfaces of the laminated body including the dielectric and the internal electrodes, and the internal electrodes and the external electrodes having the same polarity are formed by a plurality of the columnar connecting members. Since the columnar connecting members are arranged at locations where the electromagnetic fields caused by the currents flowing through the internal electrodes cancel each other out, the directions of the currents flowing through the internal electrodes are dispersed so as not to be biased in a certain direction. At the same time, the number of the columnar connecting members shortens the distance through which the current flows, resulting in a decrease in ESL.

Further, since a capacitance is formed on the facing surface of the laminated internal electrodes, a large capacitance can be obtained.

Further, when mounting, by connecting the LSI chip to the external electrodes by, for example, wire bonding, it is not necessary to integrate a large number of current paths, the mutual inductance is reduced, and the connection path is shortened. Therefore, the inductance between the LSI chip and the multilayer capacitor is reduced.

[0023]

Embodiments of the multilayer capacitor according to the present invention will be described below with reference to the drawings. Here, a case where four layers of internal electrodes are formed will be described. 1, 2 and 3 are a perspective view, a bottom view and an exploded perspective view showing a multilayer capacitor according to an embodiment. 11, 21, 31, 4 in the figure
Reference numerals 1 and 51 denote dielectric plates formed by using a high dielectric constant material such as barium titanate.
A plurality of through holes 11a, 21a, 31
a, 41a, 51a are formed. Dielectric plate 11 ~
Internal electrodes 12, 22, 32, 4 are formed on portions of each upper surface of 41 except for a certain width around the upper surface by using a metal paste made of Pb, Pt, Ag, Pd-Ag or the like that can be co-fired with a dielectric.
2 is formed. The dielectric plate 11 to 51 and the internal electrodes 12 to 42 are sequentially and alternately laminated to form the laminated body 15. Pb, Pt, Ag, and Pd capable of being simultaneously fired with a dielectric are formed on both front and back main surfaces of the laminate 15.
The external electrode 56 and the external electrode 16 are formed using a metal paste such as -Ag. Then, the external electrodes 16 having the same polarity and the internal electrodes 12 and 32 having the alternate layers are connected by the columnar terminals 13 filled in the through holes 11a to 31a, and the external electrodes 56 having the same polarity and the internal electrodes having the alternate layers. 22 and 42 are connected by the columnar terminals 14 filled in the through holes 21a to 51a. The columnar terminals 13 and 14 are made of a metal paste made of Pb, Pt, Ag, Pd-Ag, or the like, which has conductivity and can be co-fired with the dielectric, and the internal electrodes 12 to 4 are formed.
It is arranged at a position where the electromagnetic field due to the current flowing through the element 2 cancels out. Further, the internal electrodes 22, 42 are formed with hollow portions 22a, 42a for not connecting the columnar terminals 14, and the internal electrodes 12, 32 are formed with hollow portions 12a, 32a for not connecting the columnar terminals 13. Cage,
The multilayer capacitor 10 is configured by including the multilayer body 15 and the external electrodes 16 and 56.

In order to manufacture the laminated capacitor 10 having such a structure, first, a dispersant, an organic binder and a plasticizer are added to a barium titanate powder to which a glass-based sintering aid is added, and the mixture is kneaded. A dielectric sheet is obtained by forming a sheet having a thickness of about 50 μm by a doctor blade method.

Next, the baked size is, for example, 15 m in the vertical direction.
After cutting the dielectric sheet into a size of 15 mm in width and 15 mm in width, a plurality of through holes are formed in each of the three dielectric sheets so as to have the same arrangement as the through holes 21a shown in FIG. FIG. 3 of one main surface of the three dielectric sheets formed.
The internal electrode 22 is formed by the screen printing method using a metal mask on the same portion as the portion where the internal electrode 22 is formed, that is, on the portion except for the cutout portion 22a where the columnar terminals 13 and 14 having a constant peripheral width and different polarities are not connected. At the same time as forming each pattern, a Pd—Ag paste as a metal paste is filled in all the through holes.

After that, the internal electrode pattern is formed on the upper surface 3
The dielectric sheets are sequentially laminated one by one while rotating 180 ° one by one.

Next, a plurality of through holes are formed in another two dielectric sheets so as to have the same arrangement as the through holes 51a shown in FIG. External electrode patterns are respectively formed on the entire one main surface by a screen printing method using a metal mask, and at the same time, all the through holes are filled with the metal paste. An internal electrode pattern is formed by a screen printing method using a metal mask on a portion except a certain peripheral width. After this, a dielectric sheet having only the external electrode pattern formed on the laminated dielectric sheet is hollowed out around the upper surface of the dielectric sheet with the external electrode pattern as the upper surface and the positions of the through holes. The dielectric sheet having the external electrode pattern and the internal electrode pattern is further laminated under the laminated dielectric sheet so as to be aligned with the position of the through hole where the portion is not formed. The position of the through hole in the uppermost dielectric sheet is 18
The laminated dielectric sheets are formed by laminating them so that they are rotated by 0 °. At this time, the through holes and the internal electrode patterns are formed such that the columnar terminals 13 and 14 are arranged at locations where the electromagnetic fields due to the currents flowing through the internal electrodes 12 to 42 cancel each other out.

Next, the laminated dielectric sheet is fired in the air at 1250 ° C. to produce the laminated capacitor 10.

FIG. 4 is a schematic diagram showing the direction of the current flowing through the internal electrode 12 in the multilayer capacitor 10 according to the embodiment when the polarity of the internal electrode 12 is +, and FIG. 5 is the polarity of the internal electrode 22. It is a schematic diagram showing the direction of the current flowing through the internal electrode 22 when is −.

As is clear from FIGS. 4 and 5, in the multilayer capacitor 10 according to the embodiment, the currents flowing through the internal electrodes 12 and 22 flow from + to − as a whole, and the directions thereof are respectively expressed as vectors. Spreads in all directions, or flows in from all directions. The distance through which the current flows is as short as 1/2 of the distance between the columnar terminals 14 of the same type. in this way,
By geometrically considering the arrangement of the columnar terminals 13 and 14, it is possible to disperse the direction of the current to cancel the electromagnetic field of the current, shorten the distance through which the current flows, and reduce the ESL.

Actually, the multilayer capacitor 10 according to the embodiment
When the ESL was examined, it was confirmed that the value was as small as 0.05 nH.

FIG. 6 is a schematic sectional view showing one usage example of the multilayer capacitor 10 according to the embodiment. Here, LS
The multilayer capacitor 10 having a size slightly larger than the I-chip 57 was used. Reference numeral 55 in the figure denotes a package, and the multilayer capacitor 1 mounted in the package 55.
0 is closely connected to the power supply layer 69 of the package 55 by a conductive material, and the external electrode 16 on the lower surface of the multilayer capacitor 10 is the external electrode terminal of the power supply line and the external electrode 5 on the upper surface.
6 is an external electrode terminal of the ground line. An LSI chip 57 made of a conductive material is closely attached to and connected to the external electrode 56. A ground terminal (not shown) of the LSI chip 57 is directly connected to the external electrode 56 by a wire 59,
Further, from the wire 60 to the package ground pad 61, via hole 62, ground layer 63, via hole 64, pin 65.
A large number of short current paths are secured by being connected to an external power source (not shown) through. On the other hand, the power supply terminal (not shown) of the LSI chip 57 is connected to the external electrode 16 of the multilayer capacitor 10 from the wire 66 through the pad 67 of the package, the via hole 68, and the power supply layer 69, and the external power supply through the via hole 53 and the pin 54. (Not shown).

As is apparent from FIG. 6, in the multilayer capacitor 10 according to the embodiment, since the external electrodes 16 and 56 having a large area are formed on the front and back main surfaces of the multilayer body 15,
The current path from the LSI chip 57 is directly the multilayer capacitor 1
0 is connected to the external electrode 56, or is connected to the external electrode 16 via a large number of current paths to secure a large number of short current paths, and it is not necessary to combine these current paths in the middle of the connection path, and the LSI chip 57 The inductance between the capacitor and the multilayer capacitor 10 can be reduced.

In this embodiment, the case where the external electrodes 16 and 56 are formed on the entire front and back main surfaces of the laminated body 15 has been described, but the portion where the external electrodes 16 and 56 are formed is the laminated body 15. It is sufficient to include all the columnar terminals 13 or the columnar terminals 14 instead of the entire main surfaces on both front and back sides.

As described above, in the multilayer capacitor 10 according to the embodiment, the direction of the current flowing through the internal electrodes 12 to 42 can be dispersed in all directions, and the current can be distributed by the large number of columnar terminals 13 and 14. Can be shortened and the ESL of the multilayer capacitor 10 itself can be reduced. Moreover, since a capacitance is formed on the opposing surfaces of the internal electrodes 12 to 42, a large capacitance can be obtained.

Further, by connecting the external electrodes 16 and 56 having a large area to the outside, they can be mounted directly below the LSI chip 57 mounted on the package 55 or the like. Further, when mounting, it is not necessary to integrate a large number of current paths, the inductance can be reduced, and
It is possible to shorten the connection path with the chip 57 and reduce the inductance between the LSI chip 57 and the multilayer capacitor 10.

[0037]

As described above in detail, in the multilayer capacitor according to the present invention, in a multilayer capacitor in which a plurality of dielectric plates and internal electrodes are alternately stacked, the multilayer plate including the dielectric plates and the internal electrodes is laminated. An external electrode is formed on at least a part of each of the front and back main surfaces of the body, the internal electrode and the external electrode having the same polarity are connected to each other by a plurality of columnar connecting members, and an electromagnetic field generated by a current flowing through the internal electrode. Since the columnar connecting members are arranged at positions where they cancel each other out, the direction of the current flowing through the internal electrodes can be dispersed in all directions, and the number of the columnar connecting members shortens the current flowing distance. However, the ESL of the multilayer capacitor itself can be reduced, and a large capacitance can be obtained because the capacitance is formed on the facing surface of the internal electrodes. Also, when mounting, it is not necessary to combine many current paths, and the inductance can be reduced,
The connection path with the LSI chip can be shortened, and the inductance between the LSI chip and the multilayer capacitor can be reduced. Therefore, it is possible to effectively remove switching noise and the like of the logic circuit particularly in a high frequency region.

[Brief description of drawings]

FIG. 1 is a perspective view schematically showing an embodiment of a chip type monolithic ceramic capacitor according to the present invention.

FIG. 2 is a bottom view showing a chip type monolithic ceramic capacitor according to an example.

FIG. 3 is an exploded perspective view of a laminated body portion of the chip type monolithic ceramic capacitor according to the example.

FIG. 4 is a schematic diagram showing a direction of a current flowing through an internal electrode in the multilayer capacitor according to the example.

5 is a schematic diagram showing directions of currents flowing through the internal electrodes adjacent to the internal electrodes shown in FIG. 4 in the multilayer capacitor according to the example.

FIG. 6 is a schematic cross-sectional view showing a case where the multilayer capacitor according to the example is mounted in a package in which an LSI is mounted.

FIG. 7 is a partial cross-sectional perspective view showing a conventional chip type monolithic ceramic capacitor.

FIG. 8 is an equivalent circuit diagram showing a circuit configuration of a chip type multilayer ceramic capacitor.

FIG. 9 is a graph showing frequency characteristics of impedance | Z | in a conventional chip type multilayer ceramic capacitor.

FIG. 10 is a schematic cross-sectional view showing the direction of current flow in a conventional multilayer capacitor.

FIG. 11 is a schematic cross-sectional view showing a case where a conventional chip type monolithic ceramic capacitor is mounted on a package in which an LSI is mounted.

[Explanation of symbols]

 10 Multilayer Capacitors 11, 21, 31, 41, 51 Dielectric Plates 12, 22, 32, 42 Internal Electrodes 13, 14 Columnar Terminals 15 Multilayers 16, 56 External Electrodes

Claims (1)

[Claims] 1. In a multilayer capacitor in which a plurality of dielectrics and internal electrodes are alternately stacked, an external electrode is formed on at least a part of both front and back main surfaces of a multilayer body including the dielectric and the internal electrode, The internal electrodes and the external electrodes having the same polarity are connected to each other by a plurality of columnar connecting members, and the columnar connecting members are arranged at locations where magnetic fields due to currents flowing through the internal electrodes cancel each other out. Characteristic multilayer capacitor.