JP2006179620A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit wherein high-density capacitors are formed in a standard logic integrated circuit manufacturing process. <P>SOLUTION: The electrodes of each same potential, the gray sections, and the slash sections are connected by contact holes so that in an M (1) layer, the electrodes in the gray section may serve as a lattice pattern and electrode terminals may be led out from a circumferential section. Moreover, in an M (2) layer, the electrodes of a shadow area serves as a lattice pattern, and an electrode terminals can be led out from the circumferential section. By this arrangement, a capacitor can be efficiently formed with rectangle electrodes and lattice electrodes. Furthermore, they can be manufactured without requiring a special process in addition to the usual manufacturing process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a capacitor element in a semiconductor integrated circuit.

Conventionally, there is an MIM (Metal-Insulator-Metal) structure as a capacitor element structure often used in a semiconductor integrated circuit. FIG. 8 is a diagram showing a conventional MIM structure. As shown in FIG. 8, the MIM structure of this prior art example includes an upper aluminum metal layer, an interlayer insulating film (SiO _{2 in} this example), and a lower polysilicon metal layer. In order to obtain a larger capacity with a smaller area, it is necessary to form a thin oxide film in a portion where the capacity is formed.

  In addition, such an MIM structure has a drawback in that the manufacturing process increases in order to form a large capacitance by thinning the oxide film in a portion where the MIM structure capacitance is formed. An example of the MIM structure is shown in the document “Analog Technology for VLSI Kyoritsu Publishing” on page 127 (Non-Patent Document 1).

  A method for increasing the capacitance density (capacitance value per unit area) of such an MIM structure capacitor is disclosed in “Patent Document 1”. 9 and 10 are diagrams showing a conventional MIM structure capacitance using this method.

  The conventional MIM structure capacitance will be described with reference to FIGS.

  As shown in FIGS. 9 and 10, the structure is formed by sequentially laminating a first metal film, a first insulating film, a second metal film, a second insulating film, and a third metal film on a semiconductor substrate. The first metal film and the third metal film are electrically connected. A first capacitor formed by the first metal film, the first insulating film, and the second metal film and a second capacitor formed by the second metal film, the second insulating film, and the third metal film are arranged in parallel. As a result, the capacity per unit area is increased.

  However, although the capacitance density is increased by such a structure, it is necessary to form the first and second insulating films thin in order to realize a high-capacity capacitance, resulting in an increase in the manufacturing process.

In addition, with recent advances in microfabrication technology, there is also a method of increasing the capacity density using the capacity in the vertical direction as disclosed in “Patent Document 2”. This conventional example is shown in FIG. As shown in the figure, a stock electrode portion 409 protruding toward the upper electrode 421 is formed on the lower electrode 413 of the MIM capacitor element, and a recess is formed on the upper electrode 421 corresponding to the lower electrode portion 409. The lower electrode portion 409 of the lower electrode 413 is disposed in the concave portion of the upper electrode 421 through a capacitive insulating film 415. The capacitance between the upper surface of the lower electrode 413 and the lower surface of the upper electrode 421 and the side surface of the lower electrode portion 409 of the lower electrode 413 and the side surface in the recess of the upper electrode 21 are increased to increase the capacitance density. Yes.
JP 2001-102529 A JP 2004-128466 A “Analog technology for VLSI” Kyoritsu Shuppan p. 127

  However, in the above-described method, the process steps are increased because the concave portions of the lower electrode portion 409 and the upper electrode 421 described above are formed.

  As described above, there are several methods for realizing a high-capacity density MIM capacitor in a semiconductor integrated circuit. In any case, even if the chip size is reduced and the cost is reduced, the number of process steps is increased. The manufacturing cost due to increases.

  For this reason, there is a problem that the number of masks necessary for manufacturing is increased in some cases, which leads to an increase in manufacturing cost.

  In addition, there is an increasing demand for the integration of analog circuits and logic circuits that require high-capacitance capacitors. At this time, there is a growing demand for mixed analog and logic using a normal logic process instead of a special process for forming a capacitor in order to reduce costs.

  The semiconductor integrated circuit according to the present invention has been made in view of the above-mentioned conventional problems, and provides a semiconductor integrated circuit that realizes a high-density capacitor in a standard logic semiconductor integrated circuit manufacturing process in order to meet the above-mentioned demand. It is intended to do.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention has the following features.

  A semiconductor integrated circuit according to the present invention includes a metal wiring layer formed in a grid pattern and an identical metal wiring layer formed in a rectangular pattern at the center of the metal wiring layer formed in the grid pattern. The capacitor element is formed by using the metal wiring layer formed in the lattice pattern as a first electrode and the same metal wiring layer formed in the rectangular pattern as a second electrode.

  The semiconductor integrated circuit according to the present invention includes a plurality of stacked metal wiring layers formed in the grid pattern forming the capacitor element and the same metal wiring layer formed in the rectangular pattern. Thus, the capacitor element is formed.

  Further, in the semiconductor integrated circuit according to the present invention, when the metal wiring layer forming the capacitor element is laminated, on the lattice point of the metal wiring layer formed in the lattice pattern as the first layer, Laminate so that the same metal wiring layer formed in the rectangular pattern that is the second layer matches, and connect the grid points of the first layer and the rectangular pattern of the second layer through contact holes to form capacitor elements It is characterized by doing.

  Further, the semiconductor integrated circuit according to the present invention is formed in a lattice pattern, the uppermost layer in which the metal wiring layer is formed in a solid pattern, the lowermost layer in which the metal wiring layer is formed in a solid pattern, and A plurality of intermediate layers comprising a metal wiring layer and a metal wiring layer formed in a rectangular pattern arranged in the center of the lattice, the lowermost layer, the intermediate layer, and the uppermost metal wiring layer The capacitor patterns are stacked so as to overlap each other, and each of the lattice patterns and a rectangular pattern arranged at the center of the lattice pattern are connected by a contact hole to form a capacitor element.

  As described above, according to the present invention, a capacitor element having a large capacity can be realized without using a special process for forming a capacitor by using a recent microfabrication technique.

  In addition, by making the pattern formed in a lattice pattern and the rectangular pattern formed in the center of the pattern and the interval the minimum interval, the parasitic capacitance between the wirings that have been increasing is actively and efficiently utilized by the recent fine processing technology. Thus, a large-capacity capacitor can be realized by a normal manufacturing process. Further, since the rectangular pattern is surrounded by the lattice pattern, it is easy to obtain processing accuracy due to pattern dependence, and high accuracy can be realized.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a semiconductor integrated circuit according to the present invention will be described in detail with reference to the drawings.

<Description of First Embodiment>
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.

  FIG. 1A is a diagram showing a first-layer metal wiring pattern, and FIG. 1B is a diagram showing a second-layer metal wiring pattern.

  In the figure, the gray portion 10 of the metal pattern indicates the first electrode, and the hatched portion 11 indicates the second electrode. In the figure, black circles 12 indicate contact holes for connecting the metal wiring of the first (hereinafter referred to as “M (1) layer”) layer and the metal wiring of the M (2) layer.

  It should be noted that the index i can be generally referred to as the M (i) layer. In this embodiment, since it is formed of two layers, they are denoted as M (1) layer and M (2) layer.

  FIG. 2 is a diagram showing a cross-sectional pattern between A and A ′ of the metal wiring pattern shown in FIG. 1.

  FIG. 3 is a view showing a cross-sectional pattern between B and B ′ of the metal wiring pattern shown in FIG.

  2 and 3, the gray portion 10 indicates a first electrode, the shaded portion 11 indicates a second electrode, and the black portion 12 indicates a contact hole connecting the metal wiring layers.

  Hereinafter, it demonstrates in detail according to the said FIGS. 1-3.

  The space between the grid pattern and the rectangular pattern of each metal wiring pattern is designed with the smallest possible spacing with the manufacturing technology. The capacitance of each metal wiring pattern is formed as indicated by C in the figure. With recent advances in microfabrication technology, the distance between the minimum distances has become smaller, and the thickness of the metal wiring has become larger than that. The capacitance of a capacitor increases as the distance between the electrodes decreases and the area of the overlapping electrodes increases, and the current microfabrication technology uses the parasitic capacitance on the side of the same wiring pattern as in this pattern. Efficient. Therefore, as shown in the present embodiment, a capacitor can be efficiently formed by forming an electrode formed in a rectangular pattern and a grid-like electrode pattern around the electrode at a minimum interval.

  Referring to the plan view of FIG. 1A, a capacitor is formed at a portion indicated by C in the figure between the grid-like electrode of the gray portion 10 and the rectangular electrode of the shaded portion 11. This is formed on each grid. Further, in the plan view of FIG. 1B, capacitors indicated by C are similarly formed between the rectangular electrodes of the gray portion 10 and the grid-like electrodes of the shaded portion 11, and capacitors are similarly formed for each lattice.

  FIG. 2 is a diagram showing a cross-sectional structure between A-A ′ shown in FIG. 1. The capacitor forming portion is indicated by C in the figure. In addition to the above-described lateral capacitor, a vertical capacitor is also formed to add more capacitance. It can also be seen that the grid pattern portion 10 (gray portion in the figure) is connected to electrodes from both sides of the capacitor pattern and can be drawn out as an electrode to the outside.

  FIG. 3 is a diagram showing a cross-sectional structure between B-B ′ shown in FIG. 1. The capacitor forming portion is indicated by C in the figure. In addition to the above-described lateral capacitor, a vertical capacitor is also formed to add more capacitance. It can also be seen that the grid pattern portion 11 (shaded portion in the figure) is connected to electrodes from both sides of the capacitor pattern and can be drawn out as an electrode to the outside.

  In this way, the electrodes of the same potential, the gray portions, and the shaded portions are connected by the contact holes, and in the M (1) layer, the gray portion electrodes become a lattice pattern, and the electrode terminals can be drawn from the outer peripheral portion. ing. In the M (2) layer, the shaded electrodes become a lattice pattern, and the electrode terminals can be drawn out from the outer periphery. With this configuration, a capacitor can be efficiently formed with rectangular electrodes and lattice electrodes. Moreover, it can manufacture without adding a special process from a normal manufacturing process in forming these.

<Description of Second Embodiment>
Next, a second embodiment of the present invention will be described. This is a technique for realizing a larger capacity in the same area by forming the first embodiment described above in multiple layers. In recent years, the number of metal wiring layers has been increasing in semiconductor integrated circuits, and this embodiment is an example of forming a larger capacity by adapting to such a multilayer wiring technology.

  4 is a diagram showing a metal wiring pattern of the M (i) layer (i = 1, 3, 5...), And FIG. 5 shows the M (i + 1) layer (i = 1, 3, 5,... It is a figure which shows the metal wiring pattern of (-).

  This embodiment shows an example of a metal wiring layer composed of six layers as a whole.

  The capacitance of the present embodiment is formed by the metal wiring layers from the M (1) layer (first layer) to the M (6) layer (sixth layer), and the M (1) layer, M (3) layer, M ( 5) The wiring pattern of the layer is formed as shown in FIG. 1A, and the wiring pattern of the M (2) layer, the M (4) layer, and the M (6) layer is formed as shown in FIG. 1B. ing. FIG. 4 is a cross-sectional view taken along the line A-A ′ of the capacitor thus formed, and FIG. 5 is a cross-sectional view taken along the line B-B ′. Capacitors formed on the plane and the cross section are shown in FIG.

  By forming in this way, a large-capacity capacitor is realized by using capacitors in both vertical and horizontal directions. For each electrode, gray electrodes are from the M (1) layer, M (3) layer, and M (5) layer, and hatched electrodes are from the M (2) layer, M (4) layer, and M (6) layer. Can be pulled out.

<Description of Third Embodiment>
Next, a third embodiment of the present invention is shown in FIGS.

  This embodiment shows an example in which a total of six metal wiring layers are formed as in the second embodiment. FIG. 6 shows a planar pattern of each wiring layer of the present embodiment. In the lowermost layer pattern, as shown in M-bottom of FIG. 6C, the electrode of the gray portion 20 is formed as a solid pattern. In the case of this embodiment, the first layer is formed.

  In the uppermost pattern, as shown by M-top 21 in FIG. 6A, the electrode of the shaded portion 21 is formed as a solid pattern. In this embodiment, it is formed of an M (6) layer.

  Further, the intermediate wiring layer is formed in a pattern indicated by M-middle in FIG. This is formed of an electrode of a gray portion 22 formed in a lattice pattern and an electrode of a shaded portion 23 of a rectangular pattern arranged in the center of the lattice. The upper and lower solid pattern electrodes of the gray lattice pattern of each layer are connected by a contact hole 24. Further, the upper and lower layers and the uppermost solid pattern electrodes of the hatched rectangular pattern of each layer are connected by a contact hole 24.

  FIG. 7 shows a cross-sectional view taken along the line A-A ′ of the capacitor thus formed. The capacitor portion formed by these configurations is indicated by C in FIGS.

  By forming in this way, a gap between the concave portions formed at the center of each lattice of the electrodes formed in a lattice shape from the lower layer is formed, and the convex electrodes connecting the rectangular pattern from above are inserted. A capacitor in which electrodes are formed in a comb shape in the vertical direction can be realized.

  By forming in this way, the capacitance between the side surfaces of the metal wiring layer, which can realize a larger parasitic capacitance in the recent microfabrication technology, is laminated to efficiently realize a large capacitance.

1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. (A) is a figure which shows the metal wiring pattern of a 1st layer, (b) is a figure which shows the metal wiring pattern of a 2nd layer. FIG. 2 is a structural diagram showing a cross-sectional structure between symbols A and A ′ shown in FIG. 1. FIG. 2 is a structural diagram showing a cross-sectional structure between symbols B-B ′ shown in FIG. 1. In the semiconductor integrated circuit according to the second embodiment of the present invention, the metal wiring pattern of the M (i) layer (i = 1, 3, 5...) Showing the cross-sectional structure between AA ′ in the drawing. FIG. In the semiconductor integrated circuit according to the second embodiment of the present invention, the metal wiring pattern of the M (i + 1) layer (i = 1, 3, 5...) Showing the cross-sectional structure between BB ′ in the figure. FIG. It is a figure which shows the plane pattern of each wiring layer of the 3rd Embodiment of this invention. (A) is a figure which shows M-top in which the electrode of the oblique line part 21 is formed with the solid pattern. (B) is a diagram showing M-middle which is an intermediate wiring layer. (C) is a figure which shows M-bottom in which the electrode of the gray part 20 is formed with the solid pattern. It is a figure which shows the cross-section between A-A 'shown in FIG.6 (c). It is a figure which shows the conventional MIM structure which is the structure of the capacitor | condenser element often used in a semiconductor integrated circuit. It is a figure which shows the MIM structure capacity | capacitance of a prior art example. It is a figure explaining the cross-section of the prior art example of FIG. It is a figure which shows the MIM structure capacity | capacitance of another prior art example.

Explanation of symbols

10, 20, 22 Gray part (lattice pattern part)
11, 23 Shaded portion (rectangular pattern portion)
12 Black circle (contact hole)
21 M-top layer 24 Contact hole 30 First electrode 30a First electrode wiring connection 31 Second electrode 31a Second electrode wiring connection 32 Lead wire 33 Third electrode 34 First protective film 35 First metal wiring 36 Second metal wiring 37 GaAs substrate 38 Insulating film 39 First interlayer insulating film 40 First capacitor insulating film 41 Second interlayer insulating film 42 Second capacitor insulating film 43 Second protective film (surface protective film)
50 First interlayer insulating layers 50a, 55a, 57a Silicon oxide films 50b, 55b, 57b Silicon nitride film 51 First metal wiring layers 52, 59 Barrier metal layer 53 Lower electrode 54 Lower electrode portion 55 Second interlayer insulating film 56 Capacitance insulation Film 57 Third interlayer insulating film 58 Upper electrode 60 Upper electrode portion 61 Second metal wiring layer and via 62 Cap layer

Claims (4)

A metal wiring layer formed in a lattice pattern;
The same metal wiring layer formed in a rectangular pattern in the center of the metal wiring layer formed in the lattice pattern,
A semiconductor integrated circuit, wherein a capacitor element is formed by using the metal wiring layer formed in the grid pattern as a first electrode and the same metal wiring layer formed in the rectangular pattern as a second electrode. .   The capacitor element is formed by laminating a plurality of metal wiring layers formed in the grid pattern forming the capacitor element and the same metal wiring layer formed in the rectangular pattern as a set. The semiconductor integrated circuit according to claim 1.   When laminating the metal wiring layer forming the capacitor element, it is formed in a rectangular pattern as a second layer on the grid points of the metal wiring layer formed in the grid pattern as the first layer. 3. The capacitor element is formed by stacking so that the same metal wiring layer matches, and connecting the lattice points of the first layer and the rectangular pattern of the second layer through contact holes. Semiconductor integrated circuit. A top layer in which the metal wiring layer is formed in a solid pattern; and
The lowest layer in which the metal wiring layer is formed in a solid pattern;
A plurality of intermediate layers comprising a metal wiring layer formed in a lattice pattern and a metal wiring layer formed in a rectangular pattern disposed in the center of the lattice;
The lowermost layer, the intermediate layer, and the metal wiring layer pattern of the uppermost layer are stacked so that they overlap each other, and each of the lattice patterns and the rectangular patterns arranged at the center of the lattice pattern are contact holes. A semiconductor integrated circuit characterized in that a capacitor element is formed by connection.

Images