JP2007013211A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which does not need a specific process for forming a capacitor in the semiconductor device equipped with an MIM capacitor. <P>SOLUTION: In the semiconductor device, four strip electrodes, whose longitudinal directions are the same, are formed in each layer of wiring layers M2 to M5 which are provided by a same design rule with each other, simultaneously with regular wirings. For example, in the wiring layer M2, two pieces each of a first electrode 2A and a second electrode 2B are formed parallelly with each other, alternately, and remote from each other. Then, the electrodes 2A to 5A are connected to each other by a via, the electrodes 2B to 5B are connected to each other by the via, a structure body 10A formed by connecting the electrodes 2A to 5A and the via to each other is connected to a ground wiring GND, and a structure body 10B formed by connecting the electrodes 2B to 5B and the via to each other is connected to a power source wiring VDD. Thereby, a capacitor C is formed by the structure body 10A and the structure body 10B. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device including a MIM (Metal-Insulator-Metal) capacitor, and more particularly to a semiconductor device in which a manufacturing process is simplified.

Conventionally, when a capacitor is formed in a semiconductor device, a lower electrode, a capacitive insulating film, and an upper electrode are stacked in this order on a substrate to form an MIM capacitor (for example, Non-Patent Document 1).
reference. ).

FIG. 4 is a cross-sectional view showing a semiconductor device having a conventional MIM capacitor. As shown in FIG. 4, in this conventional semiconductor device, an oxide film 102 is provided on a substrate 101, and a lower electrode 103 made of metal is provided thereon. A capacitive insulating film 104 is provided on the lower electrode 103, an upper electrode 105 is provided thereon, and a cap film 106 is provided thereon. The upper electrode 105 is connected to the wiring 109 through the base layer 107 and the via 108, and the lower electrode 103 is connected to the wiring 111 through the base layer 107 and the via 110. As a result, the MIM capacitor 112 is formed by the lower electrode 103, the capacitor insulating film 104 and the upper electrode 105. Further, the lower electrode 103, the capacitor insulating film 104, the upper electrode 105, and the like are embedded in the interlayer insulating film 113.

Also disclosed is a technique in which a capacitor insulating film and an upper electrode are formed so as to cover the lower electrode, and a MIM capacitor is formed using a side surface in addition to the upper surface of the lower electrode (see, for example, Patent Document 1). ).

FIG. 5A is a plan view showing a semiconductor device provided with this conventional MIM capacitor.
b) is a sectional view taken along line DD shown in FIG. As shown in FIGS. 5A and 5B,
In this conventional semiconductor device, a silicon substrate 121 is provided, and a diffusion layer 122 is formed on a part of the surface of the silicon substrate 121. An interlayer insulating film 123 is provided on the silicon substrate 121, and a plug 124 connected to the diffusion layer 122 is formed in the interlayer insulating film 123. Further, a lower electrode 125 is provided on the interlayer insulating film 123 so as to be connected to the plug 124, and a barrier insulating layer 126 and a high dielectric constant film 127 are provided so as to cover the lower electrode 125. A capacitor insulating film 128 is formed by the barrier insulating layer 126 and the high dielectric constant film 127. In addition, an upper electrode 129 is provided so as to cover the capacitor insulating film 128. As a result, the capacitor 130 is formed by the lower electrode 125, the capacitor insulating film 128 and the upper electrode 129. According to this conventional technique, a capacitor can be formed on the side surface in addition to the upper surface of the lower electrode 125.

M. Armacost, et. Al. "A High Reliability Metal Insulator Met al Capacitor for 0.18um Copper Technology" IEDM2000 pp.157-160 JP 2002-222934 A

However, the conventional techniques described above have the following problems. As mentioned above,
When a capacitor is formed by stacking a lower electrode, a capacitor insulating film, and an upper electrode in this order, the lower electrode can be formed simultaneously with other wirings in the wiring layer of the semiconductor device. However, when a normal interlayer insulating film is used as the capacitor insulating film, the thickness of the interlayer insulating film is 0.3 to 1.0 μm.
Since the thickness is about m, the capacitance insulating film becomes too thick and the capacitance value of the capacitor decreases.
Therefore, an insulating film having a thickness of about 50 nm is specially formed on the capacitor insulating film, and an upper electrode is formed on the capacitor insulating film. As a result, a special process for forming the capacitor insulating film and the upper electrode is required, and the number of masks is increased by about 1 to 2 as compared with the case where no capacitor is formed, and an additional etching process is also required. Become. This complicates the manufacturing process of the semiconductor device and increases the manufacturing cost.

The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device that includes a MIM capacitor and does not require a special process for forming the capacitor.

The semiconductor device according to the present invention has a plurality of wiring layers stacked on each other, and each wiring layer is embedded in the interlayer insulating film and the first and second layers embedded in the interlayer insulating film and separated from each other. An electrode, a first via that interconnects the first electrode and the first electrode of the wiring layer provided in the upper layer or the lower layer, and the second electrode and the upper layer or the lower layer. A second via interconnecting the second electrode of the wiring layer, wherein the first electrode and the first via are connected to a first terminal, and the second electrode and A second via is connected to a second terminal, and a capacitor is formed between the first electrode and the first via and the second electrode and the second via.

In the present invention, in the wiring layer of the semiconductor device, the first and second electrodes can be formed simultaneously with the normal wiring, and the first and second vias can be formed simultaneously with the normal via. . For this reason, it is not necessary to provide a special process for forming the capacitor.
In addition, the first and second electrodes are formed in a plurality of wiring layers, the first electrodes are connected by a first via, the second electrodes are connected by a second via, By connecting the electrode and the first via to the first terminal, and connecting the second electrode and the second via to the second terminal, the first electrode and the first via
A capacitor can be formed between the via and the second electrode and the second via. Thus, the capacitance value per unit area in the capacitor can be increased by making the capacitor structure a vertical product structure.

The plurality of wiring layers are preferably provided with the same design rule. Thereby, the first and second electrodes having the same shape can be formed in each wiring layer, the design of the capacitor is facilitated, and the capacitance value per unit area can be further improved.

Furthermore, it is preferable that three or more wiring layers are provided. As a result, the effect of making the capacitor structure a vertically stacked structure becomes remarkable, and the capacitance value of the capacitor per unit area can be further improved.

Furthermore, when viewed from the stacking direction of the wiring layer, the plurality of first vias are arranged at positions where they overlap each other, and the plurality of second vias are arranged at positions where they overlap each other. It is preferable. Thereby, the distance between the first via provided in one wiring layer and the first via provided in the other wiring layer is reduced, and the structure including the first electrode and the first via is formed. The internal resistance of the body can be reduced. Similarly, the internal resistance of the structure including the second electrode and the second via can be reduced. Further, since the distance between the first via and the second via can be reduced in the same wiring layer, the capacitance value between the first via and the second via is increased. Can do.

Furthermore, when viewed from the stacking direction of the wiring layer, a plurality of the first electrodes are arranged at positions where they overlap each other, and a plurality of the second electrodes are arranged at positions where they overlap each other. It is preferable. Thereby, the area of the capacitor can be reduced when viewed from the stacking direction of the wiring layers, and as a result, the capacitance value per unit area can be increased.

Furthermore, in the same wiring layer, the distance between the first electrode and the second electrode is 0.
. It is preferably 3 μm or less, and more preferably 0.2 μm or less. As a result, the distance between the electrodes becomes as small as about 6 times the thickness (for example, 50 nm) of the conventional capacitive insulating film, and the capacitance value of the capacitor can be increased.

Furthermore, in the same wiring layer, the distance between the first electrode and the second electrode is
The minimum value allowed by the design rule of the wiring layer is preferable, and the distance between the first via and the second via formed at a position closest to the first via is as follows: The minimum value allowed by the wiring layer design rule is preferable. Furthermore, the vias in each electrode are preferably arranged in a line along the longitudinal direction of the electrodes, and all the first vias are preferably arranged so as to face the second vias. Thereby, in the same wiring layer, the distance between the first electrode and the second electrode and the distance between the first via and the second via can be reduced. The capacitance value of the capacitor can be increased.

Furthermore, it is preferable that the first and second electrodes have a strip shape parallel to each other. Thereby, the area of the side surface contributing to the capacitance value of the capacitor in the first and second electrodes can be increased, and the capacitance value per unit area in the capacitor can be increased.

At this time, it is preferable that a plurality of the first and second vias are arranged in the longitudinal direction of the first and second electrodes for each of the first and second electrodes. As a result, all the first vias face the second vias, and the capacitance value of the entire capacitor increases.

At this time, the distance between the first vias in the longitudinal direction of the first electrode is the distance between the first and second vias of the first and second electrodes adjacent to each other in each wiring layer. The distance between the second vias in the longitudinal direction of the second electrode is larger than the distance between the first and second vias of the first and second electrodes adjacent to each other in each wiring layer. Is also preferably large. Thus, without increasing the distance between the first via and the second via,
Lithography accuracy can be ensured when forming the first and second vias, and the first via can be prevented from contacting the second via.

Alternatively, at least one of the first and second vias may be a slit-type via extending in the longitudinal direction of the first and second electrodes.

Furthermore, the semiconductor device according to the present invention may have an integrated circuit part, and the diameters of the first and second vias may be larger than the diameters of vias provided in the integrated circuit part. As a result, the side areas of the first and second vias are increased, and the distance between the first and second vias is reduced to increase the capacitance value between the first and second vias. Can do.

Furthermore, a decoupling capacitor in which the first terminal is connected to a ground wiring, the second terminal is connected to a power supply wiring, and the capacitor is connected in parallel to a power supply may be used. Thereby, power supply noise can be absorbed and the operation of the semiconductor device can be stabilized.

Furthermore, a semiconductor device according to the present invention includes an upper electrode provided in a region including a region immediately below the first and second electrodes and connected to one of the first and second terminals, and the upper electrode. An insulating film provided below the insulating film, and a lower electrode provided below the insulating film and connected to the other of the first and second terminals, and the upper electrode and the lower electrode Another capacitor may be formed between them. Thereby, the total capacitance value of the capacitor and the other capacitor can be obtained, and the capacitance value per unit area of the capacitor can be further improved.

Furthermore, an N-type semiconductor layer provided in a region including a region immediately below the first and second electrodes and connected to a terminal to which a higher potential is applied among the first and second terminals; A P-type semiconductor layer provided in contact with the N-type semiconductor layer in a region including a region and connected to a terminal to which a lower potential is applied among the first and second terminals. Another capacitor may be formed between the p-type semiconductor layer and the p-type semiconductor layer. Thereby, the total capacitance value of the capacitor and the other capacitor can be obtained, and the capacitance value per unit area of the capacitor can be further improved.

Or having a semiconductor substrate disposed below the wiring layer, the semiconductor substrate being the first substrate
And an N-type semiconductor region formed in a region including a region directly below the second electrode and connected to a terminal to which a higher potential is applied among the first and second terminals, and a region including the region directly below A P-type semiconductor region formed in contact with the N-type semiconductor region and connected to a terminal to which a lower potential is applied among the first and second terminals, and the N-type semiconductor region and the P-type semiconductor region Another capacitor may be formed between the type semiconductor region. Thereby, the total capacitance value of the capacitor and the other capacitor can be obtained, and the capacitance value per unit area of the capacitor can be further improved.

According to the present invention, in each wiring layer of a semiconductor device, the first and second electrodes can be formed simultaneously with the normal wiring, and the first and second vias are formed simultaneously with the normal via. Can do. For this reason, MI does not require a special process for forming a capacitor.
A semiconductor device including an M capacitor can be manufactured.

Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a perspective view showing an MIM capacitor provided in the semiconductor device according to the present embodiment, FIG. 2 is a plan view showing the MIM capacitor, and FIG. 3A is an AA line shown in FIG. (B) is sectional drawing by the BB line.

As shown in FIG. 1, in the semiconductor device according to this embodiment, a semiconductor substrate (not shown)
A plurality of layers, for example, nine wiring layers are laminated on the semiconductor substrate. This 9
Among the wiring layers of the layers, the second to fifth wiring layers (hereinafter referred to as wiring layers M2 to M5) from the bottom, that is, the semiconductor substrate side, are intermediate wiring layers and are provided with the same design rule. Yes. The sixth to ninth wiring layers (hereinafter referred to as wiring layers M6 to M9) from the bottom are global wiring layers, which have different design rules from the wiring layers M2 to M5, and have a minimum dimension larger than that of the wiring layers M2 to M5. It is getting bigger. The lowermost wiring layer (wiring layer M1) has a design rule different from that of the wiring layers M2 to M5, and the minimum dimension is smaller than that of the wiring layers M2 to M5.

Further, as shown in FIGS. 3A and 3B, an interlayer insulating film 1 is provided in each wiring layer, and wiring is provided on the surface of the interlayer insulating film 1. 1 is provided with vias for interconnecting the wiring and a wiring provided in a wiring layer below the wiring.

In particular, in the capacitor formation region of the semiconductor device, four strip-shaped electrodes each having the same longitudinal direction are embedded in the same layer as the wiring on the surface of the interlayer insulating film 1. That is, in the wiring layer M2, two electrodes 2A and two electrodes 2B are provided on the surface of the wiring layer M2, and are parallel to each other, alternately and perpendicular to the stacking direction of the wiring layers M2 to M5. They are spaced apart from each other in the direction. Similarly, in the wiring layer M3, the electrodes 3A and 3B are connected to the wiring layer M.
In FIG. 4, electrodes 4A and 4B are arranged, and in the wiring layer M5, two electrodes 5A and 5B are arranged in parallel with each other, alternately and spaced apart from each other. The electrodes 2A to 5B are formed at the same time as the wiring in the region other than the capacitor formation region in the normal wiring formation process of the semiconductor device.

On the other hand, the global wiring layer, that is, any one of the wiring layers M6 to M9 is provided with the ground wiring GND and the power supply wiring VDD. And the electrode 5 provided in the wiring layer M5
A is connected to the ground wiring GND through a via (not shown), for example, and the electrode 5B is
For example, the power supply wiring VDD is connected via a via (not shown). The length in the longitudinal direction of the electrodes 2A to 5B is, for example, 10 to 100 μm, and the width may be a dimension that is allowed in the design rule, for example, 0.3 μm or less, and for example, the minimum dimension that is allowed in the design rule. It is 0.14 μm. The thickness of the wiring layer at that time is, for example, 0.3 μm. The distance between the electrode 2A and the electrode 2B is a minimum dimension allowed in the design rule, and is 0.3 μm or less, for example, 0.14 μm. The distance between electrode 3A and electrode 3B;
The same applies to the distance between the electrode 4A and the electrode 4B and the distance between the electrode 5A and the electrode 5B.
3 μm or less, for example, 0.14 μm. When the wiring interval is wider than 0.14 μm, for example 0.28 μm, the thickness of the wiring layer is set to 0.45 to 0.6 μm and 0.3 μm, for example.
If it is formed thicker than m, the capacitance value can be obtained from (2/3) times the equivalent value when the wiring interval is 0.14 μm.

Further, as shown in FIG. 2 and FIGS. 3A and 3B, in the wiring layer M3, the electrode 2
A plurality of vias VA3 that connect A to the electrode 3A are provided. The vias VA3 are arranged in a line along the longitudinal direction of the electrodes 2A and 3A. The shape of the via VA3 is designed, for example, in a square shape when viewed from the stacking direction of the wiring layers, and the length of one side of the square is, for example, 0.1.
3 μm.

The wiring layer M3 is provided with a plurality of vias VB3 that connect the electrode 2B to the electrode 3B. The arrangement, shape, and dimensions of the via VB3 are the same as those of the via VA3. Similarly, in the wiring layer M4, a plurality of vias VA4 that connect the electrode 3A to the electrode 4A, and the electrode 3B
A plurality of vias VB4 that connect the electrode 4B to the electrode 5B are provided. In the wiring layer M5, a plurality of vias VA5 that connect the electrode 4A to the electrode 5A and a plurality of vias VB5 that connect the electrode 4B to the electrode 5B are provided. Is provided. The vias VA3 to VB5 are formed simultaneously with vias in regions other than the capacitor formation region in a normal via formation process of the semiconductor device.

With the configuration as described above, as shown in FIG. 1, the electrodes 2A to 5A and vias VA3 to V
A5 are connected to each other to form a structure 10A, and this structure 10A is connected to the ground wiring GND via a terminal (not shown). Also, the electrodes 2B to 5B and the vias VB3 to VB5
Are connected to each other to form a structure 10B, and this structure 10B is connected to the power supply wiring VDD via another terminal (not shown). The structure 10A and the structure 10B are insulated from each other.

The distance a (see FIG. 2) between the via VA3 and the adjacent via VB3 is, for example, 0.1.
5 μm. The distance between the via VA4 and the via VB4 and the distance between the via VA5 and the via VB5 are the same. Further, the distance b (see FIG. 2) between the vias VA3 in the longitudinal direction of the electrode is larger than the above-described distance a, for example, 0.17 to 0.19 μm. Via VA
The same applies to 4 to VB5. Further, when the wiring interval is wide, for example, 0.28 μm, the wiring interval is widened by increasing the via size to, for example, about 0.28 μm or increasing the via height. It is possible to compensate for the decrease in capacitance due to the increase in the side area of the via.

2 and FIGS. 3A and 3B show an example in which three vias are connected to one electrode in order to simplify the drawing. For example, four or more vias may be connected to one electrode.

Next, the operation of the semiconductor device according to this embodiment will be described. When a ground potential is applied to the ground wiring GND, the electrode 5A, the via VA5, the electrode 4A, the via VA4, the electrode 3A, and the via VA
3 and a ground potential is applied to the structure 10A composed of the electrode 2A. When a power supply potential is applied to the power supply wiring VDD, a power supply potential is applied to the structure 10B including the electrode 5B, the via VB5, the electrode 4B, the via VB4, the electrode 3B, the via VB3, and the electrode 2B. Since the structure 10A and the structure 10B are insulated from each other, the capacitor C is formed between the structure 10A and the structure 10B. That is, mainly between the adjacent electrodes 2A and 2B, between the electrodes 3A and 3B, between the electrodes 4A and 4B, between the electrodes 5A and 5B, and
Between via VA3 and via VB3 adjacent to each other, between via VA4 and via VB4, via V
A capacitor is formed between A5 and via VB5. The capacitor C is a decoupling capacitor connected in parallel to the power supply and can absorb power supply noise.

In the present embodiment, the electrodes 2A and 2B can be formed on the wiring layer M2 simultaneously with the normal wiring. Similarly, the electrodes 3A to 5B can be formed simultaneously with the normal wiring in each wiring layer. Also, the vias VA3 and VB3 can be formed in the wiring layer M3 simultaneously with the normal vias. Similarly, the vias VA4 to VB5 can be formed simultaneously with normal vias in each wiring layer. For this reason, it is not necessary to provide a special process for forming the capacitor C.

In the present embodiment, the capacitor C having a four-layered vertical structure is formed in the wiring layers M2 to M5. For this reason, the capacitance value per unit area of the capacitor C is large.

Further, since the electrodes 2A to 5B are formed in the wiring layers M2 to M5 having the same design rule, the electrodes 2A to 5B are formed in the same strip shape, and the electrode 2A is viewed from the lamination direction of the wiring layers. 5A and the electrodes 2B to 5B can be formed to overlap each other. Further, the vias VA3 to VB5 can have the same shape, and the vias VA3 to VA5 and the vias VB3 to VB5 can be formed so as to overlap each other when viewed from the stacking direction of the wiring layers. Thereby, the internal resistance in the structures 10A and 10B can be reduced, and the distance between the via in the structure 10A and the via in the structure 10B can be reduced. As a result, the capacitance value per unit area of the capacitor C can be further increased.

Furthermore, when viewed from the stacking direction of the wiring layers, each electrode has a strip shape and is arranged in parallel to each other. For this reason, the area of the side surface contributing to the capacitance value of the capacitor C in each electrode can be increased, and the capacitance value per unit area in the capacitor C can be increased. Also, the vias between the electrodes are arranged in a line along the longitudinal direction of the electrodes, and the vias to which all the ground potentials are applied are arranged so as to face the vias to which the power supply potential is applied. The capacitance value of the entire capacitor C increases.

In addition, since the distance b between the vias in the longitudinal direction of the electrode is larger than the distance a in the short direction of the electrode, the vias can be formed without increasing the distance between the structure 10A and the structure 10B. Lithography accuracy during formation can be ensured. This can prevent the via to which the ground potential is applied from coming into contact with the via to which the power supply potential is applied. In addition,
If the distance b is set to a minimum dimension according to the design rule, for example, 0.14 μm, the lithography accuracy when forming the via is lowered, the via becomes large, and the vias may be short-circuited.

In the present embodiment, the example in which the capacitor C is formed in the four wiring layers M2 to M5 has been shown. However, the present invention is not limited to this, and the capacitor is formed in three or less wiring layers or five or more wiring layers. It may be formed. However, the wiring layers forming the capacitors are preferably provided with the same design rule. In order to secure a capacitance value per unit area, it is preferable to form capacitors in three or more wiring layers.

Further, the dimensions of the vias VA3 to VB5 may be larger than the dimensions of the vias in a region other than the capacitor formation region in this semiconductor device. Thereby, in the capacitor C, the capacitance value generated between the vias can be increased.

Furthermore, the shape of the via is not limited to a square shape, and may be a slit-type via extending in the longitudinal direction of the electrode, for example. Thereby, the capacitance value between vias can be further increased.

Furthermore, in the present embodiment, the structure 10A is connected to the ground wiring GND, and the structure 1
Although an example in which 0B is connected to the power supply wiring VDD and the capacitor C is a decoupling capacitor connected in parallel to the power supply is shown, the present invention is not limited to this, and the capacitor C is used as a capacitor constituting the circuit. May be.

Furthermore, a semiconductor device including the capacitor C may be formed on the semiconductor chip, and at this time, the ground wiring GND and the power supply wiring VDD may be disposed on the outer periphery of the semiconductor chip.

Further, a normal MIM capacitor may be formed below the capacitor C. That is, a plate-like upper electrode connected to the ground wiring GND is formed immediately below the capacitor C in the wiring layer M1, and a capacitive insulating film having a thickness of, for example, 50 nm is formed immediately below the upper electrode. A plate-like lower electrode connected to the power supply wiring VDD may be formed immediately below the insulating film, and a capacitor may be formed by the upper electrode and the lower electrode. Thereby, the wiring layer M1
And a capacitor C formed on the wiring layers M2 to M5.
Can be connected in parallel, and the capacitance value per unit area can be further increased.

Further, a capacitor with a PN junction may be formed below the capacitor C. For example,
An N-type semiconductor layer connected to the power supply wiring VDD is formed on the surface of the semiconductor substrate immediately below the capacitor C or on the wiring layer M1. Then, P connected to the surface of the semiconductor substrate or the wiring layer M1 immediately below the capacitor C and to the ground wiring GND so as to be in contact with the N-type semiconductor layer.
Forming a mold type semiconductor layer; As a result, a reverse-biased PN junction is formed between the N-type semiconductor layer and the P-type semiconductor layer, thereby forming a capacitor. As a result, the capacitor by the PN junction and the capacitor C formed in the wiring layers M2 to M5 can be connected in parallel, and the capacitance value per unit area can be further increased.

Furthermore, an N-type semiconductor region connected to the power supply wiring VDD is formed immediately below the capacitor C in the semiconductor substrate, and a P-type semiconductor region connected to the ground wiring GND is in contact with the N-type semiconductor region. It may be formed. Thereby, a reverse-biased PN junction is formed between the N-type semiconductor region and the P-type semiconductor region, and a capacitor is formed. As a result, the capacitor by the PN junction and the capacitor C formed in the wiring layers M2 to M5 can be connected in parallel, and the capacitance value per unit area can be further increased.

Furthermore, in the present embodiment, an example in which the electrode is formed in a strip shape and the electrodes are arranged in parallel to each other is shown, but the present invention is not limited to this. For example, the shape of the electrode may be a curved wiring shape, and in the same wiring layer, electrodes connected to the ground wiring and electrodes connected to the power supply potential are alternately arranged in a matrix. Also good.

1 is a perspective view showing an MIM capacitor provided in a semiconductor device according to an embodiment of the present invention. It is a top view which shows this MIM capacitor. (A) is sectional drawing by the AA line shown in FIG. 2, (b) is sectional drawing by the BB line. It is sectional drawing which shows the semiconductor device provided with the conventional MIM capacitor. (A) is a top view which shows the semiconductor device provided with the other conventional MIM capacitor, (b) is sectional drawing by the DD line | wire shown to (a).

Explanation of symbols

1; interlayer insulating films 2A to 5A, 2B to 5B; electrodes VA3 to VA5, VB3 to VB5; via GND; ground wiring VDD; power supply wiring M2 to M5; wiring layers 10A and 10B; Substrate 102; Oxide film 103; Lower electrode 104; Capacitance insulating film 105; Upper electrode 106; Cap film 107; Underlayer 108 and 110; Vias 109 and 111; Wiring 112; MIM capacitor 113; Interlayer insulating film 121; Diffusion layer 123; interlayer insulating film 124; plug 125; lower electrode 126; barrier insulating layer 127; high dielectric constant film 128; capacitive insulating film 129; upper electrode 130;

Claims (20)

Each wiring layer has a plurality of wiring layers stacked on each other, each wiring layer including an interlayer insulating film, first and second electrodes embedded in the interlayer insulating film and spaced apart from each other, and the first electrode And a first via that interconnects the first electrode of the wiring layer provided in the upper layer or the lower layer thereof, and the second via of the second electrode and the wiring layer provided in the upper layer or the lower layer thereof. A second via connecting the electrodes to each other;
The first electrode and the first via are connected to a first terminal, the second electrode and the second via are connected to a second terminal, the first electrode and the first via, and the A capacitor is formed between the second electrode and the second via;
For each of the first and second electrodes, a plurality of the first and second vias are arranged in the longitudinal direction of the first and second electrodes, and are adjacent to the wiring layers. The first
The distance between the first via and the second via is a, the distance between the adjacent one vias in each wiring layer and the distance between the two adjacent vias are b, and the wiring layers The length of the first via and the second via in the longitudinal direction is c, and the length of each of the wiring layers perpendicular to the longitudinal direction of the first via and the second via is d. In some cases, the semiconductor device satisfies the relationship of a / d <b / c. The semiconductor device according to claim 1, wherein the plurality of wiring layers are provided with the same design rule. The semiconductor device according to claim 1, wherein three or more wiring layers are provided. When viewed from the stacking direction of the wiring layer, a plurality of the first vias are arranged at positions overlapping each other, and a plurality of the second vias are arranged at positions overlapping each other. The semiconductor device according to claim 3. When viewed from the stacking direction of the wiring layer, a plurality of the first electrodes are arranged at positions where they overlap each other, and a plurality of the second electrodes are arranged at positions where they overlap each other. The semiconductor device according to any one of claims 1 to 4. 6. The semiconductor device according to claim 1, wherein a distance between the first electrode and the second electrode in the same wiring layer is 0.3 μm or less. The distance between the first electrode and the second electrode in the same wiring layer is a minimum value allowed by the design rule of the wiring layer. 2. The semiconductor device according to claim 1. A distance between the first via and the second via formed at a position closest to the first via is a minimum value allowed by a design rule of the wiring layer. The semiconductor device according to claim 1. 9. The first and second electrodes have a strip shape parallel to each other.
The semiconductor device according to any one of the above. The semiconductor device according to claim 9, wherein a width of each of the first and second electrodes is 0.3 μm or less. 11. The semiconductor device according to claim 9, wherein the width of the first and second electrodes is a minimum value allowed by a design rule of the wiring layer. A plurality of the first and second electrodes are provided in each wiring layer, and the first and second electrodes are alternately arranged in each wiring layer. 12. The semiconductor device according to any one of 11 above. The distance between the first vias in the longitudinal direction of the first electrode is greater than the distance between the first and second vias of the first and second electrodes adjacent to each other in each wiring layer, Second
The distance between the second vias in the longitudinal direction of the electrodes is larger than the distance between the first and second vias of the first and second electrodes adjacent to each other in each wiring layer. The semiconductor device according to claim 9. The at least one of the first and second vias is a slit-type via extending in the longitudinal direction of the first and second electrodes. 14. Semiconductor device. 15. The device according to claim 1, further comprising an integrated circuit portion, wherein a diameter of the first and second vias is larger than a diameter of a via provided in the integrated circuit portion. Semiconductor device. The first terminal is connected to a ground wiring, the second terminal is connected to a power supply wiring;
The semiconductor device according to claim 1, wherein the capacitor is a decoupling capacitor connected in parallel to a power source. The semiconductor device according to claim 16, wherein the wiring layer is formed in a semiconductor chip, and the ground wiring and the power supply wiring are arranged on an outer periphery of the semiconductor chip. An upper electrode provided in a region including a region immediately below the first and second electrodes and connected to one of the first and second terminals; an insulating film provided below the upper electrode; and A lower electrode provided below the insulating film and connected to the other of the first and second terminals, and another capacitor is formed between the upper electrode and the lower electrode. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: An N-type semiconductor layer provided in a region including a region directly below the first and second electrodes and connected to a terminal to which a higher potential is applied among the first and second terminals; and the region directly below A P-type semiconductor layer provided in contact with the N-type semiconductor layer and connected to a terminal to which a lower potential is applied among the first and second terminals, and the N-type semiconductor layer The semiconductor device according to claim 1, wherein another capacitor is formed between the P-type semiconductor layer and the P-type semiconductor layer. A semiconductor substrate disposed below the wiring layer, the semiconductor substrate being formed in a region including a region directly below the first and second electrodes, and having a higher potential of the first and second terminals; And an N-type semiconductor region connected to a terminal to which voltage is applied, and a region including the region immediately below is formed so as to be in contact with the N-type semiconductor region, and a lower potential is applied to the first and second terminals. 19. A P-type semiconductor region connected to a terminal, and another capacitor is formed between the N-type semiconductor region and the P-type semiconductor region. 2. The semiconductor device according to claim 1.

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