JPH07200412A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the cache hit rate of the microprocessor. CONSTITUTION:This microprocessor is equipped with EXU101, EAG102, IDU104, ACU105, DCU106, MNUI1101, DCHE1102, and main storage 108. Data of low frequency of access are registered in a cache memory and data of high frequency of access are expelled from the cache memory to prevent the hit rate of the cache memory from decreasing. In addition to the function, this microprocessor is equipped with a function which improves the hit rate of the cache memory even for the data of low frequency of access by registering the data in the cache memory when an area where the data should be registered is free.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to microprocessors.

[0002]

2. Description of the Related Art First, virtual recording in the paging system will be described. The virtual record is a storage area in which the entire virtual space is divided by a space of a certain size (hereinafter referred to as a page), and a page table entry (hereinafter abbreviated as PTE) for each page. It has a region called. In this PTE, various information of the page is stored. As information stored in the PTE, there is information indicating whether or not the page exists in the main memory area. Also, if the page is in the main storage area, the information indicating where in the main storage area, the data contained in the page,
There is information such as whether to permit or prohibit registration in the cache. Virtual memory is a data read or write operation (hereinafter referred to as access)
By doing so, various information of the page is read from the PTE of the page corresponding to the virtual space desired to be accessed.

If the page corresponding to the accessed virtual address space is not in the main storage area, the execution of the program is interrupted, an exception is generated by hardware, and exception processing is executed. It This exceptional processing is to transfer the requested page from the auxiliary storage device such as a disk to the main storage area. At that time, information indicating that the page exists in the main memory and where the page exists in the main memory is set in the PTE. After the exception processing, the execution of the program is restarted and the area of the same virtual address space is accessed again. When the page corresponding to the accessed virtual address space is stored in the main memory area, the information indicating where the page exists in the main memory area is obtained from the PTE, so that the main memory is actually stored. Access is made.

Next, data registration in the cache at the time of access in the high-performance microprocessor will be described.

In the conventional high-performance microprocessor, data having a low access frequency is registered in the cache, so that data having a high access frequency is excluded from the cache, resulting in a decrease in the cache hit rate. is there. In order to cope with this problem, in order to prevent the cache hit rate from decreasing, the following measures are taken in the conventional high-performance microprocessor.

That is, when there is a page satisfying either of the following two conditions, information for prohibiting registration in the cache is added to those PTEs, and the data contained in those pages is added. I try not to register it in the cache. The first of the above conditions is
This is the case where the data of the program being executed spans multiple pages and the access frequency of most of the data contained in that page is clearly lower than the data contained in other pages. The second condition is
This is the case when the page contains data that should not be registered in the cache.

A specific example of the conventional high-performance microprocessor is a 32-bit microprocessor μPD70832 (hereinafter referred to as V80) manufactured by NEC Corporation. First, the data cache of data at the time of this V80 access (hereinafter referred to as DCHE
The registration operation for the above) will be briefly described. First, in V80, at the time of access, the virtual address is converted into a real address, and it is checked whether or not it is permitted to register the simultaneously accessed data in DCHE. Next, it is checked that the accessed data is registered in DCHE, and if registered, the DCHE is accessed to obtain the data. Then, if the data is permitted to be registered in the DCHE, the obtained data is registered in the DCHE, and if it is not permitted, no processing is performed.

Next, the V80 DCHE will be described [Reference: User's Manual μPD70832].
(V80 ^™ ) 32-bit Microprocessor Architecture Edition].

The V80 DCHE has a space of 1280 bytes, and the space is divided into two spaces of 640 bytes, which are called set (0) and set (1). These set (0) and set (1) each have a space of 512 bytes for registering data and a space for registering a part of the real address of the registered data (hereinafter,
It is divided into 128 bytes (called tag memory). Space for registering the above data is 3 by 16 bytes
It is divided into two spaces, and each space is called a block. Further, the tag memory is divided into 32 pieces of 4 bytes so as to correspond to each block, and each is called a tag memory entry (hereinafter, abbreviated as TME). This TME holds an address (hereinafter, referred to as a real address) <9-31> on the main memory in which data registered in the corresponding block is stored, and four TMEs included in the corresponding block are held. Valid flag <0 indicating that each of the sub-blocks is valid
-3> is also held. Also, the set (0) TME
Is a flag (hereinafter referred to as an LRU bit) indicating that the registration or output of the data of the corresponding block is performed more recently than the registration or output of the data of the block of the set (1) paired with it. Also holds.

An actual V80 access operation will be described with reference to FIGS. 11, 12, 13, 14, and 15.

FIG. 11 is a block diagram showing a system configuration of a conventional microprocessor. As shown in FIG. 11, in this conventional example, an instruction execution unit (hereinafter, EXU
101) and an execution address generation unit (hereinafter,
EAG) 102, instruction decode unit (hereinafter referred to as IDU) 104, access control unit (hereinafter referred to as ACU) 105, and data
Control unit (hereinafter referred to as DCU) 106
And a memory management unit (hereinafter referred to as MMU) 110
1, a DCHE 1102, and a main memory 108.

In FIG. 11, according to the instruction fetched from the main memory 108, the instruction is decoded in the IDU 104. Further, the virtual address calculated in the EAG 102 is input to the MMU 1101 via the internal virtual address bus 115. And MMU
In 1101, the virtual address is converted into a real address and output, and the real address is transferred to the ACU 105 for controlling the address bus 109 and the DCHE 1102 via the internal real address bus 116. In the ACU 105, when the real address is input and the cache hit signal 113 is inactive, the ACU 105 controls the address bus 109 and the control signal 111 to access the main memory. In the main memory 108, the accessed data is output and transferred to the DCU 106 via the data bus 110. In the DCU 106, the data from the main memory 108 is received and the internal data bus 1 is received.
14 and outputs to EXU101, IDU104 and DC
Transfer to HE1102. In the DCHE 1102, when the data is not registered in the DCHE 1102 and the cache registration inhibit signal 1103 is inactive, the data output from the DCU 106 to the internal data bus 114 is registered.

FIG. 15 shows the MMU 1101 in FIG.
6 is a diagram showing an outline of the operation of FIG. Of the 32-bit virtual address 501 sent via the internal virtual address bus 115 in FIG. 11, the upper 12 bits (bit 20 to
31) From the section and area ID 503, the address conversion data 509 (which stores the base address of the page table) in the address conversion table 508 (which is composed of the address conversion data) is selected,
The base address of page table 510 is specified. PTE1501 is the page ID of bits 12-19
Determined by 504. The real page number indicated by the PTE 1501 and the in-page offset 505 specify the real address 512 corresponding to the virtual address 501. This real address 512 is transferred to the ACU 105 which controls the address bus 109 via the internal real address bus 116 of FIG. Also, at this point, registration permission or registration prohibition information for the data cache is extracted from the DCHE inhibit 1301 of the PTE 1501 of FIG. 13, and the information is passed through the cache registration prohibition signal 1103 to the DCHE 1102.
Transfer to. The configuration inside the PTE 1501 is shown in FIG.
As shown in FIG. 13, the PTE 1501 is
It is composed of an inhibit 1301 and a real page number field 309 having a real address on the main memory of the page pointed to by the PTE 1501.

FIG. 12 is a block diagram of the DCHE 1102 of FIG. The real address <23-31> and the real address <2, 3> are input from the MMU 103 to the decoder 203 via the internal real address bus 116. In the decoder 203, the TME (0) 1204 and sub-block (0) 220 of the corresponding block (0) 218 from the set (0) 201 and the TME (of the corresponding block (1) 219 from the set (1) 202 are set. 1) 1205 and sub-block (1) 221 are selected. The selected TME (0) 1204 and TME (1) 1205 pass through the tag address bus (0) 233 and the tag address bus (1) 234, and then the comparator (0) (hereinafter, CM).
P (0) 204 and comparator (1) (hereinafter CM
A (9-31) is output to the P (1) 205. In addition, the cache bit is passed through the valid bit line (0) 231 and the valid bit line (1) 230.
For control block 1201, valid bit (0) 21 corresponding to the selected sub-block
6 and valid bit (1) 217 are output. In addition, TME (0) 1204 is routed through cache control block 120 via LRU bit line 230.
For 1, the state of the LRU bit 215 is output.

In CMP (0) 204, TMP
A <9-31> of (0) 1204 is the real address <9-3.
1>, the comparison result line (0) 226 is activated. In CMP (1) 205, T
A <9-31> of MP (1) 1205 is the real address <9
-31>, the comparison result line (1) 227 is activated. Also, the P of the page containing the data
The TE DCHE inhibit 1301 is output to the cache control block 1201 via the cache registration prohibition signal 1103. In the cache control block 1201, when the comparison result line (0) 226 and the valid bit (0) 216 are active, the data buffer 207 is controlled via the buffer control bus 222 and・
The data of the block (0) 220 is transferred to the internal data bus 11
4 and activate LRU bit 215. Further, when the comparison result line (1) 227 and the valid bit (1) 217 are active, the data buffer 2 is routed via the buffer control bus 222.
07 to cause the data contained in sub-block (1) 221 to be output to internal data bus 114, and LRU
Make bit 215 inactive. Further, when all of the comparison result line (0) 226 and the comparison result line (1) 227 and the cache registration prohibition signal 1103 are inactive, the cache control block 12
01 performs one of the following operations depending on the state of the LRU bit 215.

If LRU bit 215 is active, then LRU bit 215 is made inactive. Further, the real address <9-8> of the data is stored in the TME (0) corresponding to the selected sub-block of the block (1) 219, and the internal data bus 1 is transmitted from the DCU 106.
The data output to 14 is controlled by the buffer control
The data buffer 207 is controlled and stored via the bus 222, and in addition, TME (0) corresponding to the sub-block is stored.
Activate the valid bit of. In the following description, as described above, the real address <9− of the data is stored in TME (0) corresponding to the selected sub-block.
8>, the data output from the DCU 106 to the internal data bus 114 is stored, and in addition, the operation of activating the valid bit of TME (0) corresponding to the sub-block is simply performed by "registering data in sub-block". I will call it. " When the LRU bit 215 is inactive, the LRU bit 2159 is activated and the data is registered in the sub block (0) of the block (0) 218.

The internal structure of the TME is shown in FIG. As shown in FIG. 14, the TME has unused bits 1401, LRU bit 403 which indicates which of set (0) and set (1) was most recently registered or referenced,
VL <0-31> bit 404 indicating whether or not the subblock (0) to subblock (3) are valid, and A <9-31> which is the upper 23 bits of the real address of the data registered in the cache. 405.

[0018]

In the above-mentioned conventional high-performance microprocessor, when data having a low access frequency is registered in the cache and data having a high access frequency is expelled from the cache, Bit rate is reduced. In order to deal with this and improve the hit rate, the following measures are taken in the conventional microprocessor as described above.

That is, the first condition is that the page or the data spans a plurality of pages, and the number of data whose access frequency is obviously lower than that of other data is included, and the second condition is As a condition, when there is a page that meets the two conditions including that the page contains data that should not be registered in the cache, the information that prohibits the PTE from registering in the cache. Is added to prevent the data contained in those pages from being registered in the cache.

However, since the registration of the data in the cache is controlled only by prohibiting or permitting it, when the data that is accessed infrequently is accessed, the area in which the accessed data should be registered is empty. However, there is a drawback in that data that is not frequently accessed is not registered in the cache, and the hit rate of the cache is reduced accordingly.

Further, regardless of the data registered in the cache, since it is only possible to control whether or not the accessed data is registered in the cache, the data is registered in the cache when there is no free area. However, there is a drawback in that the data that is being accessed is evicted from the cache due to data that is accessed less frequently.

It is an object of the present invention to register data, even if the data is accessed infrequently, in a cache when the area for registering the data is empty, and when the area for registering the data is not empty. The purpose of the present invention is to provide a microprocessor which improves the bit rate by preventing the data registered in the cache from being evicted from the cache by the data that is less frequently accessed.

[0023]

A microprocessor of the first invention comprises a paging-type virtual memory management mechanism,
In a microprocessor with a built-in or externally connected cache memory that performs a wayset associative replacement by the LRU method, a higher value in the page table entry indicates that an instruction or data included in a page is more likely to be registered in the cache. When the value is minimum, bit information indicating that the data included in the page is prohibited from being registered in the cache memory (hereinafter referred to as IPT bit) is stored in the cache memory in set units. Has the IPC bit formed in accordance with a predetermined main memory, and the value of the IPT bit in the page table entry of the page including the data being accessed is the lowest value. Bit determining means for checking whether or not the cache N number of IP stored in memory
From the C bits, the bit selecting means for selecting the IPC bit with the lowest value, the IPC bit selected by the bit selecting means or the IPC bit selected by the predetermined LRU method, and the current IPT bit are compared and collated. Means for registering data in the cache memory according to the results of the bit determining means, the bit selecting means, and the bit comparing means, which are configured to be provided at least in the central processing unit, and which are indicated by the IPT bits. If the information does not prohibit registration of data in the cache memory, the selected IPC bit corresponds if the value of the IPT bit is higher than the value of the IPC bit selected by the bit selection means. IPC bit selected by the bit selecting means by registering data in the entry A low value of the IPT bits than the value, is characterized by IPC bit selected does not register the data in the corresponding entry.

The microprocessor of the second invention is a microprocessor which has a paging-type virtual memory management mechanism and a cache memory for performing N-way set associative replacement by the LRU system, which is built-in or externally connected. Indicates that the higher the value, the easier the instruction or data included in the page is registered in the cache, and when the value is the minimum, the data included in the page is prohibited from being registered in the cache memory. Bit information (hereinafter, referred to as IPT bit) indicating that is stored in the cache memory in units of set, and has an IPC bit formed, and is accessed corresponding to a predetermined main storage device. Page table of pages that contain data
The IPC bit with the lowest value is selected from the bit determination means for checking whether or not the value of the IPT bit in the entry is the lowest value and the N IPC bits stored in the cache memory. Bit selecting means, and the IPC selected by the bit selecting means
IPC selected by bit or predetermined LRU method
A bit comparing means for comparing and collating a bit with the current IPT bit, and means for registering data in the cache memory according to the results of the bit determining means, the bit selecting means and the bit comparing means are provided at least outside the central processing unit. If the information indicated by the IPT bit is not prohibited from being registered in the cache memory, the value of the IPT bit is higher than the value of the IPC bit selected by the bit selecting means. For example, the data is registered in the entry corresponding to the selected IPC bit, and the IP selected by the bit selecting means is registered.
If the value of the IPT bit is lower than the value of the C bit, data is not registered in the entry corresponding to the selected IPC bit.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of the first embodiment of the present invention. As shown in FIG. 1, in this embodiment, EXU 101, EAG 102, and IDU 1
04, ACU105, DCU106, MMU11
01, DCHE 1102, and main memory 108, and the system configuration is the same as the above-mentioned conventional example, but in the present embodiment, data with low access frequency is registered in the cache. By doing
A function is provided to prevent the hit rate of the cache from being lowered because the frequently accessed data is evicted from the cache. In addition to that function, even if the data is accessed infrequently, it can be registered in the cache when the area where the data should be registered is free, and the cache hit rate can be improved accordingly. Has been done.

In order to realize the above function, in this embodiment, as a first step of accessing, the virtual address is converted into a real address, and at the same time, the IPT bit of the page including the accessed data is checked. . Next, it is checked whether the accessed data is registered in the DCHE 1102. When registered, the DCHE 1102 is accessed to obtain data. When not registered in the DCHE 1102, the main memory 108 is accessed to obtain data. Then, the IPT of the page containing the obtained data
If the bit is not the lowest and there is an unused area in the registerable area where data can be registered,
The obtained data is registered in DCHE 1102. Further, the IPC bit included in each TME of the registrable area is the IPT of the page including the accessed data.
If it is the same as the bit or lower than the IPT bit, the obtained data is. Register with DCHE 1102.

Next, address conversion in this embodiment will be described.

The virtual address space of this embodiment is 4 Gbytes, and this space is divided into four 1 Gbytes, and each virtual address space is called a section. Each section is further divided into 1024 areas, and each area is called an area. Each of these areas has a size of 1 MB and is further divided into 2
It is divided into 56 pages. Each page has a size of 4 Kbytes. The address conversion in this embodiment is performed with reference to the address conversion data and PTE information. The address conversion data is the virtual address 2
It is arranged in the address conversion table so that it can be selected by bits 0 to 31. There is a one-to-one correspondence with areas. The page table is a table that exists one for each area, and its main storage 108
The base address above is specified by the address translation data corresponding to that area, and each entry is a PTE.

The DCHE of this embodiment will be described.

The DCHE 107 of this embodiment has a space of 1280 bytes, and the space is divided into two parts of 64 bytes, which are called set (0) and set (1). Each of set (0) and set (1) has 512 bytes of space to register data and tom memory 1
It is divided into 28 bytes. Furthermore, the space for registering data is divided into 32 pieces of 16 bytes each, and each is called a block. Then, the block is further divided into 4 bytes 4
It is divided into pieces and each is called a sub-block. Further, the tag memory is divided into 32 pieces by 4 bytes so as to correspond to each block, and each is called TME. This TME holds the real address <9-31> of the data registered in the corresponding block. Also, valid bits <0-3> indicating that each of the four sub-blocks included in the corresponding block is valid, I of the PTE of the page including the data registered in the block.
IPC bit <0, which copies the PT bit <0, 1>
1> is also held. In addition, the set (0) TME
Indicates that the registration or output of the data of the corresponding block is performed more recently than the registration or output of the data of the block of the set (1) with which the corresponding block is paired.
Holding a bit.

Regarding the actual access operation of this embodiment,
This will be described with reference to FIGS. 1, 2, 3, 4, and 5.

In FIG. 1, the instruction is decoded in the IDU 104 according to the instruction fetched from the main memory 108. Further, the virtual address calculated in the EAG 102 is input to the MMU 103 via the internal virtual address bus 115. And MMU10
3, the virtual address is converted into a real address and output, and the real address is converted into the internal real address bus 1
AC controlling the address bus 109 via 16
Transfer to U105 and DCHE107. Also, the IPT bit <0,1> of the PTE of the page including the data accessed this time is checked and transferred to the DCHE 107 via the cache registration level signal 112. DC
The HE 107 receives the real address, and when the data being accessed is registered in the DCHE 107, the registered data is transferred to the internal data.
Output to the bus 110. Also, the data is DCHE107.
Was registered in the cache hit signal 11
3 is activated and transferred to the ACU 105.

In the ACU 105, when the real address is input and the cache hit signal 113 is inactive, the address bus 109 and the control signal 111 are controlled to access the main memory 108. . In the main memory 108, the accessed data is output and transferred to the DCU 106 via the data bus 110. The DCU 106 receives data from the main memory 108 and sends the data via the internal data bus 114 to the EXU 101, I
Transfer to DU 104 and DCHE 107. DCHE
In 107, when the data is not registered in the DCHE 107, the registration level of the data registered in the DCHE 107 is compared with the registration level of the accessed data, and according to the result, the internal data from the DCU 106 The data output to the bus 114 is registered.

FIG. 5 is a diagram showing an outline of the operation of the MMU 103 in FIG. From the 32-bit virtual address 501 sent via the internal virtual address bus 115 in FIG. 1, the upper 12-bit section (bits 20 to 31) and the area ID 503 are used to calculate the address conversion table 5.
Address translation data 509 (which stores the base address of the page table) out of 08 (which is composed of address translation data) is selected,
The base address of table 510 is specified. PT
E511 is determined by the page ID 504 of bits 12-19. The virtual address 5 is determined by the real page number pointed to by this PTE 511 and the in-page offset 505.
The real address 512 corresponding to 01 is designated. This real address 512 is the internal real address bus 116 of FIG.
Through the ACU 105, which controls the address bus 109. Also, at this time, PTE5
The value of the IPT bit 305 of 11 is transferred to the DCHE 107 via the cache registration level signal 112. PT
The structure inside E511 is shown in FIG. As shown in FIG. 3, PTE 511 has IPT bit 305 and PT
It is composed of a real page number field 309 having a real address on the main memory 108 of the page pointed to by E511.

FIG. 2 is a block diagram of the DCHE 107 of FIG. The operation of the DCHE 107 will be described below with reference to FIG. The real address <23-31> and the real address <2, 3> are input from the MMU 103 to the decoder 203 via the internal real address bus 116. In the decoder 203, the TME (0) 213 and the sub-block (0) 220 of the corresponding block (0) 218 from the set (0) 201, and the TME (of the corresponding block (1) 219 from the set (1) 202. 1) 214 and sub-block (1) 221 are selected. Selected TME
(0) 213 and TME (1) 214 have a tag address bus (0) 233 and a tag address bus (1) 2
A <9-31> to the comparator (0) (hereinafter referred to as CMP (0)) 204 and the comparator (1) (hereinafter referred to as CMP (1)) 205 via 34. Is output. In addition, cache control via the valid bit line (0) 231 and the valid bit line (1) 232.
The valid bit (0) 216 and the valid bit (1) 217 corresponding to the selected sub-block are output to the block 206. And again the registration level
The cache control block 20 is routed through the bus (0) 228 and the registration level bus (1) 229.
The contents of the IPC bit stored in 6 are also output. In addition, TME (0) 213 is routed through cache control block 206 via LRU bit line 230.
, The state of the LRU bit 215 is output.

In CMP (0) 204, TME
A <9-31> of (0) 213 is the real address <9-3.
If it matches 1>, the comparison result line (0) 226 is activated. In CMP (1) 205,
A <9-31> of TME (1) 214 is real address <9
-31>, the comparison result line (1) 227 is activated. Also, the P of the page containing the data
The value of the IPT bit <0,1> of TE is output to the cache control block 206 via the cache registration level signal. Cache control
In block 206, when the comparison result line (0) 226 and the valid bit (0) 216 are active, the data buffer 207 is controlled via the buffer control bus 222, and the sub block (0) 22 is controlled.
0 data is output on the internal data bus 114 and the LRU bit 215 is activated. When the comparison result line (1) 227 and the valid bit (1) 217 are active, the data contained in the sub-block (1) 221 is transferred to the data buffer 207 via the buffer control bus 222. Controls to output on internal data bus 114 and deactivates LRU bit 215.

Further, in the cache control block 206, when both the comparison result line (0) 226 and the comparison result line (1) 227 are inactive and the value of the cache registration level signal is not the minimum value, the valid value is valid. Depending on the states of bit (0) 216 and valid bit (1) 217, one of the following operations (-) is executed. If valid bit 216 is inactive, then activate LRU bit 215. Also TM
The value of the cache registration level signal 112 is copied to the IPC bit of E (0) 213, and the data is registered in the sub-block of block (0) 218. If the valid bit 217 is inactive, the LRU bit 215 is made inactive. Further, the value of the cache registration level signal 112 is copied to the IPC bit of TME (1) 214, and the data is registered in the sub block of block (1) 219. If both valid bits 216 and 217 are inactive, then activate LRU bit 215. Also, the value of the cache registration level signal 112 is copied to the IPC bit of TME (0) 213, and the data is registered in the sub block of block (0) 218. If both valid bits 216 and 217 are active, the cache control block 206 causes the value of the IPC bit of TME (0) 213, the IPC bit of TME (1) 214 and the cache registration level signal 112 to be small or large. Check the relationship.

Then, the cache control block 206 causes the following operations (-1 to -1) depending on the magnitude relationship between the IPC bit of TME (0) 213, the IPC bit of TME (1) 214 and the value of the cache registration level signal 112. Execute one of -3). -1: The value of the cache registration level signal 112 is higher than the IPC bit value of TME (0) 213,
The IPC bit value of (0) 213 is TME (1) 214
LRU bit 2 if lower than the IPC bit value of
Activate 15. Also, the value of the cache registration level signal 112 is copied to the IPC bit of TME (0) 213, and the data is registered in the sub block of block (0) 218. -2, the value of the cache registration level signal 112 is higher than the IPC bit value of TME (1) 214,
(1) The IPC bit value of 214 is TME (0) 213
LRU bit 2 if lower than the IPC bit value of
Make 15 inactive. Also, TME (1) 21
The value of the cache registration level signal 112 is copied to the IPC bit of 4 and the data is registered in the sub block of the block (1) 219. -3: TME (0) 213 IPC bit and TM
The value of the cache registration level signal is higher than either of the IPC bits of E (1) 214 and I of TME (0) 213.
When the value of the PC bit and the value of the IPC bit of TME (1) 214 are the same, the LRU bit 2 of TME (0) 213
The following operations (-3-1 to -3-
Perform one of 2). 3-1: When the LAU bit 215 is active, make the LRU bit 215 inactive. Further, the value of the cache registration level signal 112 is copied to the IPC bit of TME (1) 214, and the block (1) 21
Data is registered in 9 sub-blocks. -3-2: When the LRU bit 215 is inactive, activate the LRU bit 215. Also, the value of the cache registration level signal 112 is copied to the IPC bit of TME (0) 213, and the block (0) 21
Data is registered in 8 sub-blocks.

In the cache control block 206, in the cases other than those mentioned above, the real address <9-8> of the data and the data output from the DCU 106 to the internal data bus 114 are registered. Not performed.

The internal structure of the TME is shown in FIG. As shown in FIG. 4, the TME indicates an unused bit 401, an IPC bit 402, an LRU indicating which of set (0) and set (1) was most recently registered or referenced.
Bit 403, VL <0-31> bit 404 indicating whether or not subblock (0) to subblock (3) are valid, and A <9 which is the upper 23 bits of the real address of the data registered in the cache. -31> 405.

FIG. 6 is a block diagram showing the system configuration of the second embodiment of the present invention. As shown in FIG. 6, in the present embodiment, the CPU 609, the MMU 601, and the DCHE
The memory 602 and the main memory 604 are provided, and the cache and the address translation mechanism are arranged outside the CPU 609. This embodiment is different from the first embodiment in that an IPT bit, an IPC bit, a cache control block and a cache registration level signal connecting them, a registration level bus (0), a registration level
The number of bits on the bus (1) is increasing. Also, the structure of the cache memory is changing. Since the number of bits is increased in this manner, the present embodiment can control the registration of data in the cache in more detail than the first embodiment described above.

Next, the DCHE of this embodiment will be described.

The DCHE 107 of this embodiment has a space of 1536 bytes, and the space is divided into two by 768 bytes, which are called set (0) and set (1). Each of set (0) and set (1) has 512 bytes of space for registering data and tag memory 2
It is divided into 56 bytes. Furthermore, the space for registering data is divided into 64 pieces of 8 bytes each, and each is called a block. Then, the block is further divided into two by 4 bytes and each is called a sub-block. Further, the tag memory is divided into 64 units of 4 bytes so as to correspond to each block, and each is referred to as TME. This TME holds the real address <9-31> of the data registered in the corresponding block. A valid bit <0-1> indicating that each of the two sub-blocks included in the corresponding block is valid, the PTE IP of the page including the data registered in the block
IPC bit <0-2> for copying T bit <0-2>
Also holds. In addition, the TME of set (0) indicates that the registration or output of the data of the corresponding block was performed more recently than the registration or output of the data of the block of set (1) with which it was paired. It holds the LRU bit.

In FIG. 6, according to the instruction fetched from the main memory 604, the CPU 609 sends the virtual address to the MMU 601 via the virtual address bus 610.
Transfer to. The MMU 601 converts the virtual address into a real address and outputs the real address.
Main memory 604 and D via real address bus 605
Transfer to CHE602. Also, the IPT bits of the PTE of the page containing the data accessed this time <0, 1, 2>
Check the cache registration level signal 60
3 to DCHE 602. DCHE602
, When the real address is received and the data being accessed is registered in DCHE602,
The registered data is output to the data bus 606. Further, the fact that the data has been registered in the DCHE 602 is transferred to the MMU 601 by activating the cache hit signal 608.

In the MMU 601, when the cache hit signal 608 is inactive, the access to the main memory 604 is executed via the control signal 607. In the main memory 604, the accessed data is output and the CPU 60 is output via the data bus 606.
9 and DCHE 602. In the DCHE 602, when the data is not registered in the DCHE 602, the registration level of the data registered in the DCHE 602 is compared with the registration level of the accessed data, and the data bus 606 corresponding to the result is compared. Register the data output to.

FIG. 10 is a diagram showing an outline of the operation of the MMU 601 in FIG. Comparing with the case of the first embodiment of FIG. 1, it can be seen that the PTE 511 is changed to the PTE 1001. Regarding the operation,
This is the same as the case of the above embodiment, and the description thereof will be omitted. P
The configuration inside the TE 1001 is shown in FIG. PTE is I
PT bit 801, main memory 604 of page pointed to by PTE
It is composed of a real page number field 309 having the real address above. Compared to the case of the first embodiment, TME (0) 213 to TME
(0) 704, TME (1) 213 to TME (1)
705, tag memory (0) 211 to tag memory (0) 702, tag memory (1) 212 to tag memory
The memory (1) 703 has changed. Also,
The block (0) 218 and the block (1) 219 configured by four sub blocks are changed to the block (0) 708 and the block (1) 709 configured by two sub blocks. A decoder 203 that decodes the real address <23-32> and the real address <2-3> to select a block and a sub block
However, it is changed to a decoder 710 which decodes the real address <22-3> and the real address <2> and selects a block and a sub block. Also, the internal real address bus 1
16, internal data bus 114 and cache hit signal 113 are the real address bus 605, data bus 606 and cache hit signal 608, respectively.
Has changed to. In addition, registration level bus (0) 228
Registered level bus (0) 7 increased by 1 bit
The number of bits of the registration level bus (1) 229 is increased by 1 bit and changed to the registration level bus (1) 707. In addition, the cache control block 701 is the cache control block 2
06, a circuit for checking the magnitude relationship among the value of the registration level bus (0), the value of the registration level bus (1) and the value of the cache registration level signal, and that the value of the cache registration level signal is the lowest. It is formed as a circuit in which the number of bits of the circuit to be checked is increased by 1 bit.

The DCHE 602 in this embodiment is used.
Is the real address <22-31> and the real address <2>,
The operation other than the input from the MMU 103 to the decoder 710 via the real address bus 605 is the same as the operation of the DCHE 107 of the first embodiment shown in FIG. Further, the internal structure of the TME in this embodiment is as shown in FIG. 9, and the number of IPC bits 402 is increased as compared with the first embodiment, and the IP
It has changed to C bit 901. In addition, the number of bits of the valid bit 404 is reduced by 2 bits and changed to the valid bit 903.

[0049]

As described above, according to the present invention, when the area for registering the data has a free space, even if the data is accessed infrequently, the cache registration can be performed. There is an effect that can improve.

The data registered in the cache controls whether or not the data to be accessed can be registered. As a result, when the data registration area is not empty, the data registered in the cache is Data that is less frequently accessed than that can be prevented from being evicted from the cache, and the hit rate can be improved accordingly.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a built-in cache of the first embodiment.

FIG. 3 is an information structure diagram inside the PTE of the first embodiment.

FIG. 4 is an information structure diagram inside the TME of the first embodiment.

FIG. 5 is a schematic diagram of address translation of the first embodiment.

FIG. 6 is a system configuration diagram showing a second embodiment of the present invention.

FIG. 7 is a configuration diagram showing a built-in cache of the second embodiment.

FIG. 8 is an information structure diagram inside the PTE of the second embodiment.

FIG. 9 is an information structure diagram inside the TME of the second embodiment.

FIG. 10 is a schematic diagram of address conversion in the second embodiment.

FIG. 11 is a system configuration diagram showing a conventional example (V80).

FIG. 12 is a configuration diagram showing a built-in cache of the conventional example.

FIG. 13 is an information structure diagram inside the PTE of the conventional example.

FIG. 14 is an information structure diagram inside the TME of the conventional example.

FIG. 15 is a schematic diagram of address conversion in the conventional example.

[Explanation of symbols]

101 instruction unit 102 EAG 103, 601, 1101 MMU 104 IDU 105 ACU 106 DCU 107, 602, 1102 DCHE 108, 604 main memory 109 address bus 110 data bus 111, 607 control signal 112, 603 cache registration level signal 113, 608 cache hit signal 114 internal data bus 115 internal virtual address bus 116 internal real address bus 201 set (0) 202 set (1) 203 decoder 204 comparator (0) 205 comparator (1) 206, 701, 1201 cache control block 207 data buffer 211, 702, 1202 tag memory (0) 212, 703, 1203 tag memory (1) 213, 704, 1204 ME (0) 214, 705, 1205 TME (1) 215, 403 LRU bit 216 Valid bit (0) 217 Valid bit (1) 218, 708 block (0) 219, 709 block (1) 220 Sub block (0) 221 Subblock (1) 222 Buffer control bus 226 Comparison result line (0) 227 Comparison result line (1) 228, 706 Registration level bus (0) 229, 707 Registration level bus (1) 230 LRU bit line 231 Valid bit line (0) 232 Valid bit line (1) 233 Tag address bus (0) 234 Tag address bus (1) 305, 801 IPT bit 309 Real page number field 401, 902, 904, 1401 Unused bit 402, 901 IPC Bit 404, 903 VL bit 405 A <31-9> 501 virtual address 503 section and area ID 504 page ID 505 in-page offset 508 address translation table 509 address translation data 510 page table 511, 1001, 1501 PTE 512 real address 605 Real address bus 606 Data bus 609 CPU 610 Virtual address bus 710 Decoder 1103 Cache registration inhibit signal 1301 DCHE inhibit

Claims (2)

[Claims] 1. A paging-type virtual memory management mechanism,
N (Positive integer) In a microprocessor that has internal or external cache memory that performs replacement by the LRU method with wayset associative, the higher the value in the page table entry, the easier the instruction or data included in the page is registered in the cache. Bit information (hereinafter referred to as an IPT bit) indicating that the data included in the page is prohibited from being registered in the cache memory when the value is the minimum, in units of sets. It has an IPC bit stored and formed in the cache memory, and the value of the IPT bit in the page table entry of the page containing the data being accessed corresponds to a predetermined main memory device, A bit determining means for checking whether the value is the lowest, The bit selecting means for selecting the IPC bit having the lowest value from the N IPC bits stored in the cache memory, and the IPC bit selected by the bit selecting means or a predetermined LRU method. IPC bit,
A bit comparison means for comparing and collating the current IPT bit, and a means for registering data in the cache memory according to the results of the bit determination means, bit selection means and bit comparison means are provided at least in the central processing unit. And said I
If registration of data in the cache memory is not prohibited by the information indicated by the PT bit, if the value of the IPT bit is higher than the value of the IPC bit selected by the bit selecting means, the selected IPC Data is registered in the entry corresponding to the bit, and if the value of the IPT bit is lower than the value of the IPC bit selected by the bit selecting means, the data is not registered in the entry corresponding to the selected IPC bit. And a microprocessor. 2. A paging-type virtual memory management mechanism,
In a microprocessor with a built-in or external cache memory that performs N-way set associative replacement by the LRU method, it is shown that the higher the value in the page table entry, the easier the instruction or data included in the page is registered in the cache. , Bit information (hereinafter referred to as an IPT bit) indicating that the data included in the page is prohibited from being registered in the cache memory when the value is the minimum in the cache memory. It has an IPC bit formed by storing, and the value of the IPT bit in the page table entry of the page containing the data being accessed is the lowest value corresponding to the predetermined main memory. A bit determining means for checking whether or not there is any; Address selection means for selecting the IPC bit with the lowest value from the N IPC bits stored in the memory, and the IPC bit selected by the bit selection means or the IPC bit selected by a predetermined LRU method. When,
A bit comparing means for comparing and collating the current IPT bit, and a means for registering data in the cache memory according to the results of the bit determining means, bit selecting means and bit comparing means are provided at least outside the central processing unit. And said I
If registration of data in the cache memory is not prohibited by the information indicated by the PT bit, if the value of the IPT bit is higher than the value of the IPC bit selected by the bit selecting means, the selected IPC Data is registered in the entry corresponding to the bit, and if the value of the IPT bit is lower than the value of the IPC bit selected by the bit selecting means, the data is not registered in the entry corresponding to the selected IPC bit. And a microprocessor.