JPH07200352A - Data processor, program translation method and debug tool - Google Patents

Abstract

PURPOSE:To trace and acquire a parameter transfered for a subroutine call in a program described in a high class language with a real time trace function of an emulator. CONSTITUTION:A data processor 1 has an instruction set comprising a usual instruction and a debug instruction whose instruction code only differs from that of the usual instruction. For example, the debug instruction is used for a data transfer instruction to transfer a parameter to a subroutine. The data processor 1 uses a debug instruction analysis section 11 to analyze the debug instruction and makes the same operation as that of the corresponding usual instruction. The parameter or the like is traced and acquired by using the emulator recognizing the debug instruction and tracing the execution process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for making it possible to verify a parameter passed at the time of a subroutine call in a program written in a high-level language. The present invention relates to a realized program translation method and a debugging tool such as an emulator. In this specification, a data processor is a CPU (central
Processing unit)), microprocessor,
It is positioned as a generic concept including a one-chip microcomputer.

[0002]

2. Description of the Related Art In a large-scale computer, an information output device such as a printer or a console is already prepared as a peripheral device, so that information necessary for program debugging is output to these information output devices. There is. For example, as a method for debugging a program written in a high-level language, parameters (function arguments, etc.) are output to an information output device at the time of a subroutine call, and parameters are compiled at the time of compiling the source file. There has been proposed a method of inserting a sentence for outputting the information to the information output device.

On the other hand, in program debugging in embedded equipment such as industrial equipment and household electric appliances in which a data processor or a microcomputer is incorporated as a control circuit, debugging of a debugger or an input / output device for debugging is performed on the embedded equipment. It is difficult to prepare a working environment. Therefore, the emulator is used. The emulator has an emulation microcomputer having at least the same control function as the microcomputer mounted on the embedded device to be debugged,
The emulation microcomputer actually executes the control of the embedded device while executing the debug target program. In the process of this proxy control, various information such as data and addresses input / output from the emulation microcomputer is stored in the trace memory,
The contents of the trace memory can be analyzed and provided for each required breakpoint to support program debugging and system debugging. Therefore, by using this emulator, the history of memory access and the like can be acquired through the trace function. For example, memory addresses and data are stored in the trace memory in bus cycle units, and the history of memory access can be determined by referring to the data corresponding to the thus stored information as an address.

As described above, in the emulator, due to the nature of debugging based on the trace information obtained by actually operating the embedded device, the debugging operation requires real-time operation with respect to the operation of the embedded device.

As an example of a document describing the emulator, "Microcomputer Handbook" No. 58, published by Ohm Co., Ltd. on December 25, 1985
There are pages 0 to 584.

[0006]

In recent years, there have been increasing examples of using a high-level language such as a C language for hardware and software for controlling embedded devices, and tracing of an emulator for such embedded devices. It is possible to obtain the history of memory access by a function for a variable with a known address.
It is not possible for variables whose addresses change (parameters and local variables at the time of subroutine call). Because, when calling a subroutine on a program written in a high-level language such as C language and passing parameters, the variables in the stack area are used in C language. Since the position of the stack pointer changes depending on how the subroutine is called, the value of the stack pointer (and the address of the local variable) at the beginning of the same subroutine is not always constant when focusing on a certain subroutine. is there. For example, in the data area assigned to the address space in FIG. 9, the global variable area has a fixed variable address, but the stack and local variable areas are not constant because the variable address is determined relative to the stack pointer. . 10A, that is, the program A calls the program B, and the program C is further called in the program B, and FIG. 10B, that is, the program A directly calls the program C. Comparing with the case, the value of the stack pointer in each case is shown in FIG.
Are different as shown in.

As described above, in debugging an embedded device equipped with a data processor for executing a program generated by using a high-level language such as C language, a subroutine call in a program written in a high-level language is required. It is impossible to trace the parameters passed to the emulator by the real-time trace function of the emulator. Even so, even if a debugging method in a large-scale computer system is adopted for debugging embedded devices, the debugging environment is not set up, and a special parameter is output for debugging using an emulator that requires real-time performance for embedded device operation. You cannot insert a sentence or description.

An object of the present invention is to enable a parameter or a local variable passed at the time of a subroutine call in a program written in a high-level language to be trace-acquired by a real-time trace function of a debugging tool such as an emulator. To provide. That is, the present invention provides a data processor, a program translation method realized by a compiler and the like, and a debugging tool such as an emulator for enabling the above.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

[1] Debugging instructions are adopted in order not to impair the real-time property that the operation of the embedded device requires real-time property for the operation of debugging. That is, the debug instruction is added to the instruction set of the data processor. The added instruction has the following features. (A) The debug instruction includes a normal instruction that is paired with the debug instruction. (B) The only difference between the normal instruction and the debug instruction, which are paired, is the instruction code, and the instruction word length, the size and arrangement of the operands, the operation, the number of instruction execution cycles, etc. are the same. Absent.

[2] The invention having a point of view as means for generating the above-mentioned debugging instruction focuses on a program translation method such as a compiler (and a debugger). To have. (2-a) The invention for automatically generating instructions for debugging recognizes a specific portion in the description of the source program and facilitates the debugging when the program is translated, such as compiling, to facilitate debugging. Generates an instruction code for debugging instead of a normal instruction code. For example, the portion of the subroutine call and the location of the data transfer instruction for passing the parameter are recognized, the jump subroutine instruction and the move instruction of the portion are replaced with the debug jump subroutine instruction and the debug move instruction, and the code is generated. (2-b) In the invention which deals with by generating debug information in place of the debug instruction, instead of generating the debug instruction code in 2-a, information indicating the position is generated as debug information. . For example, the portion of the subroutine call and the location of the data transfer instruction for passing the parameter are recognized, and the information indicating the positions of the jump subroutine instruction and the move instruction of the portion is generated as debug information. The generation of the instruction code for debugging, which was performed by the compiler in 2-a above, refers to the debug information by the software for debugging (for example, the software of the emulator), and the instruction code for debugging is changed from the normal instruction code. Replace with.

[3] In the invention focused on a debug tool such as an emulator for a data processor having the above-mentioned debug instruction as an instruction set, the debug tool has the following functions. (3-a) When the program translation method of 2-a is adopted, the trace circuit has a function of recognizing the debug instruction, and a function of acquiring the instruction execution result of only a portion necessary for debugging by tracing. Have. For example, it has a function of recognizing a debug jump subroutine instruction and a debug move instruction, and a function of obtaining a trace of a debug jump subroutine instruction, a debug move instruction, and a necessary peripheral instruction execution result at the time of the subroutine call. In addition, the debug tool has a function to edit and display the trace results. (3-b) When the program translation method of 2-b is adopted, the debug tool has the following functions in addition to the functions of 3-a. That is, the debug tool has a function of replacing a necessary part of the instruction with the debug instruction based on the debug information. For example, it has a function of replacing a jump subroutine instruction and a move instruction during a subroutine call with a debug jump subroutine instruction and a debug move instruction.

[0014]

[Action]

[1] Adding the above-mentioned debugging instruction to the instruction set of the data processor means that in an embedded device using such a data processor, a program composed of only ordinary instructions and a part of the program are instructions for debugging. It is guaranteed that there is no difference in the size, configuration and operation of the program with the program replaced by. This acts so as not to impair the real-time property required for a debug tool that assists in debugging while controlling the target device on behalf. Further, it works so that a debug tool such as an emulator can easily distinguish a normal instruction and a debug instruction during program execution. As a result, by using the debug tool that has the function of recognizing the above debug instruction and tracing the execution process, the parameters and local variables passed at the time of the subroutine call in the program written in the high-level language can be , The real-time trace function of the emulator can be used to acquire traces, enabling debugging focusing on such parameters and local variables.

[2] The program translation method for automatically generating the debug instruction simply generates a machine language program for a data processor having an architecture including the debug instruction in an instruction set. The program translation method for generating the debug information instead of the debug instruction suppresses an increase in the size of the machine language program due to the information used only for debugging.

[3] A debug tool that has a function of recognizing a debug instruction and traces the execution process of the instruction uses parameters and local variables passed at the time of a subroutine call in a program written in a high-level language. It is possible to debug by acquiring with a trace circuit and focusing on such parameters and local variables. Debug tools that operate by receiving debug instructions directly have a physical scale larger than that of a debug tool that has a function to replace necessary parts of instructions with debug instructions based on debug information generated by a compiler. To reduce. The latter debugging tool enables debugging focusing on parameters and local variables by using the debugging instruction even when there is not enough undefined code that can be assigned to the debugging instruction.

[0017]

[Embodiment] An embodiment of the present invention [1] a data processor,
The items will be sequentially described in accordance with items of [2] compiler and [3] emulator. [1] Data Processor [1-a] Debug Instruction The data processor of this embodiment has a debug instruction in its instruction set. The debug instruction has the features (1) and (2). (1) The debug instruction has a normal instruction paired with it. (2) The difference between the normal paired instruction and the debugging instruction is only the instruction code, and the instruction word length, the size and arrangement of the operands, the operation, the number of instruction execution cycles, etc. are not different between the two.

A description will be given of a case where a debug data transfer instruction (also referred to as a DBGMOV instruction) and a debug jump subroutine instruction (also referred to as a DBGJSR instruction) are added to the instruction set as debugging instructions.

The data processor uses the data transfer instruction MOV.
And the jump subroutine instruction JSR, the DBGMOV instruction and the DBGJSR instruction are added as the corresponding debugging instructions.

The DBGMOV instruction is a data transfer instruction MO.
This instruction is the same as V. The instruction word length, the size and arrangement of the operands are the same, and only the instruction code (and the corresponding instruction mnemonic) is different. Both are exactly the same in terms of the operation of the data processor. An example of the instruction mnemonic and instruction code (machine language code) of the MOV instruction and the DBGMOV instruction is as follows. (MOV instruction) Instruction mnemonic; MOV. W Rx, @ (yy,
Rz) instruction code; 1234xxxxxxxxx (DBGMOV instruction) instruction mnemonic; DBGMOV. W Rx, @ (yy,
Rz) instruction code; 1A34xxxxxxxxxx

The DBGJSR instruction is an instruction that operates in the same manner as the jump subroutine instruction JSR. The instruction word length, the operand size and arrangement are the same, and only the instruction code (and the corresponding instruction mnemonic) are different. Both are exactly the same in terms of the operation of the data processor. An example of instruction mnemonics and instruction codes (machine language code) of the JSR instruction and the DBGJSR instruction are shown below. (JSR instruction) Instruction mnemonic; JSR @xxxxxxxxx instruction code; 5678xxxxxxxxx (DBGJSR instruction) Instruction mnemonic; DBGJSR @xxxxxxxxx instruction code; 5E78xxxxxxxxxx

[1-b] Configuration of Data Processor FIG. 1 shows the configuration of the data processor 1 in which the debug instruction is added to the instruction set, focusing on the instruction analysis unit and the instruction execution control unit. The instruction analysis unit 10 is a circuit portion that analyzes an instruction by a microprogram or hardware, and a debugging instruction analysis unit 11 configured by a program or hardware for analyzing a debugging instruction is added to this portion. Has been done. When executing the instruction for debugging, the instruction execution control unit 20 operates in the same manner as the execution of a normal instruction paired with the instruction for debugging. Paying attention to this, even if the data processor 1 shown in FIG. 9A can execute a debugging instruction, no special hardware is added to the instruction execution control unit 20. The instruction execution control unit 20 uses control signals obtained by the instruction analysis units 10 and 11 such as an execution unit having an arithmetic circuit such as an arithmetic and logic unit, a general-purpose register or various dedicated registers, a memory control unit, and a cache memory. It is composed of various circuits for executing instructions based on the above.
In the present invention, the specific configuration of such a general circuit is not limited at all.

Although details will be described in the section of the emulator, in order to simplify the hardware configuration of the emulator, a status signal such as a status signal for distinguishing execution of a debugging instruction from execution of a normal instruction. It is effective to add the output function of 3 to the data processor 1. In consideration of this, the data processor 1 shown in FIG. 1B has the hardware of the instruction execution control unit 20 as follows.
An output control circuit 21 for the status signal 3 is added. The output control circuit 21 includes a debug instruction analysis unit 1
1 outputs the status signal 3 as a first logical value based on a signal obtained by analyzing the operation code of the debug instruction, and otherwise outputs a second logical value.

When the data processor creates an instruction set that defines the positions of the bits that do not decode the instruction code, and the emulator distinguishes the normal instruction from the debugging instruction by the bits that do not decode, the data processor is changed. Is unnecessary.

[2] Compiler A compiler compatible with the data processor 1 will be described. [2-a] Generation of Instructions for Debugging To facilitate debugging at the time of subsequent debugging at the time of compilation, the compiler recognizes a specific portion, and the necessary portion is not a normal instruction code but an instruction for debugging. Generate code. For example, the compiler recognizes the portion of the subroutine call and the data transfer instruction for passing parameters when compiling, and replaces the JSR instruction and MOV instruction of the portion with the DBGJSR instruction and the DBGMOV instruction to generate the code.
For example, when the description of / * SUBROUTINE CALL * / sbrtn (a); is matched in the program written in C language, the compiler which does not consider the above-mentioned debugging instruction is usually xx xx MOV. Generate the code W Rx, @ (yy, Rz) xx JSR _sbrtn xx xx. On the other hand, when the compiler in this embodiment considering the above debug instruction recognizes the subroutine call (the subroutine call in the C language is easily recognized because it is indicated by the character string and the following () and;), For this part, xx xx DBGMOV. The code W Rx, @ (yy, Rz) xx DBGJSR_sbrtn xx xx is generated. In the above description, the mnemonic is used instead of the generated code for convenience, but it goes without saying that the finally generated code is a numerical code in machine language. Although it is written that the compiler generates the code, it goes without saying that the code may be generated in combination with an assembler, a linker, etc. depending on the configuration of the cross software system. It should be understood that xx above means an appropriate code.
The compiler is implemented by being applied to a data processing system such as an engineering workstation.

FIG. 2 shows an example of the processing procedure by the compiler of this embodiment. The compiler sequentially determines which instruction corresponds to each description line with respect to the description of the source file described in a high-level language such as C language, and when there is a corresponding instruction, the instruction is corresponded to. Generate the machine language code. For example, focusing on the compilation of the xx instruction and the yy instruction included in the instruction set of the data processor 1, as shown in FIG. 2, it corresponds to the xx instruction for the current processing target description line of the source file. There are a source description description determination step S1 and a source description correspondence determination step S3 corresponding to the yy instruction. The compiler of the present embodiment is added with a function of compiling the above-mentioned debug instruction.
Step S2 of determining whether the source description corresponds to the V instruction
Has been added. When an instruction corresponding to the source description exists (when YES is determined in any of steps S1, S2, and S3 above), a machine language code corresponding to the instruction is generated (steps S10, S20,
S30). When the instruction corresponding to the source description exists and is translated into the machine language code, the processing for the next instruction, that is, the processing for the next description of the source file is performed. Such processing is performed for all the description lines of the source file. In FIG. 2, steps S2 and S20 are representatively shown as the processing corresponding to the debug instruction.
Processing for other debugging instructions, such as SR instructions, is included in a number of similar processing steps that will be present before step S1 or in a number of similar processing steps that will be present after step S3. I want you to understand.

[2-b] Generation of Debug Information Instead of Generation of Debug Instruction Although the above-mentioned compiler directly generates the debug instruction, the compiler according to another embodiment is such that the compiler selects a specific portion. It recognizes and generates information indicating the position of the necessary part as debug information. The debug information is used as information for facilitating debugging at the time of debugging, and is not particularly limited, but it is physically separated from the machine language instruction code to be executed by the data processor. For example, the compiler recognizes a portion of a subroutine call and a data transfer instruction for passing a parameter at the time of compilation, and generates information indicating the positions of the JSR instruction and the MOV instruction of the portion as debug information. Such debug information is referred to by the software of the emulator, which will be described later in the section of the emulator, and the DBGJSR instruction and the DB executed by the compiler of the above-described embodiment by such software are referred to.
Replacement with the GMOV instruction is performed. If the contents of the debug information file include, for example, the addresses of debugging instructions recorded in order, the replacement of instructions is easy.

[3] Emulator An embodiment of an emulator as a debug tool used for system debugging or program debugging of an embedded device equipped with the data processor 1 of the above embodiment will be described.

FIG. 3 is a block diagram showing the entire debug tool. The emulator 4 shown in FIG.
A function of a target microcomputer which is connected between a host system 5 such as a parent computer and a microcomputer system (also referred to as a target system) 6 as an embedded device to be debugged and which should originally control the target system 6. While acting as a substitute, it has a function as a debugger and supports detailed system evaluation and program debugging. The host system 5 and the emulator 4 are connected by a serial line 7, for example. The target system 6 and the emulator 4 are connected by an interface cable 8. That is, by connecting the tip of the interface cable 8 to the target microcomputer socket 61 of the target system 6, the emulator 4 is connected to the target system 6.
Control on behalf of. The emulator 4 and the host system 5 constitute a debug tool.

The emulator 4 is not particularly limited, but controls the entire emulator such as the emulation data processor 40 for substituting the function of the target microcomputer which should originally control the target system 6 and the condition setting for emulation. A control data processor 41 for controlling is provided. The emulation data processor 40 is coupled to an emulation bus 42, the control data processor 41 is coupled to a control bus 43, and both buses 42 and 43 have emulation control circuits 44,
The break control circuit 45, the trace circuit 46, and the proxy memory circuit 47 are connected to each other. The emulation data processor 40 executes a target program developed for the target system 6 or under development to control the target system 6 on behalf of the target system 6.
Various bus information such as addresses and data exchanged with the target system 6 and control signals are also given to the emulation bus 42. The information provided in this way is traced by the trace circuit 46 according to the bus cycle of the emulation data processor 40, for example.
Traced to. Further, the break control circuit 45 monitors the state of the emulation bus 42, and when the preset state is reached, the emulation operation is stopped. The proxy memory circuit 47 is used as a storage area for supplementing a memory not yet prepared in the target system 6 and a storage area for a target program. The control data processor 41 performs setting of various conditions such as setting of break conditions for the break control circuit 45, setting of a trace start address for the trace circuit 46, and initial setting via the control bus 43. In a state where the emulation operation is stopped by the break control circuit 45, the trace information held by the trace circuit 46 is read by the control data processor 41 and the host interface 48.
Through the host system 5. The host system 5 supports debugging by displaying the transferred trace information and analyzing it.

FIG. 4 shows an example of the trace circuit 46. The trace circuit 46 shown in the figure is a trace condition determination circuit 4 that controls writing to the trace memory based on addresses, data, and other data processor information (for example, status information and access control signals).
60, and a trace memory 461 that stores information as required based on its control. The trace circuit 46 analyzes the operation of the data processor in consideration of the instruction prefetch by the data processor.
2 and an instruction analysis circuit 463. Address, data, and other data processor information are information of the emulation bus 42, and are basically equivalent to information exchanged between the emulation data processor 40 and the target system 6 via the interface cable 8. .

The instruction analysis circuit 463 analyzes whether or not the data processor 40 has fetched a debug instruction. The instruction analysis circuit 463 can recognize the debug instruction from the status information of the data processor 40 indicating the instruction fetch and the instruction code. As described with reference to FIG. 1B, when the data processor outputs the status signal 3 for distinguishing the debugging instruction from the normal instruction, the status signal can be used to recognize the fetching of the debugging instruction. Good. Upon recognizing the debug instruction, the instruction analysis circuit 463 controls writing of the debug instruction on the emulation bus 42 to the trace memory 461. The PC tracking circuit 462 monitors whether or not the prefetched instruction is executed. For the control, for example, a status signal indicating that the prefetched instruction has been supplied to the decode circuit and a status signal indicating that the prefetched branch destination instruction is not executed are received from the data processor 40 for determination. For example, the PC tracking circuit 462
When the prefetched debug instruction is executed, the write control is performed on the trace memory 461 so as to store the parameter transferred in the bus cycle activated by the prefetched instruction in the trace memory 461. As described above, the trace circuit 46 has a function of acquiring traces of the instruction fetch cycle for debugging and its execution cycle.

When the compiler generates the debug information, the debug tool including the emulator needs a function of replacing a necessary part of the instruction with the debug instruction based on the debug information generated by the compiler.
This function can be realized by the host system 5 when the host system 5 downloads the program to be verified by the emulator. Alternatively, the control processor 41 of the emulator 4 may be used.

In FIG. 5, the data processor is the DBG.
An example of a timing chart showing a state of trace acquisition when the MOV instruction is executed is shown. Here, DB
Execution of GMOV instruction causes data d to address cccc
A case where writing of ddd is performed will be schematically described.
First, the data processors 1 and 40 start the DBGMOV instruction starting from the address aaaa (first operation code of instruction code = 1a34, second operation code = xx).
xx) is fetched. Emulator instruction analysis circuit 4
63 recognizes that the DBGMOV instruction is fetched, and instructs the trace memory 461 to write the instruction to be fetched. The instruction analysis circuit 463 determines whether the information on the data bus input thereto is instruction information or other data information based on the LIR signal which is a kind of status signal output from the data processor. To do. The LIR signal is a signal indicating that the data processor is fetching the head of an instruction due to its low level. Then the PC tracking circuit 462
When the execution of this instruction is confirmed, the trace memory 461 is instructed to acquire the data of the data transfer cycle (writing of the data dddd to the cccc address). In the case of a data processor that performs instruction prefetch, the prefetched instruction may not be executed. The PC tracking circuit 462 identifies whether or not the prefetched instruction is actually executed by the LID signal. The LID signal is
This signal indicates that the data processor has transferred the prefetched instruction to the instruction decoder.

The data processor 40 outputs a status signal indicating that the debugging instruction has been executed, or a status signal indicating that the debugging instruction has been fetched and a status signal indicating that the fetched debugging instruction has been executed. When outputting, the instruction analysis circuit 463 and the PC tracking circuit 462 of the emulator are unnecessary, and the status signal analysis circuit is placed instead. In this case, it is not necessary to analyze the complicated instruction code and operation of the data processor, so that the physical circuit scale of the emulator can be reduced. Each of the above status signals is an example of the status signal 3 described in FIG.

After the trace acquisition is completed, the emulator or the host system analyzes and displays the contents of the trace memory. Taking the execution result of the DBGMOV instruction of FIG. 5 as an example, the contents of the trace memory are as shown in FIG. When the contents of (A) of FIG. 6 are organized and displayed, it is as shown in (B) of FIG. Also, although not explained in the example of trace acquisition, this is further described in DBG.
When displayed in combination with the JSR command, it becomes as shown in FIG. If this is displayed in a high-level language description, it will be as shown in FIG.

The compiler is not a debug instruction,
The operation of the emulator when the position of the debug instruction is generated as the debug information is as follows. First,
Download program and debug information. Next, the instruction of the address designated by the debug information (adding address information designated by the user in the emulator command if necessary) is replaced with the code of the debug instruction. Then run the program, get the trace,
Then display. The operation of this part is as described above. If necessary, the user may instruct another address information with an emulator command, replace the instruction again, execute the program, and acquire the trace.

Next, the trace acquisition timing when the data processor 40 performs prefetch will be described in more detail with reference to FIGS. 7 and 8. Here, the prefetch queue is one stage, and when prefetching the instruction following the conditional branch instruction, both the instruction at the address next to the conditional branch instruction and the instruction at the branch destination are prefetched in this order. . In this example, the conditional branch instruction (Bcc,
In this example, a BEGM instruction) is followed by a DBGMOV instruction, and when this is executed, it is assumed that the data dddd is written to the cccc address (for example, parameter transfer). That is, attention is paid to the instruction description shown in FIG. At this time, the data processor 40
Outputs a LIR signal, a LID signal, and a BCB signal as a status signal, and the emulator 4 outputs the signal LI
The execution of the prefetched instruction is monitored based on R, LID, and BCB. The LIR signal is sent to the data processor 40.
Is a signal indicating that the beginning of the instruction is being fetched. It is not output in the data transfer cycle. The emulator uses the LI to identify whether the information on the data bus input to this is command information or other data information.
The R signal is used. The LID signal is sent to the data processor 4
An instruction decoder that prefetches 0 (included in the instruction analysis unit 10 and the debug instruction analysis unit 11 in FIG. 1)
Is a signal indicating that it has been transferred to. In the case of the data processor 40 that performs instruction prefetch, the prefetched instruction may not be executed. The emulator 4 determines whether the prefetched instruction is actually executed.
It is identified by the D signal and the BCB signal. The BCB signal is a signal indicating that the branch instruction such as the conditional branch instruction prefetched by the data processor 40 is not executed.

FIG. 7 shows a timing chart when the branch destination instruction (the instruction at the address zzz) in the BEQ instruction is not executed under the above conditions. First, the data processor prefetches the BEQ instruction and then prefetches the DBGMOV instruction starting from the address aaa. The instruction analysis circuit 463 of the emulator 4 recognizes the prefetch of the DBGMOV instruction by using the LIR signal. At this time, the trace memory 461 is instructed to acquire the trace (write information such as data and address). Next, the prefetch of the address zzzzz, which is the jump destination of the BEQ instruction, is started. At this time, when the BCB signal is set to the low level to invalidate the execution of the instruction at the branch destination, that is, when the condition is not satisfied in the BEQ instruction, the branch does not occur. , The DBGMOV instruction will be executed,
The PC tracking circuit 462 confirms the execution of the DBGMOV instruction by the BCB signal and the LID signal, and then instructs the trace memory 461 to acquire the trace of the data transfer cycle (writing the data dddd to the address cccc).

FIG. 8 shows a timing chart when the branch destination instruction (the instruction at the address zzz) in the BEQ instruction is executed under the above conditions. When the BCB signal is invalid (branching, and thus the DBGMOV instruction is not executed), the PC tracking circuit 462 instructs cancellation of the prefetch data acquisition of the DBGMOV instruction to the trace memory 461. As a result, the next writable current address of the trace memory 461 is D.
The current writing can be invalidated by being returned before the trace acquisition of the prefetch of the BGMOV instruction and being overwritten at the next writing.

According to the above embodiment, there are the following effects. [1] Adding the above-mentioned debugging instruction to the instruction set of the data processors 1 and 40 means that, in an embedded device using such a data processor, a program composed of only ordinary instructions and a part of the program are added. It can be guaranteed that there is no difference in the size, configuration, and operation of the program with the program replaced with the debug instruction. This acts so as not to impair the real-time property required of the emulator 4 that supports debugging while controlling the target device on behalf. Furthermore, this acts so that the emulator 4 can easily distinguish between a normal instruction and a debug instruction during program execution. As a result, by using the emulator 4 having the function of recognizing the debugging instruction and tracing the execution process thereof, the parameters and local variables passed at the time of the subroutine call in the program written in the high-level language can be set. The trace can be acquired by the real-time trace function of the emulator 4, and it becomes possible to debug focusing on such parameters and local variables.

[2] The compiler that automatically generates the above-mentioned debugging instruction can easily generate a machine language program for the data processor of the architecture including the above-mentioned debugging instruction in the instruction set. The compiler that generates the debug information instead of the debug instruction can suppress an increase in the size of the machine language program due to the information used only for debugging.

[3] Emulator 4 having a function of recognizing a debug instruction and tracing the execution process of the instruction
Enables the trace circuit to obtain parameters and local variables that are passed when a subroutine is called in a program written in a high-level language, and enables debugging focusing on such parameters and local variables. An emulator that operates by receiving debug instructions directly has a smaller physical scale than an emulator that has a function to replace necessary parts of instructions with debug instructions based on the debug information generated by a compiler. it can. The latter debugging tool can be used even when there is not enough undefined code that can be assigned to debugging instructions.
It becomes possible to debug by paying attention to parameters and local variables by using debug instructions.

[4] A status signal for distinguishing between the execution of a debugging instruction and the execution of a normal instruction, and further, a status signal indicating that the data processor 40 has executed a debugging instruction, or a debugging instruction. Data processor 1, which outputs a status signal 3 indicating that the fetched debug instruction and a status signal indicating that the fetched debug instruction has been executed,
By having 40, the physical circuit scale of the emulator can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
The overall configuration of the emulator is not limited to that shown in FIG. 3, but may be changed as appropriate without using a control processor. Also, the type of debugging instruction is not limited to the above embodiment, and can be set in correspondence with the instruction necessary for debugging focusing on parameters and local variables. The meanings of the status signals LIR, LID, and BCB output by the data processor may be opposite to those described with reference to FIGS. 7 and 8. That is, the first signal indicating that the head of the instruction is not fetched, the second signal indicating that the prefetched instruction is not transferred to the instruction decoder, and the third signal indicating that the prefetched branch destination instruction is executed. It may be defined as a signal. Alternatively, other definitions may be given.

[0046]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

[1] By adding the debug instruction to the instruction set of the data processor, a debug tool having a function of recognizing the debug instruction and tracing the execution process thereof can be used to generate a high-level language. The parameters and local variables passed when calling a subroutine in the described program can be trace-acquired by the real-time trace function of a debugging tool such as an emulator. Debugging focusing on such parameters and local variables Will be possible.

[2] The program translation method for automatically generating the debug instruction realizes easy generation of the machine language program for the data processor of the architecture including the debug instruction in the instruction set. The program translation method for generating the debug information instead of the debug instruction suppresses an increase in the size of the machine language program due to the information used only for debugging.

[3] A debugging tool that has a function of recognizing a debug instruction and traces the execution process of the instruction uses parameters and local variables that are passed when a subroutine is called in a program written in a high-level language. It is possible to obtain it with a trace circuit and enable debugging focusing on such parameters and local variables. A debug tool that operates by directly receiving debug instructions is
The physical scale of the debug tool can be reduced as compared with a debug tool having a function of replacing a necessary part of the instruction with a debug instruction based on debug information generated by a compiler or the like. The latter debugging tool enables debugging focusing on parameters and local variables by using the debugging instruction even when there is not enough undefined code that can be assigned to the debugging instruction.

[4] A status signal for distinguishing execution of a debug instruction from execution of a normal instruction, a status signal indicating that the data processor has executed a debug instruction, or a debug instruction. Since the data processor has a function of outputting a status signal such as a fetched status signal and a status signal indicating that the fetched debug instruction has been executed, the physical circuit scale of the emulator can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processor according to an embodiment of the present invention.

FIG. 2 is an example flowchart of a processing procedure by a compiler according to the temporary command of the present embodiment.

FIG. 3 is a block diagram showing an entire emulator according to an exemplary embodiment of the present invention.

FIG. 4 is a block diagram of an example of a trace circuit included in the emulator.

FIG. 5 is an example timing chart showing how traces are acquired when a data processor executes a DBGMOV instruction.

6 is an explanatory diagram showing an example of contents obtained in a trace memory according to the execution result of the DBGMOV instruction of FIG. 5 and display contents based on the contents.

FIG. 7 is a timing chart showing in detail the trace acquisition timing when the data processor performs prefetch by taking as an example a case where a branch destination instruction in a BEQ instruction is not executed.

8 is a timing chart when a branch destination instruction in the BEQ instruction of FIG. 7 is executed.

FIG. 9 is an explanatory diagram of an example of an address map assigned based on a program written in a high-level language such as C language.

FIG. 10 is an explanatory diagram showing that the same program, such as a subroutine, is called differently.

FIG. 11 is an explanatory diagram showing that even if the same program is called differently, the addresses of variables are not constant.

[Explanation of symbols]

 1 Data Processor 10 Instruction Analysis Unit 11 Debug Instruction Analysis Unit 20 Instruction Execution Control Unit 21 Output Control Circuit 3 Status Signal 4 Emulator 40 Emulation Data Processor 46 Trace Circuit 460 Trace Condition Judgment Circuit 461 Trace Memory 462 PC Tracking Circuit 463 Instruction Analysis Circuit 5 Host system 6 Target system

Claims (9)

[Claims] 1. A data processor comprising an instruction analysis unit for analyzing a fetched instruction and an instruction execution control unit for executing an instruction according to an instruction analysis result, and an instruction to be analyzed by the instruction analysis unit. A debug instruction analysis unit for analyzing a debug instruction having an instruction code different from that of a predetermined instruction included in the set is provided, and the debug instruction analysis unit forms a pair with the debug instruction. A data processor which obtains at least the same analysis result as an analysis result of an instruction analysis unit for an instruction. 2. The debugging instruction is such that the instruction word length, the size and arrangement of operands, and the number of instruction execution cycles are made equal to the predetermined instruction forming a pair with the debugging instruction. 1. The data processor according to 1. 3. A status signal indicating that the data processor has executed a debug instruction, or a status signal indicating that the debug instruction has been fetched and the fetched debug in response to the analysis result of the debug instruction analysis unit. 3. The data processor according to claim 1, further comprising an output control circuit which outputs a status signal indicating that the instruction for execution has been executed. 4. A program translation method for generating a machine language program for a data processor according to any one of claims 1 to 3 from a source program written in a high-level language, the method comprising: A program translation method comprising a step of generating an instruction code of the above-mentioned debugging instruction with respect to a location of a subroutine call and parameter passing accompanying it. 5. The debug instruction includes a debug jump subroutine instruction in which only an instruction code is different from a jump subroutine instruction in the relevant portion, and a debug move instruction in which only an instruction code is different from a move instruction in the relevant portion. The program translation method according to claim 4, wherein the program translation method includes: 6. A program translation method for generating a machine language program for a data processor according to any one of claims 1 to 3 from a source program written in a high-level language, the method comprising: A program translation method including a step of generating debug information for indicating a position of a subroutine call and a parameter passing position accompanying the subroutine call. 7. A debug tool for debugging a machine language program generated by the program translation method according to claim 4, wherein the trace circuit stores control information for a target device by the debug tool in a trace memory. A debug tool characterized by comprising a debug instruction control circuit for recognizing a debug instruction and storing the execution process in a trace memory. 8. A debug tool for debugging a machine language program generated by the program translation method according to claim 6, wherein a necessary part of the instruction is based on the debug information generated by the program translation method. Is equipped with a circuit that replaces the debug instruction with a debug instruction, and a debug instruction control circuit that recognizes the debug instruction and stores the execution process in the trace memory A debugging tool characterized by being provided. 9. The debug instruction control circuit includes a first signal indicating whether the beginning of an instruction is fetched and a second signal indicating whether a prefetched instruction is transferred to an instruction decoder. , A third signal indicating whether or not to execute the prefetched branch destination instruction is received as a status signal of the data processor, and it is discriminated whether or not the information on the data bus inputted thereto is instruction information. The first signal is used to identify whether or not the prefetched instruction has been executed by the second signal, and it is determined whether or not the prefetched branch destination instruction has been executed by the third signal. 9. The debugging tool according to claim 7, wherein the execution process of the prefetched debugging instruction is stored in a trace memory.