JPH0719870B2 - Lead frame - Google Patents

Description

TECHNICAL FIELD The present invention relates to a lead frame used in manufacturing a semiconductor device.

[Prior Art] A conventional lead frame is constructed as shown in FIGS. 3 (a) and 3 (b).

3 (a) and 3 (b) are plan views showing a conventional lead frame, FIG. 3 (a) is an enlarged view of a semiconductor device forming portion, and FIG. 3 (b) is a view showing the entire lead frame. Is.
In these drawings, 1 is a lead frame, 2 is an inner lead of the lead frame 1, 3 is also an outer lead, 4 is a die pad for mounting a semiconductor element (not shown), and 5 is an outer frame of the lead frame 1. 6 is a suspension lead for connecting the die pad 4 and the outer frame portion 5 of the lead frame 1, and 7 is a resin mold for suppressing the inner lead 2 and the outer lead 3 from being displaced. It is a tie bar for preventing the resin from flowing out to the outer lead portion which is not sealed in the molding process. Numeral 8 is used for aligning the lead frame 1 with the molding die, the tie bar cutting die, the lead molding die and the like in the step of molding the sealing resin, the step of cutting the tie bar 7 and the step of molding the outer lead portion. The positioning holes 8 are formed in the outer frame portion 5 of the lead frame 1 at equal intervals. The positioning hole 8 is usually formed in a circular shape or an oval shape. Reference numeral 9 denotes a portion corresponding to a sub-runner and a gate which are channels of a sealing resin in a molding die (not shown), and this portion is provided at a position just corresponding to the outer frame portion 5 of the lead frame 1. . Reference numeral 10 is a molding line showing the outer shape of the resin when the lead frame 1 is molded with the sealing resin. A two-dot chain line A in FIG. 3 (a) indicates a semiconductor device forming portion including inner leads 2, outer leads 3, die pads 4, suspension leads 6 and tie bars 7. A plurality of semiconductor device forming portions A are arranged in parallel on one lead frame 1 as shown in FIG.

In order to assemble a semiconductor device using the conventional lead frame 1 configured as described above, first, a semiconductor element (chip, die) is mounted on the die pad 4 using a resin die bonding agent, solder or the like. Then, the Al pad electrode of the semiconductor element and the inner lead 2 are connected by a thin metal wire (not shown) made of gold, copper, aluminum or the like.
Next, this lead frame 1 is clamped in a molding die (not shown), and a sealing resin is molded. After the sealing resin is hardened, the tie bar 7 is cut using a mold to bend the outer lead 3 into a predetermined shape, and at the same time, the tip of the outer lead 3 and the outer frame portion 5 of the lead frame 1 are separated. The bending process of the outer lead 3 may be performed before or after the cutting process. Thus, the semiconductor device is completed through the outer lead 3 processing steps.

However, in the conventional lead frame configured as described above, due to the difference in thermal expansion coefficient between the frame material and the sealing resin, the molded portion (hereinafter There was a problem that the molding part was warped. Therefore, recently, in order to suppress the warp of the package after sealing, a method of providing a slit that partially divides the lead frame 1 has been adopted.

4 (a) and 4 (b) are plan views showing a conventional lead frame provided with slits, FIG. 4 (a) is an enlarged view of a semiconductor device forming portion, and FIG. 4 (b) is an overall view. FIG. In these figures, the same or equivalent members as those described in FIGS. 3 (a) and 3 (b) are designated by the same reference numerals, and detailed description thereof will be omitted here. In FIGS. 4 (a) and 4 (b), reference numeral 11 suppresses the distortion caused by the difference in the thermal expansion coefficient between the lead frame 1 and the resin when the resin is sealed and the temperature of the mold during sealing is cooled to room temperature. , Slits to reduce the warp of the semiconductor device due to distortion,
The slits 11 are provided on the sides of the semiconductor device forming portion (indicated by the chain double-dashed line A in the figure) of the lead frame 1, and are provided at four locations so as to surround the semiconductor device forming portion A on four sides. Has been.

[Problems to be Solved by the Invention]

However, in recent years, as the semiconductor device has been further increased in size, the strain caused by the difference in the thermal expansion coefficient between the frame material and the resin is also increased, and as described above, the slit 11 is only provided in the lead frame 1. I can no longer absorb the strain. Therefore, when manufacturing a large-sized semiconductor device, even if a lead frame provided with the slit 11 is used, the warp of the package becomes large.

[Means for Solving the Problems]

A lead frame according to the present invention has a continuous slit surrounding substantially four sides of a semiconductor device forming portion in a portion of the lead frame body except a portion corresponding to a resin injection gate portion of a molding die.

[Action]

Since the semiconductor device forming portion is connected to the lead frame body only at the portion corresponding to the resin injection gate portion of the molding die in the lead frame body, the thermal stress generated in the cooling process after the resin sealing is applied to the lead frame body. It is possible to prevent the portion of the frame body outside the slit from being transmitted to the semiconductor device forming portion.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to FIG.

FIG. 1 is an enlarged plan view showing an essential part of a lead frame according to the present invention, in which FIG. 3 (a), (b) is shown.
The same or equivalent members as those described in 1 above are denoted by the same reference numerals, and detailed description thereof will be omitted here. First
In the figure, reference numeral 21 is a ditch slit for providing the semiconductor device forming portion A at a distance from the lead frame 1.
The ditch / slit 21 is the outer frame portion 5 of the lead frame 1 except the portion 9 corresponding to the sub-runner and the gate of the molding die and the semiconductor device forming portion A.
Are continuously provided so as to surround approximately four directions. Also,
There is a space of 0.3 mm or more between the opening 9 at both ends of the ditch / slit 21 and the portion 9 corresponding to the sub-runner and gate of the molding die.
Is configured to be securely clamped in the molding die.

To assemble a semiconductor device using the lead frame 1 having the ditch / slit 21 as described above, first,
A semiconductor element is mounted on the die pad 4, and the semiconductor element and the inner lead 2 are electrically connected by a metal thin wire or the like. Next, the lead frame 1 is clamped in a molding die, and the semiconductor element, the inner leads 2, and the like, the mold line 10 is resin-sealed. In this sealing step, the temperature of the lead frame 1 and the resin corresponds to the mold temperature, for example,
It reaches a high temperature of about 180 ℃. Then, the lead frame 1 after resin sealing is taken out from the molding die and cooled to about room temperature. When the lead frame 1 is cooled, only the portion inside the ditch / slit 21 of the lead frame 1 acts on the shrinkage of the resin, and therefore the strain caused by the difference in the thermal expansion coefficient between the frame material and the resin is generated. Becomes smaller. Therefore, the warp amount of the sealing resin becomes smaller than that of the conventional one.

Therefore, the ditch
By providing the slits 21, it is possible to prevent the thermal stress generated in the cooling process after resin sealing from being transmitted from the portion outside the slits in the lead frame to the semiconductor device forming portion. The warp of the package due to the difference with the shrinkage amount of the stopping resin can be suppressed to an extremely small size.

Although the lead frame 1 is provided with only the ditch / slit 21 in the above embodiment, a positioning hole may be provided in a portion surrounded by the ditch / slit 21 as shown in FIG.

FIG. 2 is a plan view showing another embodiment of the lead frame according to the present invention, in which the same members as those described in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 2, reference numeral 31 indicates a portion surrounded by the ditch / slit 21 in the lead frame 1, in other words, the semiconductor device forming portion A is aligned with a molding die, a tie bar cut die, a lead molding die and the like. This positioning hole 31 is formed in a corner portion of the semiconductor device forming portion A, and a plurality of positioning holes 31 are provided for one semiconductor device forming portion A. By positioning the semiconductor device forming portion A in each of the above-described devices using the positioning hole 31, even if the semiconductor device forming portion A is displaced with respect to the outer frame portion 5 of the lead 1, the lead Processing and the like can be performed with high accuracy.

〔The invention's effect〕

As described above, in the lead frame according to the present invention, continuous slits that surround substantially four sides of the semiconductor device forming portion are provided in the lead frame body except the portion corresponding to the resin injection gate portion of the molding die. Therefore, it is possible to prevent the thermal stress generated in the cooling process after resin sealing from being transmitted to the semiconductor device forming portion from the portion of the lead frame body outside the slit. Therefore, even when a large-sized semiconductor device is manufactured using the lead frame according to the present invention, it is possible to reliably prevent the sealing resin portion from warping.

[Brief description of drawings]

FIG. 1 is an enlarged plan view showing an essential part of a lead frame according to the present invention, FIG. 2 is a plan view showing another embodiment in which a positioning hole is formed in a semiconductor device forming portion, and FIG. ),
(B) is a plan view showing a conventional lead frame, (a) is an enlarged view of a semiconductor device forming portion, and (b) is a view showing the entire lead frame. 4 (a) and 4 (b) are plan views showing a conventional lead frame provided with slits, FIG. 4 (a) is an enlarged view of a semiconductor device forming portion, and FIG. 4 (b) is an overall view. FIG. 1 ... Lead frame, 2 ... Inner lead, 3 ...
Outer leads, 4 ... die pad, 21 ... ditch
Slit, 31 …… positioning hole.

Claims (1)

[Claims] 1. A semiconductor device forming portion including a die pad on which a semiconductor element is mounted and inner leads and outer leads arranged on the sides of the die pad is formed on a lead frame body, and is sealed in the semiconductor device forming portion. In a lead frame in which a resin is molded, a continuous slit surrounding substantially four sides of a semiconductor device forming portion is provided in a portion of the lead frame body except a portion corresponding to a resin injection gate portion of a molding die. A lead frame characterized in that