JPH07193609A - Digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce a data error rate by making the operation in the synchronization establishing state stable so as to sufficiently absorb a phase jitter caused in an RF frequency converter. CONSTITUTION:Signals of imaginary and real parts from a complex multiplier 12 are given to a phase comparator 13, in which a phase error theta with respect to a predetermined phase is detected, and the phase error is directly fed to one terminal of a selector 19 and fed to the other terminal via a limiter 17. Furthermore, the phase error theta is fed to a synchronization, discrimination circuit 18, which discriminates a frequency pull-in state and a synchronization establish state to control the selection of the selector 19 by its discrimination signal. The selector 19 selects an output of the limiter 17 in the synchronization establishing state to correct the phase comparison characteristic. An output of the selector 19 is smoothed by a loop filter 14 and the resulting signal is given to a numerical control oscillator 15 as a control signal, and its oscillation output is converted into signals of SIN, COS characteristics by a data converter 16 and the converted signal is fed back to the complex multiplier 12 as a carrier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase locked loop circuit used in a carrier recovery circuit of, for example, a multi-phase modulation system or a quadrature amplitude modulation system.

[0002]

2. Description of the Related Art In recent years, research and practical application have been made on large-capacity digital transmission of image information and the like. Digital data transmission methods include a multi-phase modulation method and a quadrature amplitude modulation method. In these modulation methods, when reproducing a reproduced wave from a modulated wave, it has been considered to reproduce a stable carrier wave using a carrier wave reproduction circuit that forms a phase locked loop.

FIG. 6 shows a conventional digital phase locked loop circuit using a complex number signal.

The input terminals 20 and 21 are supplied with complex number signals (I signal, Q signal) converted into digital signals.
The I signal and Q signal are input to the complex multiplier 22.

The complex multiplier 22 has an I input to one side.
Signal, Q signal, and data converter 2 input to the other side
The signal having the sine (SIN) and cosine (CON) characteristics from 6 is multiplied, and the result is supplied to the phase comparator 23. The phase comparator 23 obtains the TAN characteristic from the real number part and the imaginary number part of the multiplication result supplied from the complex multiplier 22, and detects the phase from this inverse characteristic (TAN ⁻¹ ). Then, the phase difference θ between the detected phase and the predetermined phase is obtained,
A phase error signal proportional to the phase difference θ is output to the loop filter 24. The signal composed of the real number part and the imaginary number part output from the complex multiplier 22 is used as a demodulation signal and is supplied to a data demodulation part (not shown).

The loop filter 24 smoothes the phase error signal supplied from the phase comparator 23 to obtain a control signal, and supplies this to the control terminal of the numerically controlled oscillator 25.
The numerically controlled oscillator 25 obtains a phase signal whose oscillation frequency is controlled based on the control signal and supplies the phase signal to the data converter 26. The data converter 26 divides the phase signal supplied from the numerically controlled oscillator 25 into two signals to divide SIN and CON into two signals.
The signal is converted into a characteristic signal and is supplied to the other side input of the complex multiplier 22 as a carrier.

As described above, the frequency pull-in and the phase synchronization are performed by the digital loop which returns to the complex multiplier 22, via the complex multiplier 22, the phase comparator 23, the loop filter 24, the numerically controlled oscillator 25, and the data converter 26. Is done.

Attention is now paid to the phase comparator 23.

FIG. 7 shows a data vector when the input modulated wave is QPSK. The white circles shown in the figure show the positions of the original symbols, and the black circles shown in the figure show the positions of the received symbols. The phase error θ between the symbol position of the white circle and that of the black circle, which is the received symbol, can be obtained by the inverse characteristic of TAN (Equation 1).

Θ = TAN ⁻¹ (y / x) − (π / 4) (1) When this phase difference θ is converted into a phase error signal on the sawtooth phase comparison characteristic, it becomes as shown in FIG.

Next, attention will be paid to the phase comparison characteristic of the phase comparator 23.

FIG. 8 shows the phase comparison characteristics with the horizontal axis representing the phase difference θ [rad] and the vertical axis representing the phase error signal. QPSK
In the case of, the phase comparison characteristic is −π / 4 to π / 4 shown in FIG.
And the sawtooth characteristic is proportional to the magnitude of the phase difference θ. The phase difference θ gradually decreases when the synchronization is established after the frequency pulling state. When the synchronization is completely established, the phase difference θ becomes 0 and the phase error signal output from the phase comparator 23 becomes 0. However, when C / N is low, the phase error signal is detected because it fluctuates due to noise even though the synchronization is established. Focusing on the first quadrant of FIG. 7, the original digital phase-locked loop shows that when the first received symbol is located on the left side of the original symbol position of the white circle, the next received symbol is the original symbol of the white circle. The positions are alternately arranged to the right of the position, and are configured so as to gradually approach the symbol position indicated by the white circle, but because the C / N is low despite the synchronization establishment state, When a symbol which is continuous to the left side or the right side is received due to noise, cycle slip occurs, which is a problem. If the loop gain of the loop filter 24 is set to a narrow band, it will not be affected by noise, and thus cycle slip will not easily occur. However, if the loop gain is set to a narrow band, the analog signal received by the antenna will be converted to a 140 MHz analog signal. Since it becomes impossible to absorb the phase jitter generated in the RF frequency converter (not shown), the data error rate becomes large.

[0013]

As described above, in the digital phase locked loop circuit, when the phase comparison characteristic of the phase comparator is the sawtooth characteristic, the C / N is low even though the synchronization is established. In this case, there is a problem in that a cycle slip occurs when receiving consecutive symbols on the left side or the right side of the original symbol position due to being shaken by noise. If the loop gain of the loop filter is set to a narrow band, it will not be affected by noise, but if the loop gain is simply set to a narrow band, an RF frequency converter (not shown) for converting the analog signal received by the antenna into a 140 MHz analog signal. However, since the phase jitter generated in 1) cannot be absorbed, the data error rate increases.

Therefore, an object of the present invention is to provide a digital phase locked loop circuit which stabilizes the operation in the synchronization established state, can sufficiently absorb the phase jitter generated in the RF frequency converter, and can reduce the data error rate. To do.

[0015]

According to the present invention, in a digital phase-locked loop circuit circuit that receives a signal of a complex number expression as an input, the complex number signal is used as one input, and a characteristic F or a characteristic that is an output of the data conversion means. A complex number multiplication means for performing a complex number multiplication of one side input and the other side input with the carrier of G as the other side input; and a phase error detection means for detecting a phase error from the output of the complex number multiplication means based on the phase comparison characteristic, Phase error adjusting means for adjusting the phase error output from the phase error detecting means, synchronization determining means for monitoring the frequency pull-in state or the phase synchronization established state using the output from the phase error detecting means, and the synchronization determination When the output of the means determines the frequency pull-in state, the output from the phase error detecting means is selected, and when the synchronization established state is determined, the Selecting means for selecting the output from the phase error adjusting means, loop filter means for smoothing the phase error output from the selecting means, and numerical control oscillation means for controlling the oscillation frequency by the output of the loop filter means, Data conversion means for converting the output of the numerically controlled oscillation means into the characteristic F or the characteristic G and outputting it as the carrier.

Further, according to the present invention, the phase error detecting means detects the phase by the inverse characteristic of TAN using the real part and the imaginary part of the output of the complex number multiplying means, and uses this output to detect the phase by the linear phase comparison characteristic. It is realized by means for detecting a phase error.

Further, according to the present invention, the phase error detecting means detects the phase by the inverse characteristic of TAN using the real number part and the imaginary number part of the output of the complex number multiplying means, and uses the output to detect the sawtooth phase comparison characteristic. Is realized by means for detecting the phase error.

Further, according to the present invention, the phase error adjusting means is realized by a limiter means for controlling a phase error output from the phase error detecting means.

Further, according to the present invention, the phase error adjusting means detects the phase by the inverse characteristic of TAN using the real part and the imaginary part of the output of the complex number multiplying means, and uses this output to detect the phase by the non-linear phase comparison characteristic. It is realized by means for detecting a phase error.

Further, according to the present invention, the selecting means determines whether the output from the synchronization determining means determines the frequency pull-in state or the synchronization establishment state, and further, C /
Selector for selecting the output from the phase error detecting means when N is higher than the set value A, and selecting output from the phase error adjusting means when C / N is lower than the set value A. Will be realized in.

The present invention also provides the data conversion means,
This is realized by means for converting the output of the numerically controlled oscillation means into SIN or CON characteristics and outputting as the carrier.

[0022]

According to the above means, when the synchronization is established, the output of the phase error adjusting means is automatically used as information to be supplied to the loop filter, the phase comparison characteristic is corrected, and it is less susceptible to noise. Become. Further, this makes it possible to absorb the phase jitter generated in the RF frequency converter that converts the analog signal received by the antenna into the 140 MHz analog signal, and reduce the factor of deterioration of data error.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention and shows a block of a digital phase locked loop circuit which inputs a complex number signal. A complex number signal (I signal, Q signal) converted into a digital signal is supplied to the input terminals 10 and 11. The I signal and the Q signal are input to the complex multiplier 12. The complex multiplier 12 has an I signal input to one side,
The Q signal is multiplied by the signal of the sine (SIN) and cosine (CON) characteristics input from the data converter 16 on the other side, and the result is supplied to the phase comparator 13. The complex number multiplication signal including the real number part and the imaginary number part output from the complex multiplier 22 is used as a demodulation signal and is supplied to a data demodulation unit (not shown).

The phase comparator 13 uses the complex number multiplication signal of the real number part and the imaginary number part supplied from the complex number multiplier 12 to generate T
The AN characteristic is obtained, and the phase is detected from the inverse characteristic (TAN ^-1 ). Then, the phase difference θ (equation 1) between this phase and the phase of the predetermined output is detected, and this phase difference θ is shown in FIG.
It is converted into a phase error signal having the sawtooth phase comparison characteristic shown in FIG. FIG. 2A shows a phase comparison characteristic in the case of QPSK, which is a sawtooth characteristic proportional to the magnitude of the phase difference θ. This phase error signal is supplied to the limiter 17 (phase error adjusting means),
It is supplied to one input of the synchronization determination circuit 18 and the selector 19.

The limiter 17 is set to -1/2 if the phase error signal supplied from the phase comparator 13 is -1/2 or less, 1
If it is / 2 or more, it is limited to 1/2 and the phase error signal of -1/2 to 1/2 is supplied to the other input of the selector 19. Using this limiter 17 is equivalent to having the nonlinear phase comparison characteristic shown in FIG.

The synchronization judgment circuit 18 uses the phase error signal supplied from the phase comparator 13 to output a phase locked loop (PL).
The phase locked state of L) is monitored to determine whether it is the frequency pull-in state or the synchronization established state, and the synchronization determination signal is supplied to the switching control terminal of the selector 19.

The selector 19 selectively derives the phase error signal from the phase comparator 13 when the synchronization determination signal supplied from the synchronization determination circuit 18 indicates the frequency pull-in state, and the synchronization determination signal supplied from the synchronization determination circuit 18. When the signal indicates the synchronization established state, the phase error signal from the limiter 17 is selectively derived. The output of the selector 19 is the loop filter 14
To the numerically controlled oscillator 15 as a control signal. Numerically controlled oscillator 1
5 obtains a phase signal whose oscillation frequency is controlled based on the control signal, and supplies this to the data converter 16. The data conversion device 16 divides the phase signal into two signals to generate SI signals.
It is converted into a signal having N and COS characteristics and supplied to the other end of the complex multiplier 12 as a carrier.

As described above, frequency pull-in is performed by the digital loop which returns to the complex multiplier 12, via the complex multiplier 12, the phase comparator 13, the loop filter 14, the numerical control oscillator 15 and the data converter 16. Phase synchronization is performed by a digital loop that returns to the complex multiplier 12, via the complex multiplier 12, the phase comparator 13, the limiter 17, the loop filter 14, the numerical control oscillator 15, and the data converter 16.

By using the limiter 17 to change the phase comparison characteristic of the phase comparator after the synchronization establishment state to the non-linear phase comparison characteristic shown in FIG. 2B, the cycle is affected by noise even when C / N is low. Slip can be suppressed. Also, with this circuit configuration, it is not necessary to narrow the loop gain of the loop filter, and the RF that converts the analog signal received by the antenna into a 140 MHz analog signal is used.
There is no problem that the phase jitter generated in the frequency converter (not shown) cannot be absorbed.

The present invention is not limited to the phase comparison characteristics shown in FIGS. 2A and 2B, but is not limited to the above embodiment.

FIG. 3 shows a second embodiment of the present invention. The same parts as those of the circuit of FIG. 1 are designated by the same reference numerals. The part different from the circuit of FIG. 1 will be described. In this embodiment, the signals of the real number part and the imaginary number part output from the complex multiplier 12 are supplied to the C / N determination circuit 30, and the output of this C / N determination circuit 30 is used as the control signal of the selector 31. Therefore, the synchronization determination circuit 1 is used as the control signal of the selector 31.
8 and the output of the C / N determination circuit 30 are used.

The C / N judgment circuit 30 judges whether or not the C / N of the complex number multiplication signal supplied from the complex multiplier 12 is lower than the set value B, and supplies the C / N judgment signal to the selector 31. is doing. The selector 31 determines from the phase comparator 13 if the synchronization determination signal supplied from the synchronization determination circuit 18 is the synchronization state and the determination result is that the signal supplied from the C / N determination circuit 30 is higher than the set value B. If the determination result is that the phase error signal is selectively derived and the synchronization determination signal supplied from the synchronization determination circuit 18 is in the synchronous state and the signal supplied from the C / N determination circuit 30 is lower than the set value B,
The phase error signal from the limiter 17 is selectively derived. The operation of the other parts is the same as that of the first embodiment.

In the case of the above-described embodiment, when the C / N is low after the synchronization is established, the limiter 17 is used to change the phase comparison characteristic of the phase comparator to the nonlinear phase comparison characteristic shown in FIG. Thus, when the synchronization is established, a cycle slip does not occur due to the influence of noise, and the synchronization can be stably maintained. Further, it is not necessary to set the loop gain of the loop filter to a narrow band, and it becomes impossible to absorb the phase jitter generated in the RF frequency converter (not shown) that converts the analog signal received by the antenna into the 140 MHz analog signal. Does not occur.

FIG. 4 shows a third embodiment of the present invention.

The same parts as those of the circuit of FIG. 3 are designated by the same reference numerals. The part different from the circuit of FIG. 1 will be described. In the case of this embodiment, the phase difference θ obtained from the phase comparator 13 is further supplied to the second phase comparator 40. The phase comparator 40 converts the phase difference θ into a phase error signal having a non-linear phase comparison characteristic as shown in FIG. The phase comparison characteristic shown in FIG. 2B is converted into a phase error signal of -1/2 to 1/2 proportional to the magnitude of the phase difference θ while the phase difference θ is between -π / 8 and π / 8. However, when the phase difference θ is −π / 8 or less,
The phase difference θ, which is a fixed value of −1/2, has a phase difference θ of π.
In the case of / 8 or more, a phase error signal having a fixed value of 1/2 is obtained. This phase error signal is supplied to the synchronization determination circuit 18 and one input terminal of the selector 41. The output of the phase comparator 13 is supplied to the other input terminal of the selector 41. The synchronization determination circuit 18 uses the output of the phase comparator 13 to determine whether or not the synchronization is established, and supplies the synchronization determination signal to the control terminal of the selector 17.

The selector 41 selectively derives the phase error signal supplied from the phase comparator 13 when the synchronization determination signal from the synchronization determination circuit 18 is in the frequency pull-in state, and the synchronization determination signal supplied from the synchronization determination circuit 18. When the signal is in the synchronization established state, the phase error signal supplied from the phase comparator 40 is selectively derived. The operation of the other parts is the same as in the previous embodiment.

According to the above embodiment, the phase comparator 40
By making the phase comparison characteristic of the phase comparator after the synchronization establishment state into the non-linear phase comparison characteristic shown in FIG.
When C / N is low in the synchronization established state, no cycle slip occurs due to the influence of noise, and the synchronization state can be stably maintained. Further, it is not necessary to set the loop gain of the loop filter to a narrow band, and it becomes impossible to absorb the phase jitter generated in the RF frequency converter (not shown) that converts the analog signal received by the antenna into the 140 MHz analog signal. Does not occur.

Of course, the phase comparison characteristics shown in FIGS. 2A and 2B are not limited to the above embodiments. In the third embodiment, the phase comparator 40 uses the phase difference θ supplied from the phase comparator 13 as shown in FIG.
It is converted into a phase error signal having the nonlinear phase comparison characteristic shown in.
This phase error signal is supplied to the synchronization determination circuit 18 and the selector 41. "However, instead of using the phase difference θ supplied from the phase comparator 13, the complex number multiplication output from the complex multiplier 12 is used. The phase difference θ is calculated from the signal and
It is converted into a phase error signal having the nonlinear phase comparison characteristic shown in (B). This phase error signal is supplied to one of the synchronization determination circuit 18 and the selector 41. ", The same effect can be obtained.

FIG. 5 shows a fourth embodiment of the present invention.

The same parts as those of the circuit of FIG. 4 are designated by the same reference numerals. The part different from the circuit of FIG. 1 will be described. In the case of this embodiment, the signals of the real number part and the imaginary number part obtained from the complex multiplier 12 are further input to the C / N determination circuit 50. The output control signal of the synchronization determination circuit 18 and the determination signal from the C / N determination circuit 50 are input to the control end of the selector 51. The synchronization determination circuit 18 monitors the phase synchronization state using the phase error signal supplied from the phase comparator 13, determines whether it is the frequency pull-in state or the synchronization establishment state, and supplies the synchronization determination signal to the selector 51. . Selector 15
Selects and derives the output phase error signal of the phase comparator 13 when the synchronization determination signal supplied from the synchronization determination circuit 18 is in the frequency pull-in state, and the synchronization determination signal supplied from the synchronization determination circuit 18 indicates the synchronization establishment state. Further, if the determination result that the signal supplied from the C / N determination circuit 50 is higher than the set value B is given, the phase error signal from the phase comparator 13 is selectively derived and supplied from the synchronization determination circuit 18. The phase error signal from the phase comparator 40 is selectively derived if the synchronization determination signal indicates the synchronization establishment state and the determination result that the signal supplied from the C / N determination circuit 50 is lower than the set value B. The operation of the other parts is the same as in the previous embodiment.

According to the above embodiment, the phase comparison characteristic of the phase comparator after the synchronization establishment state is set to the non-linear phase comparison characteristic shown in FIG. 2B by using the phase comparator 40. As a result, when C / N is low in the synchronization established state, cycle slip does not occur due to the influence of noise, and the synchronization state can be stably maintained. Also, it is not necessary to narrow the loop gain of the loop filter, and the analog signal received by the antenna is 140 MHz.
There is no problem that the phase jitter generated in the RF frequency converter (not shown) for converting into the z analog signal cannot be absorbed.

The phase comparison characteristics shown in FIGS. 2A and 2B are, of course, not limited to the above embodiment. In the third embodiment, the phase comparator 40 uses the phase difference θ supplied from the phase comparator 13 as shown in FIG.
It is converted into a phase error signal having the nonlinear phase comparison characteristic shown in.
This phase error signal is supplied to the synchronization determination circuit 18 and the selector 41. "However, instead of using the phase difference θ supplied from the phase comparator 13, the complex number multiplication output from the complex multiplier 12 is used. The phase difference θ is calculated from the signal and
It is converted into a phase error signal having the nonlinear phase comparison characteristic shown in (B). This phase error signal is supplied to one of the synchronization determination circuit 18 and the selector 41. ", The same effect can be obtained. Further, the present invention can be variously modified without departing from the scope of the invention.

[0044]

As described above, according to the present invention,
It is possible to stabilize the operation in the synchronization established state, sufficiently absorb the phase jitter generated in the RF frequency converter, and reduce the data error rate.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram shown to explain the operation of the circuit of the present invention.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a conventional phase locked loop circuit.

FIG. 7 is a vector diagram shown for explaining the operation of the circuit of FIG.

8 is a phase comparison characteristic diagram shown for explaining the operation of the circuit of FIG.

[Explanation of symbols]

12 ... Complex multiplier, 13, 40 ... Phase comparator, 14 ... Loop filter, 15 ... Numerically controlled oscillator, 16 ... Data conversion device, 17 ... Limiter, 18 ... Synchronization determination circuit, 19,
31, 41, 51 ... Selector, 30, 50 ... C / N determination circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location 9297-5K H04L 27/00 H (72) Inventor Susumu Komatsu 3-3-9 Shimbashi, Minato-ku, Tokyo No. Within Toshiba Abu E Co., Ltd.

Claims (7)

[Claims] 1. A digital phase-locked loop circuit which receives a signal of a complex number expression as an input, and the complex number signal as an input on one side, and a carrier of a characteristic F or a characteristic G which is an output of a data conversion means as an input on the other side. , A complex number multiplication means for performing a complex number multiplication of one side input and the other side input, a phase error detection means for detecting a phase error from the output of the complex number multiplication means by a phase comparison characteristic, and a phase error from the phase error detection means A phase error adjusting unit that adjusts the output, a synchronization determining unit that determines whether the frequency pulling state or the phase synchronization is established by using the output from the phase error detecting unit, and the output of the synchronization determining unit determines the frequency pulling state. The output from the phase error detection means is selected when the output is from the phase error detection means, and the output from the phase error adjustment means is selected when the synchronization establishment state is determined. Select means for selecting, loop filter means for smoothing the phase error output from the select means, numerical control oscillation means whose oscillation frequency is controlled by the output of the loop filter means, and output of the numerical control oscillation means A digital phase-locked loop circuit comprising: a data conversion unit that converts the characteristic F or the characteristic G and outputs the carrier. 2. The phase error detecting means detects the phase with the inverse characteristic of TAN using the real number part and the imaginary number part of the output of the complex number multiplying means, and uses this output to detect the phase error with the linear phase comparison characteristic. The digital phase locked loop circuit according to claim 1, wherein the digital phase locked loop circuit is detected. 3. The phase error detecting means detects the phase with the inverse characteristic of TAN using the real number part and the imaginary number part of the output of the complex number multiplying means, and uses this output to detect the phase error with the sawtooth phase comparison characteristic. The digital phase-locked loop circuit according to claim 1, wherein 4. The digital phase locked loop circuit according to claim 1, wherein the phase error adjusting means has a limiter means for controlling a phase error output from the phase error detecting means. 5. The phase error adjusting means detects a phase with an inverse characteristic of TAN using a real number part and an imaginary number part of an output of the complex number multiplying means, and uses this output to detect a phase error by a non-linear phase comparison characteristic. The digital phase locked loop circuit according to claim 1, wherein the digital phase locked loop circuit is detected. 6. The selecting means, when the output from the synchronization judging means judges the frequency pull-in state,
When the output from the phase error detecting means is selected, the synchronization establishment state is determined, and C / N is lower than the set value A,
2. The digital phase locked loop circuit according to claim 1, further comprising select means for selecting an output from the phase error adjusting means. 7. The digital phase locked loop circuit according to claim 1, wherein said data conversion means has means for converting an output of said numerically controlled oscillation means into a SIN or CON characteristic and outputting it as said carrier. .