JPH07193529A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To converge a judgement feedback-type equalizer at high speed in a digital subscriber transmission system using an echo cancellor so as to shorten training time. CONSTITUTION:A correlation signal between inter-remaining code interference and an identification result, which is the differential signal of the input/output signals of an identification judgement unit 7, is cumulatively added by an integrator. The integrated result is sampled by a sampling means 13 at every NT (N: the number of integrating times and T: a baud rate period). The differential signal of the sampled signal and the previous integrated result is inputted by a coefficient selection circuit 16. A weight coefficient (a step size) in the judgement feedback-type equalizer in the middle of training is adaptively controlled based on the codes of the two input signals. Thus, the judgement feedback-type equalizer in a training period can be converged at high speed and training time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a two-wire / four-wire conversion circuit of a wire communication device. The present invention is used, for example, in a digital subscriber line device. INDUSTRIAL APPLICABILITY The present invention is used in a receiving side circuit of a two-wire to four-wire conversion circuit configured to remove echo using an echo canceller. The present invention relates to signal processing of a reception output in which signal processing is executed at a digital level and echo is suppressed by an echo canceller. In particular, the present invention relates to a technique for shortening the convergence time of a decision feedback equalizer that generates a signal for addition / subtraction to the output of an echo canceller during training using a training signal.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a main part of a digital subscriber line transmission system using an echo canceller. This system includes a transmission circuit 26, a digital / analog converter 25, a hybrid transformer 2, a subscriber line 1, an analog / digital converter 3, an echo canceller 4, an arithmetic circuit 5, an identification / determination unit 7, a sampling phase extraction circuit 27, and A decision feedback type equalizer 18 is provided. In a system having such a configuration, a training period is provided as a system setup mode before a full-duplex communication state is set, and a cold start, which is a startup from a system full reset state, and a subscriber line 1 It can be divided into two, warm start, which is the start-up from the state that holds the state.

The training times for these two modes are set independently, and the ANSI (American National St
andards Institute) standard, 1 cold start
Within 5 seconds, the warm start is set within 300 msec. During the training period, the echo canceller 4 converges, the decision feedback equalizer 18 converges, and the sampling phase extraction circuit 27 pulls in the sampling phase of the system. In particular, the convergence of the decision feedback equalizer 18 and the pulling in of the sampling phase interfere with each other, leading to a longer training time.

As means for controlling the phase, as shown in FIG. 3, the residual intersymbol interference, which is the difference signal between the input signal and the output signal of the discrimination / determination device 7, and the discrimination result, which is the output signal of the discrimination / determination device 7. The sampling means 13 receives as input the integration result 21 obtained by cumulatively adding the correlation signal 20 of the above, and the phase control circuit 19 receives as input the signal 22 sampled by the sampling means 13 and the output signal from the external oscillator 17. It

Next, the operation of the conventional example thus constructed will be described.

The signal 20 obtained by correlating the residual intersymbol interference with the discrimination result is the arithmetic circuit 11 and the baud rate cycle (T = 1).
/ 80 kHz) N by the integrator consisting of the delay device 12
The signal 21 is accumulated and added once. This N times of cumulative addition processing averages the signal 20. The signal 21 is sampled for each NT by the sampling means 13.

Assuming that the internal result of the delay unit 12 is reset (initialized) for each NT, the signal 22 sampled for each NT by the sampling means 13 is used.
Is input to the phase control circuit 19. This phase control circuit 1
9 is the baud rate clock (80k) which is the operating clock of the system based on the sign of the sampled signal 22.
1 cycle (about 65 nsec) of the external oscillator 17 (15.36 MHz) which is the master clock of the phase system of (Hz)
Digitally control with.

In the case of this example, N (the number of times of integration) is set to 64 in consideration of the follow-up property of phase pull-in and the amount of jitter generation. The phase control algorithm when the amount of one phase update is Δτ is as follows: 1) When signal 22 ≧ 0, Δτ = −T / 192 (delay the phase by 65 nsec) 2) When signal 22 <0, Δτ = T / 192 (advance the phase by 65 nsec) That is, the phase update amount at the time of sampling phase pull-in is one phase width (65 nsec) of the system clock (15.36 MHz) 192 times the baud rate clock (80 kHz), and the signal 22 The control (advance or delay) is performed according to the code. By performing the above operation during training and during normal operation, it is possible to extract the optimum sampling phase from the received data.

FIG. 4 shows an example of the structure of a decision feedback equalizer. The decision feedback equalizer 417 is composed of a digital FIR filter composed of M tap coefficients. In the figure, 411 and 414 are multipliers, 412 and 415.
Are adders, 413 and 416 are delay devices. Multiplier 41
1, the adder 412, the delay device 413, and the multiplier 414
One tap of the R filter is configured. The decision feedback equalizer configured as described above uses the discrimination result 401 which is the output result of the discrimination determiner and the intersymbol interference 402 due to the convergence of the internal coefficient thereof by the multiplier 410 to weight the weighting factor 403 (step size α ) The input is the doubled signal. Conventionally, during the training period, the coefficient of the digital filter unit inside the decision feedback equalizer is trained with a fixed weighting coefficient (step size) such as 2 −10.

[0010]

As described above, a signal obtained by delaying the difference between the input and the output of the discrimination / determination device 7 by a period T (baud rate period) and the discrimination / determination device 7 have been heretofore known.
Sampling means 13 is provided for sampling an integrated signal 21 obtained by integrating the correlation signal 20 with the output of N times over N times, and the output signal 2 of the sampling means 13
2 controls the phase control circuit, sampling period NT
Although there was a technique for shifting the phase of 1) by 1 phase width (about 65 nsec) of the system clock (15.36 MHz), the decision feedback equalizer 18 was fixed during the training time.

Therefore, the training time has been lengthened. In particular, it was difficult to meet the training time standard (300 msec) in the warm start mode.

The present invention intends to adaptively set the weighting coefficient α (step size) of the decision feedback equalizer 18 when the decision feedback equalizer 18 rises by using the above technique. That is, the present invention aims to reduce the training time of the decision feedback equalizer 18. An object of the present invention is to provide a signal processing device which can always meet the American standard (300 msec) of training time.

[0013]

According to the present invention, the coefficient α of a decision feedback equalizer (18) which has not been externally controlled during the training time has been used as the input and output values of the discriminator (7). Is set adaptively to shorten the convergence time.

The present invention is provided in a four-wire receiving circuit of a digital level two-wire to four-wire converting circuit, and an arithmetic circuit (5) for subtracting the output of the echo canceller (4) and the arithmetic circuit (5). An identification / determination device (7) provided at the output and a decision feedback equalizer (18) which receives the input and output of the identification / determination device (7) as inputs and gives an addition / subtraction output to the arithmetic circuit (5). In a signal processing circuit provided, a correlation signal (20) between a signal obtained by delaying a difference between an input and an output of the discrimination / determination unit (7) by a period T (baud rate period) and an output of the discrimination / determination unit (7) is provided. Means (1) for sampling the integrated signal (21) integrated N times at every cycle NT
3), a circuit (15) for calculating a difference between an output signal of the sampling means and a signal obtained by delaying the output signal of the sampling means for a time NT, and outputs of a circuit (15) for calculating the difference And a coefficient selecting circuit (16) for selecting the weighting coefficient α of the decision feedback equalizer (18) with two inputs of the output signal of the sampling means (13).

The coefficient selection circuit may be a ROM in which coefficient values are stored in advance using the two inputs as addresses.

[0016]

In the receiving side of the two-wire / four-wire conversion circuit, the discrimination judging device (7) for judging the code is provided. The difference between the input and the output of the discrimination determiner (7) corresponds to the residual intersymbol interference. The decision feedback equalizer (18) adds and subtracts its output to and from the echo canceller output to reduce this residual intersymbol interference. This is autonomously controlled by the training signal during the training time, and its parameters are fixed at the end of the training time.

Here, in the apparatus of the present invention, the parameter setting of this decision feedback equalizer is separately calculated from the input and output of the discrimination decision unit (7) during the training time, and the result is adaptively set. However, the range in which the autonomous control is actually performed is narrowed, and the time required for convergence using the training signal is shortened.

That is, the difference between the input and the output of the discrimination / determination unit (7) representing the residual intersymbol interference is calculated by a delay circuit (9).
Is delayed by the porate cycle T, and this is correlated with the output of the discriminator (7) (10). This correlation value is added N times with the signal further delayed by the period T to calculate the integral value of this correlation value over the NT time. This integrated value is sampled at the period NT. The integrated value is reset immediately after being sampled.

The difference between the sampled integrated value and the sampled value before the time NT is calculated (15). This difference and the sampled integral value will represent the change during time NT. For example N
When NT is 16 and T is 1/80 kHz, NT is 0.2 msec.
Is. The weighting coefficient (step size) α of the decision feedback equalizer (18) is selected in accordance with this change in time.
This can be immediately read out by using the ROM pre-written as a table in the addresses corresponding to the two inputs in the coefficient selection circuit.

This weighting coefficient α is used as a decision feedback equalizer (1
By forcibly setting to 8), the range in which the decision feedback equalizer (18) autonomously converges can be narrowed. Therefore, the time required for the training time to converge can be significantly shortened.

[0021]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the main part of the embodiment of the present invention.

The embodiment of the present invention is provided in a four-wire receiving circuit of a digital level two-wire to four-wire converting circuit, and an arithmetic circuit 5 for subtracting the output of the echo canceller 4 and this arithmetic circuit 5.
Discrimination determiner 7 provided at the output of the
And a decision feedback equalizer 18 for applying an addition and subtraction output to the arithmetic circuit 5, and a feature of the present invention is that the difference between the input and the output of the discrimination determiner 7 is equal to the period T (baud rate). Sampling means 13 for sampling the integrated signal 21 obtained by integrating the correlation signal 20 of the signal delayed by the period) and the output of the discrimination / determination device 7 N times, and the output signal of this sampling means 13 and this sampling. The output signal of the means 13 is time NT
Calculation circuit 1 for calculating the difference from the signal delayed over
5 and a coefficient selection circuit 16 for selecting the weighting coefficient α of the decision feedback equalizer 18 with two inputs of the output of the calculation circuit 15 for calculating the difference and the output signal of the sampling means 13 The selection circuit 16 is composed of a ROM in which coefficient values are stored in advance using the two inputs as addresses.

Further, a digital-analog converter 25 for receiving the output from the transmission circuit 26 and converting it into digital-analog, and a hybrid transformer 2 for receiving the output of the digital-analog converter 25 and outputting it to the subscriber line 1.
, An analog-digital converter 3 that inputs the output of the hybrid transformer 2 and performs analog-digital conversion, and a line equalizer 6 that inputs the output of the arithmetic circuit 5
An arithmetic circuit 8 that receives the outputs of the line equalizer 6 and the discrimination / determination device 7; a delay device 9 that receives the output of the arithmetic circuit 8; and an arithmetic operation that receives the output of the delay device 9. The circuit 10 includes an arithmetic circuit 11 having an output of the arithmetic circuit 10 as an input, and a delay device 12 having an output of the arithmetic circuit 11 as an input and feeding back.

In the embodiment of the present invention configured as described above, the difference between the input and the output of the discrimination judging device 7 for judging the code provided on the receiving side of the two-wire to four-wire conversion circuit corresponds to the residual intersymbol interference. To do. The decision feedback equalizer 18 adds and subtracts the output from the output of the echo canceller 4 by the arithmetic circuit 5 to reduce the residual intersymbol interference. The control is performed autonomously by the training signal during the training time, and its parameters are fixed at the end of the training time. During the training time, the parameter setting of the decision feedback equalizer 18 is separately calculated from the input and output of the discriminator and decider 7, and the result is adaptively set to actually autonomously control. Is shortened, and the training signal is used to shorten the convergence time.

That is, when the difference between the input and the output of the discrimination / determination unit 7 representing the residual intersymbol interference is delayed by the baud rate period T by the delay unit 9, the arithmetic circuit 10 produces the difference between this and the output of the discrimination / determination unit 7. Correlation is performed, and this correlation value is added N times with the signal delayed by the period T to calculate the integral value of this correlation value over the NT time. This integrated value is sampled at the period NT, and immediately thereafter, this integrated value is reset.

The arithmetic circuit 15 calculates the difference between the sampled integrated value and the sampled value before the time NT. This difference and the sampled integral value represent the change during time NT. For example, if N is 16 and T is 1/80 kHz, N
T is 0.2 msec. The weighting factor (step size) α of the decision feedback equalizer 18 is selected in accordance with the change in time. This can be immediately read out by using the ROM pre-written as a table in the addresses corresponding to the two inputs in the coefficient selection circuit 16.

By forcibly setting this weighting coefficient α in the decision feedback equalizer 18, the range in which the decision feedback equalizer 18 autonomously converges is narrowed. Therefore, it is possible to significantly reduce the time required for the training time to converge.

That is, according to the present invention, as in the conventional method, the residual intersymbol interference, which is the difference signal of the input / output signals of the discrimination / determination unit 7, is delayed by one time slot of the baud rate clock (80 kHz) to determine the discrimination / determination unit. 7 and the correlation signal 20 is cumulatively added by an integrator composed of the arithmetic circuit 11 and the delay unit 12. The cumulatively added signal 21 is sampled for each NT by the sampling means 13. At the same time as sampling for each NT, the signal cumulatively added to the delay unit 12 is also reset. Here, N represents the number of integrations and is set to 64 as in the conventional method. The signal 22 sampled by the sampling means 13 is input to the NT time delay device 14. The arithmetic circuit 15 uses the signal 22 and the delay device 14 to generate N.
The difference signal 23 from the signal delayed by T time is output. The signal 22 and the difference signal 23 are input to the coefficient selection circuit 16, and the coefficient selection circuit 16 uses the decision feedback equalizer 1
8 Controls the weighting coefficient (step size) used for internal coefficient growth.

[0029]

As described above, according to the present invention, when the phase of the baud rate clock is pulled during training, the weighting coefficient (step size) in the process of convergence of the decision feedback equalizer is set to the residual intersymbol interference. By adaptively controlling the decision feedback equalizer, the decision feedback equalizer can be converged at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a main part of a digital subscriber line transmission system according to a conventional example.

FIG. 3 is a block diagram showing a configuration of a main part of a conventional example.

FIG. 4 is a block diagram showing a configuration example of a decision feedback equalizer according to an embodiment of the present invention and a conventional example.

[Explanation of symbols]

 1 Subscriber line 2 Hybrid transformer 3 Analog-digital converter 4 Echo canceller 5, 8, 10, 11, 15 Arithmetic circuit 6 Line equalizer 7 Discrimination judgment device 9, 12, 14 Delay device 410, 411, 414 Multiplier 13 Sampling means 16 Coefficient selection circuit 18, 417 Decision feedback equalizer 19 Phase control circuit 17 External oscillator 25 Digital-analog converter 26 Transmission circuit 27 Sampling phase extraction circuit 412 Adder 413 Delay device

Claims (2)

[Claims] 1. An arithmetic circuit provided in a four-wire receiving circuit of a digital level two-wire to four-wire conversion circuit for subtracting the output of an echo canceller, an identification judging device provided at the output of this arithmetic circuit, and In a signal processing circuit comprising a decision feedback equalizer which receives the input and output of the discrimination / determination unit as its inputs and gives an addition / subtraction output to the arithmetic circuit, the difference between the input and output of the discrimination / determination unit is calculated as a cycle T (baud rate period). ), A means for sampling an integrated signal obtained by integrating the correlation signal between the delayed signal and the output of the discriminator / judgment device N times for each cycle NT, an output signal of the sampling means, and an output signal of the sampling means. A circuit for calculating the difference between the signal delayed by time NT and the output of the circuit for calculating the difference and the output signal of the sampling means. One of the inputs and to the decision feedback equalizer signal processing circuit, characterized in that it includes a coefficient selection circuit for selecting the weighting coefficient α for. 2. The signal processing circuit according to claim 1, wherein the coefficient selection circuit is a ROM in which coefficient values are stored in advance using the two inputs as addresses.