JPH07193401A - High frequency chalk circuit - Google Patents

Abstract

PURPOSE:To obtain a high frequency chalk circuit which is capable of miniaturizing a circuit and has sufficient high frequency blocking effect and shield effect. CONSTITUTION:A leader line 1 is the high impedance line inside a dielectric layer, and capacity lands 4 and 5 are capable of obtaining large capacitance with small area because they are provided closely to ground conductors 10 and 11 and makes up a low impedance capacitor. Because this capacitor is provided at a location apart from a signal layer LS where the leader line 1 is formed, the unnecessary electrical coupling with the signal layer LS or the circuit formed at the proximity layer is reduced. The ground conductors cover both surfaces of the dielectric layer where the capacity land and the leader line are incorporated and electromagnetically shields the circuit formed inside a dielectric from an external circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency choke circuit, and more particularly to a high frequency choke circuit for blocking the passage of high frequencies such as microwaves and millimeter waves and ensuring isolation between circuits.

[0002]

2. Description of the Related Art In a microwave / millimeter wave circuit, a high frequency choke circuit that blocks the passage of high frequencies and allows only direct current to pass is an essential circuit for supplying a direct current bias to, for example, semiconductor elements. Such a high-frequency choke circuit is composed of a high impedance part and a low impedance part (capacitance part). Particularly, the capacitance part requires a larger area as the frequency becomes lower, which is a major factor that hinders the miniaturization of the entire circuit. Has become.

Therefore, various circuit configurations have been proposed to promote miniaturization. As one example thereof, Japanese Patent Laid-Open No. Hei 4-
The high frequency choke circuit disclosed in Japanese Patent No. 284002 will be described.

FIG. 5 is a schematic sectional view showing the structure of the conventional high frequency choke circuit. This high frequency choke circuit is formed on a multi-layer substrate, and a high impedance line 51 and a first ground conductor 52 are provided on a surface layer P1, a low impedance line (capacitance land) 53 is provided on a second layer P2, and a third layer P.
Second grounding conductors 54 are provided on each of the terminals 3. The high impedance line 51 and the capacitive land 53 are connected in series via the through hole 55, and the capacitive land 53 is arranged so as to be sandwiched between the ground conductors 52 and 54.

[0005]

However, in the above-mentioned conventional high frequency choke circuit, since the input / output line connected to the device such as GaAsFET and the wiring such as the matching circuit are also formed in the surface layer P1, the space is provided therebetween. Therefore, there is a problem in that electrical coupling is likely to occur, and a sufficient high frequency blocking effect and shielding effect cannot be obtained. For this reason, active circuits such as an amplifier circuit cannot be operated sufficiently stably.

It is an object of the present invention to provide a high frequency choke circuit which can be downsized and which has a sufficient high frequency blocking effect and shielding effect.

[0007]

A high frequency choke circuit according to the present invention comprises a ground conductor provided on both surfaces of a dielectric layer,
A lead line provided in the central portion of the dielectric layer,
To connect the lead conductor and the capacitance conductor to each other, the capacitance conductor is provided closer to the ground conductor than the lead line and is opposed to the ground conductor with a part of the dielectric layer interposed therebetween. And a through hole provided in the dielectric layer.

[0008]

[Function] Since the lead-out line is a high-impedance line inside the dielectric layer, and the capacitive conductor is provided close to the ground conductor, a large capacitance can be obtained in a small area, and a low-impedance capacitor is configured. To do.

Since the capacitor formed of the capacitive conductor is provided at a position away from the central layer where the lead-out line is formed, unnecessary electrical coupling with a circuit formed in the central layer or its adjacent layer is prevented. Will be reduced.

Since the ground conductor sandwiches both surfaces of the dielectric layer containing the capacitance conductor and the lead-out line, it electrically shields the circuit formed inside the dielectric from an external circuit.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic sectional view showing an embodiment of a high frequency choke circuit according to the present invention, and FIGS. 2 and 3 are a schematic plan view and a perspective view of the embodiment, respectively. In addition,
The AA cross section in FIG. 2 corresponds to FIG. Further, each drawing is a schematic diagram for explaining the configuration, and does not reflect actual dimensions and their proportional relationship.

Multilayer Structure In FIG. 1, a lead line 1 is sandwiched between dielectric layers 2 and 3, and capacitive lands 4 and 5 are formed at a predetermined distance from the lead line 1 in the vertical direction. Through holes 6 and 7 are provided in the dielectric layers 2 and 3, and the capacitor lands 4 and 5 are connected to the lead line 1 through these holes.

Further, the capacitive lands 4 and 5 are opposed to the ground conductors 10 and 11 via the dielectric layers 8 and 9, respectively. The thickness d of the dielectric layers 8 and 9 is the dielectric layer 2
And 3 so that the capacitive lands 4 and 5 are arranged closer to the ground conductors 10 and 11 than to the lead line 1. Both surfaces of the dielectric layer are covered with the ground conductors 10 and 11.

In other words, this embodiment comprises a multi-layer substrate having a so-called triplate structure. That is, there are the capacitive layers LC1 and LC2 in which the capacitive lands 4 and 5 are respectively formed in the vertical direction centering on the signal layer LS in which the lead line 1 is formed, and the signal layer LS and the capacitive layer LC1 are present.
And LC2, through holes 6 and 7 are formed between the lead lines 1 and the capacitor lands 4 and 5.

Furthermore, the distance d from the capacitance layers LC1 and LC2
There are ground layers LG1 and LG2 on which the entire surfaces of the ground conductors 10 and 11 are formed. The distance d is set to a value smaller than the distance between the signal layer LS and the capacitance layer LC1 or LC2, and the capacitance layers LC1 and LC2 are formed closer to the ground layers LG1 and LG2, respectively. The dielectric is filled between the layers.

Lead- Out Line The lead-out line 1 is a signal layer L located substantially in the center of the dielectric layer.
The high impedance line necessary for the choke circuit is formed by being formed into S, and thereby the DC bias is passed and the high frequency signal is blocked.

Capacitance lands Capacitance lands 4 and 5 are arranged opposite to ground conductors 10 and 11 via dielectric layers 8 and 9 having a thickness d, respectively. As a result, two capacitors for bypassing a high frequency are connected in parallel vertically.

The capacitive lands 4 and 5 constitute a low impedance line provided in the middle of the lead wire 1, and are circular in this embodiment as shown in FIGS. 2 and 3. The areas of the capacitance lands 4 and 5 are set arbitrarily, and thus the capacitance of the capacitor can be set arbitrarily. Further, the shape of the capacitive land is not limited to the circular shape. The shape may be a fan shape having a desired center angle. For example, a semicircular shape having a center angle of 180 ° can reduce the capacity to ½, and a fan shape having a center angle of 120 ° can reduce the capacity to ⅓.

The distance d between the capacitive land 4 and the ground conductor 10 or between the capacitive land 5 and the ground conductor 11 is set to be shorter than 1/2 of the distance from the signal layer LS to the ground layer LG1 or LG2, preferably 1/3. It is the following. If the distance between the ground conductors 10 and 11 of the multilayer substrate is 500 μm, for example, d = 80 μm is set.

Two such high-frequency bypass capacitors are formed in parallel by the capacitor lands 4 and 5, and the capacitor lands 4 and 5 are arranged in proximity to the ground conductors 10 and 11, so that they are large in a small area. The capacity can be obtained. This further reduces the impedance of the low impedance line.

Further, since the capacitive lands 4 and 5 are formed in a layer distant from the signal layer LS, there is no intersection in the same plane as the microwave circuit formed in the signal layer LS or its adjacent layer, which is unnecessary. Electrical coupling can be reduced.

Ground conductors The ground conductors 10 and 11 have a shielding function because they cover both surfaces of the multilayer board, and electromagnetically connect the internal circuit and the external circuit formed in the signal layer LS or its adjacent layers. Can be separated.

Circuit Characteristics The circuit composed of the lead wire 1, the capacitive lands 4 and 5, and the through holes 6 and 7 constitutes a low-pass filter when viewed from one end of the lead wire 1, and this is favorable. A high frequency blocking effect can be obtained. In particular, the maximum amount of attenuation is obtained at the resonance frequency of the series resonance circuit composed of the inductance of the through holes 6 and 7 and the capacitance of the capacitive lands 4 and 5. Further, by changing the capacitance of the capacitive land 4 as described above, it is possible to easily construct a choke circuit having a plurality of attenuation poles or a wide stop band.

FIG. 4 is a schematic sectional view showing another embodiment of the high frequency choke circuit according to the present invention. As shown in the figure, the high frequency bypass capacitor may be configured by using only one capacitance land 4. In the present embodiment, the circuit structure is simplified, a high high frequency blocking effect is obtained as in the case of the first embodiment, and the capacitive land 4 is formed at a position apart from the signal layer of the lead wire 1. As described above, unnecessary coupling with the microwave circuit is minimized.

The high frequency choke circuit according to the present invention is used, for example, as a part of a microwave / millimeter wave integrated circuit, but can also be used as a component such as an EMI filter. In particular, by using it as a part of the composite microwave circuit module, it is possible to reduce the size and performance of the module.

[0027]

As described in detail above, in the high frequency choke circuit according to the present invention, the lead-out line is a high impedance line inside the dielectric layer, and the capacitive conductor is provided close to the ground conductor. A large capacitance can be obtained in a small area, and a low impedance capacitor is formed. Therefore, a high frequency blocking effect can be obtained with a small occupied area.

Since the capacitor constituted by the capacitive conductor is provided in a layer separated from the central layer in which the lead-out line is formed, even when a microwave / millimeter wave circuit is formed in the central layer or its adjacent layer, Since there is no intersection in the same plane layer, unnecessary electrical coupling is prevented, and stabilization of circuit operation can be achieved. In addition, since the capacitance pattern and the wiring pattern can be multi-layered, the circuit can be downsized.

Since the ground conductor surrounds the dielectric layer containing the capacitance conductor and the lead-out line, the circuit formed inside the dielectric and the outside are electromagnetically shielded. In particular, it is suitable for a high frequency choke circuit such as a microwave circuit because it can prevent radiation from inside the circuit to the outside.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a high frequency choke circuit according to the present invention.

FIG. 2 is a schematic plan view of the present embodiment.

FIG. 3 is a schematic perspective view of the present embodiment.

FIG. 4 is a schematic sectional view showing another embodiment of the high frequency choke circuit according to the present invention.

FIG. 5 is a schematic cross-sectional view showing an example of a conventional high frequency choke circuit.

[Explanation of symbols]

 1 Lead Wire 2 Dielectric Layer 3 Dielectric Layer 4 Capacitance Land 5 Capacitance Land 6 Through Hole 7 Through Hole 8 Dielectric Layer 9 Dielectric Layer 10 Ground Conductor 11 Ground Conductor LS Signal Layer LC1 Capacitance Layer LC2 Capacitance Layer LG1 Ground Layer LG2 Ground layer

Claims (11)

[Claims] 1. A high-frequency choke circuit for blocking high-frequency components, comprising: ground conductors provided on both surfaces of a dielectric layer; a lead-out line provided in a central portion of the dielectric layer; A capacitance conductor provided at a position close to the ground conductor and opposed to the ground conductor via a part of the dielectric layer, and the dielectric layer for interconnecting the lead-out line and the capacitance conductor. A high frequency choke circuit characterized by comprising: a through hole provided in the. 2. The high frequency choke circuit according to claim 1, wherein the capacitance conductor includes first and second capacitance conductors respectively facing the ground conductors provided on the both surfaces. 3. The high frequency choke circuit according to claim 2, wherein the first and second capacitance conductors are interconnected to the lead line through the through holes. 4. The high frequency choke circuit according to claim 1, wherein the capacitance conductor is formed of a capacitance conductor facing one of the ground conductors provided on the both surfaces. 5. The distance between the capacitance conductor and the ground conductor is
1/3 of the distance between the lead-out line and the ground conductor
The high frequency choke circuit according to any one of claims 1 to 4, wherein: 6. A high-frequency choke circuit formed on a dielectric multi-layer substrate, comprising: a ground conductor layer covering both surfaces of the dielectric layer; and a signal having at least a high impedance line formed at the center of the dielectric layer. A layer, and a capacitive conductor layer provided at a position farther from the signal layer than an intermediate position between the signal layer and the ground conductor layer, and opposed to the ground conductor layer with a portion of the dielectric layer interposed therebetween. A high frequency choke circuit formed on a multilayer substrate, comprising: a through hole provided in the dielectric layer for interconnecting the high impedance line and the capacitive conductor layer. 7. The capacitive conductor layer is composed of upper and lower two capacitive conductor layers facing the grounding conductor layers covering the both surfaces, and two upper and lower through conductors provided corresponding to each of the capacitive conductor layers. 8. The high frequency choke circuit according to claim 7, wherein the high frequency choke circuit is connected to the high impedance line through a hole. 8. The high frequency choke circuit according to claim 7, wherein the capacitance conductor layer is composed of one capacitance conductor layer facing one of the ground conductor layers provided on the both surfaces. 9. A high frequency choke circuit comprising a high impedance part and a low impedance part, wherein the high impedance part is a lead line provided in a central part in a dielectric layer, and the low impedance part is the dielectric line. A plane conductor provided in the body layer at a predetermined distance from the lead-out line in the vertical direction, and a part of the dielectric layer at a distance shorter than the predetermined distance from the plane conductor. And a ground conductor facing each other via the ground conductor, and the lead-out line and the planar conductor are interconnected through a through hole provided in the dielectric layer. 10. The high frequency choke circuit according to claim 9, wherein the low impedance portion is a capacitor that bypasses and removes a high frequency component from the lead-out line. 11. The high frequency choke circuit according to claim 9, wherein the ground conductor is provided so as to sandwich both sides of the dielectric layer.