JPH07193246A - Cmos thin-film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To realize concurrently both the high withstanding voltage and high- speed operation of a CMOS thin-film circuit, by giving to its n-channel TFT a stagger structure capable of achieving a high withstanding voltage, and by giving to its p-channel TFT a planar structure capable of accomplishing a high-speed operation. CONSTITUTION:On a glass substrate 101, n<+> source and drain regions 102, 102 are formed, and then, a polycrystal silicon film 104 is formed. Subsequently, the polycrystal silicon film 104 is patterned, and both such an n-channel TFT active layer 105 having an island it and such a p-channel TFT active layer 106 having an island structure that the n<+> source and drain regions 102, 102 convered with it and such a p-channel TFT active layer 106 having an island structure as not to overlap with the n<+> source and drain regions 102, 102 are formed respectively. Then, on both the active layer 105 and the glass substrate 101, both a gate insulation film 107 and a gate electrode 108 are formed respectively. Subsequently, an ion implantation mask 109 is formed both on the gate electrode 108 present on the p-channel IFT active layer 106 and so as to cover the n-channel TFT active layer 105. Thereafter, an ion implantation is performed, and p<+> source and drain regions 111, 111 are formed respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS thin film transistor and its manufacturing method, and more particularly to a CMOS thin film transistor which can be manufactured by a small number of steps and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the progress of the advanced information age, the importance of input / output devices is increasing, and it is required to reduce the cost and improve the reliability of the devices. Against this background,
Liquid crystal display (LCD) and contact image sensor (CI
Research into integrally forming a peripheral drive circuit on the same substrate as an input / output device such as S) has been actively conducted. This is because by integrating the drive circuit, it is possible to reduce the connection cost between the peripheral drive circuit and the device, and it is possible to suppress a decrease in reliability due to a contact failure or the like at the connection portion. A CMOS circuit configuration, which is excellent in terms of power consumption and operational stability, is considered to be advantageous as a method of configuring this drive circuit with a thin film circuit. on the other hand,
In order to further reduce the cost of the device, it is required to reduce the number of steps and increase the throughput. From the above points, it can be said that the technology for forming a CMOS circuit configuration with a small number of steps is important.

A conventional CMOS thin film transistor and its manufacturing process will be described with reference to FIG. First, as shown in FIG. 5A, the LPCV is formed on the glass substrate 301.
After depositing an amorphous silicon (a-Si) film by the D method, it is annealed by a solid phase growth method, an excimer laser annealing method, or the like to make polycrystalline silicon (poly-Si).
Form a film. Next, patterning is performed on the island-shaped structure.
The -ch TFT active layer 302 and the p-ch TFT active layer 303 are formed. Next, as shown in FIG. 5B, a SiO ₂ film is deposited by the LPCVD method, and then L
N + poly containing a high concentration of phosphorus by the PCVD method
After depositing the -Si film, patterning is performed to form the gate insulating film 304 and the gate electrode 305. Next in FIG.
As shown in (c), after applying a resist and patterning to form a first ion implantation mask 306 on the p-ch TFT active layer 303, phosphorus ions 307 are implanted by an ion implantation method to n-ch. An n + source / drain region 308 containing a high concentration of phosphorus is formed in a part of the active layer for TFT. Next, as shown in FIG.
After removing the first ion implantation mask 306, a resist is applied and patterning is performed on the gate electrode 305 on the p-ch TFT active layer, the n-ch TFT active layer 302, and the n ⁺ source / drain regions 308. A second ion implantation mask 309 is formed so as to cover the. Next, boron ions 310 are implanted by an ion implantation method to p-ch.
A p ⁺ source / drain region 311 containing a high concentration of boron is formed on a part of the TFT active layer 303. Next, as shown in FIG. 6B, the second ion implantation mask 30.
9 is removed, an interlayer insulating film 312 is formed, and then a contact hole is formed. Further, after depositing an aluminum film by sputtering, patterning is performed to form source / drain electrodes 313.

[0004]

Generally speaking, n-ch
The TFT has a lower breakdown voltage than the p-ch TFT. For this reason, the breakdown voltage of the CMOS thin film circuit is limited by the breakdown voltage of the n-ch TFT, and it is important to increase the breakdown voltage of the n-ch TFT. Further, in order to improve the performance of the device, it is required to keep the leak current low. In the poly-Si TFT, a large leak current flows as compared with a MOSFET formed in bulk silicon due to an electric field emission current passing through a level near the midgap. (Literature IEE transaction
ON ELECTRON DEVICES (IEEE Tra
ns. on Electron Devices), V
ol. ED-32 No. 9 pp. 1878) In order to improve the breakdown voltage and reduce the leakage current, it is effective to relax the electric field at the drain end.
DD (Lightly Doped Drain) structure (Japan Society of Electronic Communication, 2-20, pp. 2)
71 1978) and offset structure (reference IEE Electron Device Letters (IEEE)
Electron Device Letters) V
ol. EDL-8, No. 9, pp. 434,198
7) has been proposed and put to practical use, but an increase in the number of processes is inevitable. As a means for increasing the breakdown voltage and reducing the leak current by a relatively simple method, it is conceivable to form the TFT with a forward stagger structure. In the forward staggered structure, the surface of the channel and the surface of the source / drain region are separated by the thickness of the active layer, so a minute offset structure is formed, so that the breakdown voltage can be improved and the leakage current can be reduced. . However, in the forward stagger structure, since the gate and the source / drain regions overlap each other, the parasitic capacitance becomes larger than that of the planar TFT, and the operation speed becomes lower than that of the planar TFT.

Immediately after the implantation of the source / drain regions formed by ion implantation of the conventional thin film transistor, the impurity concentration becomes nonuniform in the depth direction. When impurities are activated at a high temperature of about 1000 ° C. after implantation, the uniformity of concentration in the depth direction is improved by diffusion,
In the low temperature process of 600 ° C. or lower, the diffusion coefficient is very small, and it is difficult to make the concentration in the depth direction uniform. This non-uniformity of the impurity concentration in the depth direction has a problem that a contact failure, an increase in leak current, and the like are likely to occur. In particular, the concentration profile when phosphorus is implanted becomes steeper than that of boron, and non-uniformity easily occurs in the depth direction.
There is a problem that it is difficult to improve the characteristics of the ch TFT.

Further, in the conventional method of manufacturing a CMOS thin film circuit, it is necessary to perform ion implantation twice in order to form the n ⁺ layer and the p ⁺ layer. For this reason, it has been difficult to reduce the number of steps, and it has been difficult to reduce the cost of the device.

An object of the present invention is to provide a CMOS thin film transistor which can be manufactured by a small number of steps, has a high breakdown voltage and can operate at high speed, and a manufacturing method thereof.

[0008]

In order to solve the above-mentioned problems, the present invention provides an n-type source / electrode formed of an n-type semiconductor containing a high concentration of n-type impurities formed on an insulating substrate.
The drain region, a p-type source / drain region made of a p-type semiconductor containing a high concentration of p-type impurities, an active layer made of a semiconductor formed in contact with the source / drain region, and the active layer are covered. A gate insulating film formed as described above, a gate electrode formed so as to cover a part of the gate insulating film, an interlayer insulating film formed so as to cover the gate electrode and the gate insulating film, and the source・
In a CMOS thin film transistor having an n-channel thin film transistor and a p-channel thin film transistor, each of which has a source / drain electrode electrically connected to a drain region, the n-channel thin film transistor serves as an n-type source / drain region and has an island-shaped n-type under the active layer. A CMOS thin film transistor comprising a staggered thin film transistor having a semiconductor layer, wherein the p-channel thin film transistor comprises a planar thin film transistor having the p-type source / drain regions formed in the same layer as the active layer. .

Further, a step of forming an n-type source / drain region made of an n-type semiconductor containing a high concentration of n-type impurities on the insulating substrate, and a semiconductor on the n-type source / drain region and the insulating substrate. A step of depositing a layer, patterning the semiconductor layer to cover the n-type source / drain region, and an n-channel thin film transistor active layer having an island structure, and the n-type source / drain region not formed Forming an island-shaped active layer for a p-channel thin film transistor on the insulating substrate; forming a gate insulating film to cover the active layer;
Forming a gate electrode so as to cover a part of the gate insulating film, forming a p-type source / drain region of the p-channel thin film transistor in a self-aligned manner, and covering the gate electrode and the gate insulating film. Thus, there is provided a method for manufacturing a CMOS thin film transistor, which comprises a step of forming an interlayer insulating film and a step of forming source / drain electrodes electrically connected to the source / drain regions.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, an n ⁺ poly-Si thin film containing phosphorus of 1021 cm −3 or more was deposited to 1000 angstroms on a glass substrate 101 by LPCVD at 600 ° C. using silane and phosphine. , Patterning the n ⁺ source
The drain region 102 is formed. Next, as shown in FIG. 1 (b), disilane is used by the LPCVD method at 500 ° C.
After depositing 1000 angstrom of a-Si film by
Irradiation with an excimer laser beam 103 is carried out to form a polycrystalline silicon film 104. Next, as shown in FIG. 1C, the polycrystalline silicon film 104 is patterned to form an island-shaped n-ch TFT active layer 105 that covers the n ⁺ source / drain regions 102 and an n ⁺ source. -The island-shaped p that does not overlap the drain region 102
The -ch TFT active layer 106 is formed. Next in FIG.
As shown in (a), the active layer 105 and the glass substrate 1
01 on top of the silane and oxygen using silane and oxygen 4
A SiO ₂ film is deposited to 2000 angstroms at 00 ° C., and an n ⁺ film containing 1021 cm ⁻³ or more of phosphorus is deposited to 1000 angstroms at 600 ° C. by LPCVD using silane and phosphine, followed by patterning to form a gate insulating film. 107 and gate electrode 10
8 is formed. Next, as shown in FIG. 2B, patterning is performed after applying a resist, and ion implantation is performed so as to cover the gate electrode 108 on the p-ch TFT active layer and the n-ch TFT active layer 105. after forming the use mask 109, an acceleration voltage, boron ions 110 by ion implantation, 15 keV dose of ⁵ × 10 ¹ 5 mc ^- injected at ^2, the gate electrode 108 of the p-ch TFT for active layer 106 is formed 1021 Boron in the unfilled area
cm ^{+ 3} or more p ⁺ source / drain region 111
To form. Further, annealing is performed in a nitrogen atmosphere at 600 ° C. for 24 hours to activate the impurities in the source / drain regions. Next, as shown in FIG. 2C, after removing the ion implantation mask 109, S is formed by plasma CVD.
An iN _X film is deposited to form an interlayer insulating film 112. Further, patterning is performed to form the interlayer insulating film 112 and n-c.
h After forming a contact hole in the TFT active layer 105, aluminum is deposited to a thickness of 3000 angstrom by a sputtering method and patterned to form the source / drain region electrodes 113.

Next, a second embodiment will be described with reference to the drawings. First, as shown in FIG. 3A, a tungsten silicide film is deposited on the glass substrate 201 by a sputtering method to have a thickness of 1000 Å, and then patterning is performed to form a pad 202. Next, as shown in FIG. 3 (b), phosphorus is added to the pad 202 at 600 ° C. by LPCVD using silane and phosphine.
021 cm-n ⁺ poly-Si containing about ³ or more
After depositing a thin film of 1000 angstrom, patterning is performed to form n ⁺ source / drain regions 203. Next, as shown in FIG. 3C, after depositing an a-Si film of 1000 angstrom at 500 ° C. using disilane by the LPCVD method, the excimer laser beam 204 is irradiated to crystallize the poly-Si film 205. To form. Next, as shown in FIG. 4A, the poly-Si film 205 is patterned into an island structure to form an active layer 206 so as to cover the n ⁺ source / drain regions 203.
Further, LP is formed on the active layer 205 and the glass substrate 201.
SiO at 400 ° C. using silane and oxygen by the CVD method
Deposition of ₂ films at 2000 angstrom and LP
600 ° C using silane and phosphine by the CVD method
And n ⁺ poly- containing phosphorus of 1021 cm ^-3 or more
After depositing a Si film at 2000 angstroms, patterning is performed to form a gate insulating film 207 and a gate electrode 20.
8 is formed. Next, as shown in FIG. 4B, after applying a resist, patterning is performed to perform ion implantation so as to cover the n ⁺ source / drain regions 203 on the gate electrode 208 and a part of the pad 202. after forming the mask 209, boron ions 210 accelerating voltage 15 keV, a dose of ⁵ × 10 ¹ 5 cm by ion implantation ^- injected at ^2, the gate electrode 208 and the ion implantation mask 209 of the active layer 206 is formed A p ⁺ source / drain region 211 containing 021 cm ⁻³ or more of boron is formed in the non-doped region. Next, as shown in FIG. 4C, after removing the ion implantation mask 209, plasma CVD is performed.
A SiN _x film is deposited to a thickness of 2000 Å by the method to form an interlayer insulating film 212, and patterning is performed to form contact holes in the interlayer insulating film 212 and the active layer 206. Next, 300 aluminum is sputtered.
A source / drain electrode 213 is formed by depositing 0 angstrom and patterning.

As described above, a CMOS thin film circuit can be manufactured even if the ion implantation is performed only once. In this embodiment, the n-ch TFT has a forward stagger structure, and p-
Although the fabrication process of making the chTFT a planar structure has been described, the n-ch TFT has a planar structure and a p-
It is also possible to fabricate the ch TFT as a staggered structure.

Further, in the second embodiment, a pad made of tungsten silicide having a slow etching rate is formed below the p ⁺ source / drain region, so that the etching at the time of forming the contact hole in the source / drain region is stopped by the pad. be able to. Therefore, the contact characteristics between the n ⁺ or p ⁺ source / drain region and the source / drain electrode can be improved.

[0014]

As described above, in the thin film transistor according to the present invention, the n-ch TFT has the stagger structure capable of increasing the breakdown voltage, and the p-ch TFT has the planar structure capable of increasing the speed. It has an effect that the high breakdown voltage of the circuit and the high speed operation can be realized at the same time.

Further, since the n-ch TFT has a staggered structure, the leak current can be reduced, so that the power consumption can be reduced.

Further, since the method of manufacturing a thin film transistor of the present invention has a step of introducing impurities into the source / drain regions of the n-ch TFT by in-situ doping by the LPCVD method, the impurity profile becomes uniform and contact characteristics are improved. Yields an improved yield, a reduced leakage current, and further improved uniformity of TFT characteristics within the substrate surface.
Furthermore, the n-ch TFT can be formed by one ion implantation process.
Since both types of TFTs, that is, p-ch TFTs and p-ch TFTs can be manufactured, the number of steps of the CMOS thin film circuit can be reduced, and the cost of the input / output device integrated with the CMOS drive circuit can be reduced. It has characteristics.

[Brief description of drawings]

FIG. 1 is a structure and process diagram of a first embodiment of the present invention.

FIG. 2 is a structure and process diagram of a first embodiment of the present invention.

FIG. 3 is a structure and process diagram of a second embodiment of the present invention.

FIG. 4 is a structure and process diagram of a second embodiment of the present invention.

FIG. 5 is a process chart of an example of the prior art.

FIG. 6 is a process diagram of an example of the prior art.

[Explanation of symbols]

101 glass substrate 102 n + source / drain region 103 excimer laser beam 104 polycrystalline silicon film 105 n-ch TFT active layer 106 p-ch TFT active layer 107 gate insulating film 108 gate electrode 109 ion implantation mask 110 boron ion 111 p ⁺ source / drain region 112 interlayer insulating film 113 source / drain electrode 201 glass substrate 202 pad 203 n ⁺ source / drain region 204 excimer laser beam 205 poly-Si film 206 active layer 207 gate insulating film 208 gate electrode 209 for ion implantation mask 210 boron ions 211 p ⁺ source and drain regions 212 interlayer insulating film 213 drain electrode 301 for the glass substrate 302 n-ch active layer 303 p-ch TFT for TFT Sexual layer 304 gate insulating film 305 gate electrode 306 first ion implantation mask 307 phosphorus ions 308 n ⁺ source and drain regions 309 a second ion implantation mask 310, boron ions 311 p ⁺ source and drain regions 312 interlayer insulating film 313 drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 9170-4M H01L 27/08 321 E

Claims (2)

[Claims] 1. An n-type source / drain region formed on an insulating substrate, which is made of an n-type semiconductor containing a high concentration of an n-type impurity, and a p-type semiconductor containing a high concentration of a p-type impurity. p-type source / drain regions and the source / drain regions
An active layer made of a semiconductor formed in contact with the drain region; a gate insulating film formed to cover the active layer; a gate electrode formed to cover a part of the gate insulating film; A CMOS thin film transistor having an n-channel thin film transistor and a p-channel thin film transistor, each of which includes a gate electrode and an interlayer insulating film formed to cover the gate insulating film, and a source / drain electrode electrically connected to the source / drain region, The n-channel thin film transistor is a staggered thin film transistor having an island-shaped n-type semiconductor layer below the active layer as an n-type source / drain region, and the p-channel thin film transistor is formed in the same layer as the active layer. Planar thin film transistor having a p-type source / drain region CMOS characterized by comprising a transistor
Thin film transistor. 2. A step of forming an n-type source / drain region made of an n-type semiconductor containing an n-type impurity at a high concentration on an insulating substrate, and a semiconductor on the n-type source / drain region and the insulating substrate. A step of depositing a layer, patterning the semiconductor layer to cover the n-type source / drain regions, and an n-channel thin film transistor active layer having an island structure and the n-type source / drain regions are not formed. Forming an active layer for a p-channel thin film transistor having an island structure on the insulating substrate; forming a gate insulating film so as to cover the active layer; and covering a part of the gate insulating film. Forming a gate electrode; forming a p-type source / drain region of the p-channel thin film transistor in a self-aligned manner; A method of manufacturing a CMOS thin film transistor, comprising: forming an interlayer insulating film so as to cover the gate insulating film; and forming a source / drain electrode electrically connected to the source / drain region.