JPH07193138A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07193138A
JPH07193138A JP5332239A JP33223993A JPH07193138A JP H07193138 A JPH07193138 A JP H07193138A JP 5332239 A JP5332239 A JP 5332239A JP 33223993 A JP33223993 A JP 33223993A JP H07193138 A JPH07193138 A JP H07193138A
Authority
JP
Japan
Prior art keywords
film
capacitor
tantalum
oxide film
tantalum oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5332239A
Other languages
Japanese (ja)
Inventor
Tatsunori Kaneoka
竜範 金岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5332239A priority Critical patent/JPH07193138A/en
Publication of JPH07193138A publication Critical patent/JPH07193138A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent leak current from increasing by suppressing the reaction between the tantalum oxide film and an upper electrode film. CONSTITUTION:A capacitor is formed by a lower electrode film 5 provided on silicon substrate 1, a dielectric film which is formed by successively laminating silicon nitride film 14 and tantalum oxide film 15 on the lower electrode film 5, and an upper electrode film 19 which is provided on the tantalum oxide film 15 and where tantalum nitride film 17 is formed at the side of the tantalum oxide film 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はダイナミックランダム
アクセスメモリ(以下DRAMと呼ぶ)を有する半導体
装置に係り、特にDRAMのキャパシタの構造に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a dynamic random access memory (hereinafter referred to as DRAM), and more particularly to the structure of a DRAM capacitor.

【0002】[0002]

【従来の技術】図4は従来の4メガビットDRAMのメ
モリセルの断面図の一例である。図において、1はシリ
コン基板、2は素子分離のための第1のシリコン酸化
膜、3はゲート電極などを形成するワード線、4はワー
ド線3を絶縁するための第2のシリコン酸化膜、5は多
結晶シリコンで形成されたキャパシタの下部電極膜であ
る。
2. Description of the Related Art FIG. 4 is an example of a cross-sectional view of a memory cell of a conventional 4-megabit DRAM. In the figure, 1 is a silicon substrate, 2 is a first silicon oxide film for element isolation, 3 is a word line for forming a gate electrode and the like, 4 is a second silicon oxide film for insulating the word line 3, Reference numeral 5 is a lower electrode film of a capacitor made of polycrystalline silicon.

【0003】6は多結晶シリコンで形成されたキャパシ
タの上部電極膜、7はシリコン窒化膜で形成されたキャ
パシタの誘電体膜、8はキャパシタの上部電極膜6を絶
縁する第3のシリコン酸化膜、9はビット線、10はビ
ット線9を絶縁するための第4のシリコン酸化膜、11
はアルミニウム配線、12は不純物拡散層、13はトラ
ンジスタのゲート絶縁膜である。
Reference numeral 6 is an upper electrode film of the capacitor formed of polycrystalline silicon, 7 is a dielectric film of the capacitor formed of a silicon nitride film, and 8 is a third silicon oxide film for insulating the upper electrode film 6 of the capacitor. , 9 is a bit line, 10 is a fourth silicon oxide film for insulating the bit line 9, 11
Is an aluminum wiring, 12 is an impurity diffusion layer, and 13 is a gate insulating film of a transistor.

【0004】従来の4メガビットのDRAMは以上のよ
うに構成され、キャパシタの容量を増大させるためにメ
モリセル構造の3次元化が行われていたが、DRAMの
一層の高集積化に伴い単位面積当たりのキャパシタの容
量を増大させるためにはそれだけでは不充分で、誘電体
膜に比誘電率の高い薄膜材料を適用する必要があり、そ
の一例として例えば図5に示すように比誘電率が約27
でシリコン窒化膜の約3.6倍というタンタル酸化膜を
用いたものがある。
The conventional 4-megabit DRAM is constructed as described above, and the memory cell structure has been three-dimensionalized in order to increase the capacity of the capacitor. In order to increase the capacity of the capacitor per unit, it is not enough, and it is necessary to apply a thin film material having a high relative dielectric constant to the dielectric film. As an example, as shown in FIG. 27
Therefore, there is one using a tantalum oxide film which is about 3.6 times as thick as a silicon nitride film.

【0005】図5はタンタル酸化膜を用いてキャパシタ
を形成する工程を示す図である。図において、図4と同
様の部分は同一符号を付して説明を省略する。14は熱
窒化法により形成されたシリコン窒化膜、15はCVD
法により形成されたタンタル酸化膜である。
FIG. 5 is a diagram showing a process of forming a capacitor using a tantalum oxide film. In the figure, the same parts as those in FIG. 14 is a silicon nitride film formed by a thermal nitriding method, and 15 is a CVD
It is a tantalum oxide film formed by the method.

【0006】以下、図5にもとづいてキャパシタの製造
工程について説明する。まず、図5(a)に示すように
多結晶シリコンによりキャパシタの下部電極膜5を形成
する。次に、図5(b)に示すように例えば800〜9
00℃のアンモニア(NH3)雰囲気による熱窒化法に
よりシリコン窒化膜14を形成する。
The manufacturing process of the capacitor will be described below with reference to FIG. First, as shown in FIG. 5A, the lower electrode film 5 of the capacitor is formed of polycrystalline silicon. Next, as shown in FIG.
A silicon nitride film 14 is formed by a thermal nitriding method in an atmosphere of ammonia (NH 3 ) at 00 ° C.

【0007】そして、このシリコン窒化膜14の上に例
えば350〜400℃でペンタエトキシタンタル(Ta
(OC255)と酸素(O2)とを用いた熱CVD法に
よりタンタル酸化膜15を形成する。その後、キャパシ
タのリーク電流を低減するために例えば800〜950
℃の酸素(O2)雰囲気で熱処理を行う。そして、図5
(c)に示すように多結晶シリコンによりキャパシタの
上部電極膜6を形成して、DRAMのキャパシタが構成
される。
Then, pentaethoxy tantalum (Ta) is deposited on the silicon nitride film 14 at, for example, 350 to 400.degree.
A tantalum oxide film 15 is formed by a thermal CVD method using (OC 2 H 5 ) 5 ) and oxygen (O 2 ). Then, in order to reduce the leakage current of the capacitor, for example, 800 to 950
Heat treatment is performed in an oxygen (O 2 ) atmosphere at ℃. And FIG.
As shown in (c), the upper electrode film 6 of the capacitor is formed of polycrystalline silicon to form a DRAM capacitor.

【0008】[0008]

【発明が解決しようとする課題】従来の半導体装置のD
RAMのキャパシタはその上部電極膜6に多結晶シリコ
ンを用いているため、タンタル酸化膜15と上部電極膜
6との間に、図6に示すように後工程として例えば第3
のシリコン酸化膜8の形成時の熱処理により、タンタル
酸化膜15のTaと上部電極膜6のSiとが反応し、T
aSi2という導電性の化合物から成る化合物層16が
形成され、さらに、順次このキャパシタの上部に形成さ
れる例えばビット線、絶縁膜、アルミニウム配線などの
形成時における熱処理により、この化合物層16のTa
Si2は増加するので、この化合物層16によりキャパ
シタのリーク電流が増大するという問題点があった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The polycrystalline silicon is used for the upper electrode film 6 of the capacitor of the RAM, and therefore, as shown in FIG.
By the heat treatment for forming the silicon oxide film 8 of Ta, Ta of the tantalum oxide film 15 reacts with Si of the upper electrode film 6,
A compound layer 16 made of a conductive compound called aSi 2 is formed, and Ta of the compound layer 16 is further formed by heat treatment when forming, for example, a bit line, an insulating film, and an aluminum wiring, which are sequentially formed on the capacitor.
Since Si 2 increases, there is a problem that the compound layer 16 increases the leak current of the capacitor.

【0009】この発明は上記のような問題点を解消する
ためになされたものでタンタル酸化膜と上部電極膜との
間の反応を阻止することにより、リーク電流の増大を防
止できる半導体装置を得ることを目的としている。
The present invention has been made to solve the above-mentioned problems, and a semiconductor device capable of preventing an increase in leak current by preventing a reaction between a tantalum oxide film and an upper electrode film is obtained. Is intended.

【0010】[0010]

【課題を解決するための手段】この発明に係る請求項1
の半導体装置は、半導体基板上に設けられた下部電極膜
と、下部電極膜上にシリコン窒化膜及びタンタル酸化膜
を順次積層して成る誘電体膜と、誘電体膜上に設けられ
誘電体膜側に金属タンタル膜が形成された上部電極膜と
から成るキャパシタを備えたものである。
[Means for Solving the Problems] Claim 1 according to the present invention
The semiconductor device described in (1) includes a lower electrode film provided on a semiconductor substrate, a dielectric film formed by sequentially laminating a silicon nitride film and a tantalum oxide film on the lower electrode film, and a dielectric film provided on the dielectric film. The capacitor is provided with an upper electrode film on which a metal tantalum film is formed.

【0011】又、この発明に係る請求項2の半導体装置
は上部電極膜のタンタル酸化膜にて成る誘電体膜側の金
属タンタル膜をタンタル窒化膜で形成したものである。
According to a second aspect of the semiconductor device of the present invention, the metal tantalum film on the dielectric film side made of the tantalum oxide film of the upper electrode film is formed of a tantalum nitride film.

【0012】[0012]

【作用】この発明における請求項1の半導体装置のキャ
パシタの上部電極膜のタンタル酸化膜側の金属タンタル
膜は、キャパシタの形成工程以降の熱処理段階における
上部電極膜とタンタル酸化膜との反応を阻止する。
The metal tantalum film on the tantalum oxide film side of the upper electrode film of the capacitor of the semiconductor device according to claim 1 of the present invention prevents the reaction between the upper electrode film and the tantalum oxide film in the heat treatment step after the capacitor forming process. To do.

【0013】又、この発明における請求項2の半導体装
置のキャパシタの上部電極膜のタンタル酸化膜側のタン
タル窒化膜は、キャパシタの形成工程以降の熱処理段階
における上部電極膜とタンタル酸化膜との反応を阻止す
る。
The tantalum nitride film on the tantalum oxide film side of the upper electrode film of the capacitor of the semiconductor device according to claim 2 of the present invention is the reaction between the upper electrode film and the tantalum oxide film in the heat treatment step after the capacitor forming process. Prevent.

【0014】[0014]

【実施例】【Example】

実施例1.以下、この発明の実施例を図にもとづいて説
明する。図1はこの発明の実施例1のDRAMのメモリ
セルの断面図である。図において、従来の場合と同様の
部分は同一符号を付して説明を省略する。17はタンタ
ル酸化膜15の上面に形成されたタンタル窒化膜、18
はこのタンタル窒化膜17の上面に形成された多結晶シ
リコンで、タンタル窒化膜17とで上部電極膜19を形
成する。
Example 1. Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 is a sectional view of a memory cell of a DRAM according to a first embodiment of the present invention. In the figure, the same parts as those in the conventional case are designated by the same reference numerals, and the description thereof will be omitted. Reference numeral 17 is a tantalum nitride film formed on the upper surface of the tantalum oxide film 15,
Is polycrystalline silicon formed on the upper surface of the tantalum nitride film 17, and forms the upper electrode film 19 with the tantalum nitride film 17.

【0015】次に、図2及び図3にもとづいて図1に示
したキャパシタ製造工程を説明する。まず、図1(a)
に示すように従来の場合と同様に、多結晶シリコンによ
りキャパシタの下部電極膜5を形成する。次に、図2
(b)に示すように例えば800〜900℃のアンモニ
ア(NH3)雰囲気による熱窒化法によりシリコン窒化
膜14を形成する。
Next, the manufacturing process of the capacitor shown in FIG. 1 will be described with reference to FIGS. First, FIG. 1 (a)
As shown in FIG. 5, the lower electrode film 5 of the capacitor is formed of polycrystalline silicon as in the conventional case. Next, FIG.
As shown in (b), the silicon nitride film 14 is formed by a thermal nitriding method in an ammonia (NH 3 ) atmosphere at 800 to 900 ° C., for example.

【0016】そして、このシリコン窒化膜14上に例え
ば350〜400℃でペンタエトキシタンタル(Ta
(OC255)と酸素(O2)とを用いた熱CVD法に
よりタンタル酸化膜15を形成する。その後、キャパシ
タのリーク電流を低減するために例えば800〜950
℃の酸素(O2)雰囲気で熱処理を行う。そして図2
(c)に示すように、タンタル酸化膜15上に例えば8
00〜950℃のアンモニア(NH3)の雰囲気中にて
熱窒化法によりタンタル窒化膜17を形成する。
Then, pentaethoxytantalum (Ta) is formed on the silicon nitride film 14 at, for example, 350 to 400.degree.
A tantalum oxide film 15 is formed by a thermal CVD method using (OC 2 H 5 ) 5 ) and oxygen (O 2 ). Then, in order to reduce the leakage current of the capacitor, for example, 800 to 950
Heat treatment is performed in an oxygen (O 2 ) atmosphere at ℃. And Figure 2
On the tantalum oxide film 15, as shown in FIG.
A tantalum nitride film 17 is formed by a thermal nitriding method in an atmosphere of ammonia (NH 3 ) at 00 to 950 ° C.

【0017】そして、図3(a)に示すように多結晶シ
リコン18を形成して、タンタル窒化膜17とで二層の
上部電極膜19を形成してDRAMのキャパシタは構成
される。そして、図3(b)に示すように従来の場合と
同様に後工程として、多結晶シリコン18を絶縁する第
3のシリコン酸化膜8を形成する。
Then, as shown in FIG. 3A, a polycrystalline silicon 18 is formed, and a tantalum nitride film 17 and a two-layer upper electrode film 19 are formed to form a DRAM capacitor. Then, as shown in FIG. 3B, a third silicon oxide film 8 that insulates the polycrystalline silicon 18 is formed as a post-process as in the conventional case.

【0018】上記のように構成された実施例1の半導体
装置は上部電極膜19のタンタル酸化膜15の対向する
側に化学的に安定なタンタル窒化膜17を備えたので、
キャパシタ工程以降の熱処理によるタンタル酸化膜15
のTaと多結晶シリコン18のSiとの反応は阻止され
るため、キャパシタのリーク電流の増大を防止すること
ができる。
Since the semiconductor device of Example 1 configured as described above has the chemically stable tantalum nitride film 17 on the side of the upper electrode film 19 opposite to the tantalum oxide film 15,
Tantalum oxide film 15 by heat treatment after the capacitor process
Since the reaction between Ta and Si of the polycrystalline silicon 18 is blocked, it is possible to prevent an increase in the leak current of the capacitor.

【0019】実施例2.上記実施例1では上部電極19
のタンタル窒化膜17を熱窒化法にて形成する場合につ
いて説明したがこれに限られることはなく、例えば約2
00℃でペンタジメチルアミノタンタル(Ta[N(C
325)とアンモニア(NH3)とを用いたCVD法
によりタンタル窒化膜を形成しても上記実施例1と同様
の効果を奏する。
Example 2. In the first embodiment, the upper electrode 19
The case where the tantalum nitride film 17 of No. 1 is formed by the thermal nitriding method has been described.
Pentadimethylamino tantalum (Ta [N (C
Even if the tantalum nitride film is formed by the CVD method using H 3 ) 2 ] 5 ) and ammonia (NH 3 ), the same effect as that of the above-described first embodiment can be obtained.

【0020】実施例3.上記実施例1では上部電極膜1
9をタンタル窒化膜17及び多結晶シリコン18の2層
構造にした場合について説明したがこれに限られること
はなく、例えば上部電極膜をタンタル窒化膜、スパッタ
法またはCVD法などにて形成されたチタン窒化膜及び
多結晶シリコンの3層構造にて形成しても、上部電極膜
のタンタル酸化膜の対向する側に化学的に安定なタンタ
ル窒化膜が形成されているので、タンタル酸化膜とチタ
ン窒化膜との反応が阻止され上記実施例1と同様の効果
を奏する。
Example 3. In the first embodiment, the upper electrode film 1
Although the case where 9 has a two-layer structure of the tantalum nitride film 17 and the polycrystalline silicon 18 has been described, the invention is not limited to this. For example, the upper electrode film is formed by a tantalum nitride film, a sputtering method or a CVD method. Even if it is formed with a three-layer structure of a titanium nitride film and polycrystalline silicon, a chemically stable tantalum nitride film is formed on the opposite side of the tantalum oxide film of the upper electrode film. The reaction with the nitride film is prevented, and the same effect as that of the first embodiment is obtained.

【0021】[0021]

【発明の効果】以上のように、この発明の請求項1によ
れば半導体基板上に設けられた下部電極膜と、下部電極
膜上にシリコン窒化膜及びタンタル酸化膜を順次積層し
て成る誘電体膜と、誘電体膜上に設けられ誘電体膜側に
金属タンタル膜が形成された上部電極膜とから成るキャ
パシタを備えるようにしたので、タンタル酸化膜と上部
電極膜との間の反応を阻止することにより、リーク電流
の増大を防止できる半導体装置を得ることが可能とな
る。
As described above, according to the first aspect of the present invention, the lower electrode film provided on the semiconductor substrate, and the dielectric formed by sequentially laminating the silicon nitride film and the tantalum oxide film on the lower electrode film. Since the capacitor including the body film and the upper electrode film provided on the dielectric film and having the metal tantalum film formed on the side of the dielectric film is provided, the reaction between the tantalum oxide film and the upper electrode film is prevented. By blocking, it becomes possible to obtain a semiconductor device capable of preventing an increase in leak current.

【0022】又、この発明の請求項2によれば上部電極
膜のタンタル酸化膜側の金属タンタル膜がタンタル窒化
膜にて成るようにしたので、タンタル酸化膜と上部電極
膜との間の反応を阻止することにより、リーク電流の増
大を防止できる半導体装置を得ることが可能となる。
According to the second aspect of the present invention, since the metal tantalum film on the tantalum oxide film side of the upper electrode film is made of a tantalum nitride film, the reaction between the tantalum oxide film and the upper electrode film. By preventing the above, it becomes possible to obtain a semiconductor device capable of preventing an increase in leak current.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例1におけるDRAMの構成を
示す断面図である。
FIG. 1 is a sectional view showing a structure of a DRAM according to a first embodiment of the present invention.

【図2】図1におけるキャパシタの製造工程の一部を示
す断面図である。
FIG. 2 is a cross-sectional view showing a part of a manufacturing process of the capacitor in FIG.

【図3】図1におけるキャパシタの製造工程の残部を示
す断面図である。
FIG. 3 is a cross-sectional view showing the rest of the manufacturing process of the capacitor in FIG.

【図4】従来のDRAMの構成を示す断面図である。FIG. 4 is a cross-sectional view showing a configuration of a conventional DRAM.

【図5】従来の半導体装置の製造工程を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

【図6】図5における半導体装置の欠点を説明するため
の図である。
FIG. 6 is a diagram for explaining a defect of the semiconductor device in FIG.

【符号の説明】[Explanation of symbols]

1 シリコン基板 5 下部電極膜 6、19 上部電極膜 15 タンタル酸化膜 16 化合物層 17 タンタル窒化膜 18 多結晶シリコン 1 Silicon Substrate 5 Lower Electrode Film 6, 19 Upper Electrode Film 15 Tantalum Oxide Film 16 Compound Layer 17 Tantalum Nitride Film 18 Polycrystalline Silicon

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成6年4月7日[Submission date] April 7, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0008[Correction target item name] 0008

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0008】[0008]

【発明が解決しようとする課題】従来の半導体装置のD
RAMのキャパシタはその上部電極膜6に多結晶シリコ
ンを用いているため、タンタル酸化膜15と上部電極膜
6との間に、図6に示すように後工程として例えば第3
のシリコン酸化膜8の形成時の熱処理により、タンタル
酸化膜15と上部電極膜6とが反応し、タンタル酸化膜
15が高リーク電流のSiを含むタンタル酸化膜20、
かつ、その上部にTaSi2という導電性の化合物から
成る化合物層16が形成され、さらに、順次このキャパ
シタの上部に形成される例えばビット線、絶縁膜、アル
ミニウム配線などの形成時における熱処理により、これ
らSiを含むタンタル酸化膜20および化合物層16は
増加するので、Siを含むタンタル酸化膜20によりキ
ャパシタのリーク電流が増大するという問題点があっ
た。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Since the capacitor of the RAM uses polycrystalline silicon for its upper electrode film 6, it is formed between the tantalum oxide film 15 and the upper electrode film 6 as a post-process such as a third process as shown in FIG.
The heat treatment at the time of forming the silicon oxide film 8, react with the tantalum oxide film 1 5 and the upper electrode film 6, a tantalum oxide film
15 is a tantalum oxide film 20 containing high leak current Si,
And, the compound layer 16 upper portion made of a conductive compound of TaSi 2 is formed, further, for example, the bit lines are formed sequentially top of the capacitor, insulating film, by heat treatment during the formation of aluminum wiring, which
Since the tantalum oxide film 20 containing Si and the compound layer 16 are increased, the tantalum oxide film 20 containing Si increases the leak current of the capacitor.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】図6[Name of item to be corrected] Figure 6

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図6】 [Figure 6]

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/822 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に設けられた下部電極膜
と、上記下部電極膜上にシリコン窒化膜及びタンタル酸
化膜を順次積層して成る誘電体膜と、上記誘電体膜上に
設けられ上記誘電体膜側に金属タンタル膜が形成された
上部電極膜とから成るキャパシタを備えたことを特徴と
する半導体装置。
1. A lower electrode film formed on a semiconductor substrate, a dielectric film formed by sequentially laminating a silicon nitride film and a tantalum oxide film on the lower electrode film, and a dielectric film formed on the dielectric film. A semiconductor device comprising a capacitor including an upper electrode film having a metal tantalum film formed on a dielectric film side.
【請求項2】 金属タンタル膜がタンタル窒化膜にて成
ることを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the metal tantalum film is a tantalum nitride film.
JP5332239A 1993-12-27 1993-12-27 Semiconductor device Pending JPH07193138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5332239A JPH07193138A (en) 1993-12-27 1993-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5332239A JPH07193138A (en) 1993-12-27 1993-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07193138A true JPH07193138A (en) 1995-07-28

Family

ID=18252738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5332239A Pending JPH07193138A (en) 1993-12-27 1993-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07193138A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0869972A (en) * 1994-08-30 1996-03-12 Sony Corp Forming method of dielectric thin film
WO1998031052A1 (en) * 1997-01-10 1998-07-16 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
KR100268940B1 (en) * 1997-06-19 2000-10-16 김영환 Capacitor of semiconductor device and manufacturing method thereof
JP2001144272A (en) * 1999-11-09 2001-05-25 Hyundai Electronics Ind Co Ltd Method for fabricating capacitor of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0869972A (en) * 1994-08-30 1996-03-12 Sony Corp Forming method of dielectric thin film
WO1998031052A1 (en) * 1997-01-10 1998-07-16 Hitachi, Ltd. Semiconductor device and method for manufacturing the same
KR100268940B1 (en) * 1997-06-19 2000-10-16 김영환 Capacitor of semiconductor device and manufacturing method thereof
JP2001144272A (en) * 1999-11-09 2001-05-25 Hyundai Electronics Ind Co Ltd Method for fabricating capacitor of semiconductor device
KR100482753B1 (en) * 1999-11-09 2005-04-14 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device

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