JPH07192492A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve a relieving rate when a defective memory cell is relieved by a redundant memory cell. CONSTITUTION:This device is a semiconductor memory having sense amplifiers arranged alternately on both sides of a memory cell region. Sense amplifiers SAR1, SA'R1 connected to redundant memory cells MC1R1... MCnR1 are arranged on both sides of the memory cell region through switching transistors QR1, BQR1, Q'R1, BQ'R1 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having redundant memory cells.

[0002]

2. Description of the Related Art In recent years, with the increase in capacity and integration of semiconductor memory devices, especially dynamic memories, memory cells have become vertical such as trench type (groove type) or stack type (stacked type). Forming a capacitor, memory cell 1
It appears that the area occupied by each piece is reduced.

On the other hand, since the transistors forming the sense amplifier are still conventional planar transistors such as MOS transistors, the sense amplifier cannot keep up with the size reduction of the memory cell described above.

As a countermeasure against this, by alternately arranging sense amplifiers on both sides of the memory cell region, the data line 2
The method of forming the sense amplifier in the size of the pair is taken.

FIG. 3 is a block diagram of a dynamic memory having such a structure.

In FIG. 3, a sense amplifier SA1 connected to data lines D1 and BD1 (in the drawing, BD1 is shown with a bar on D1; the same applies in the following description), The sense amplifier SA2 connected to the data lines D2 and BD2 is arranged on the opposite side to the memory cell region. In the other sense amplifiers, the odd-numbered ones and the even-numbered ones are arranged on the opposite sides of the memory cell region.

By arranging the sense amplifiers in this way, the sense amplifier provided for each pair of data lines is provided for each pair of data lines on one side of the memory cell region. Therefore, even if the size of the memory cell is reduced, the transistor forming the sense amplifier can be easily arranged.

Next, the case of using redundant memory cells will be described. Redundant memory cells have come to be provided with the increase in capacity of semiconductor memory devices, and by replacing defective memory cells with these redundant memory cells, semiconductor memory devices that should originally be defective products can be manufactured. I am trying to be able to rescue it as a good product.

In FIG. 3, memory cells MC _1R1 and M ₁
C _2R1, ..., MC _nR1, and MC _1R2, MC _2R2, ... M
C _nR2 is a redundant memory cell, and the sense amplifiers SA _R1 and SA _R2 connected to each are arranged on the opposite side to the memory cell area. Now, consider a case where the memory cell MC ₁₁ becomes defective. At this time, the structure of the internal circuit is changed by means such as blowing a fuse provided in the circuit, and when the defective memory cell MC ₁₁ is selected, instead of activating the switching signal Y ₁ , the switching signal Y _{R1 Are} activated to connect the data line D _R1 to which the redundant memory cell MC _1R1 is connected to the data input / output line IO2. As a result,
This means that the defective memory cell MC ₁₁ has been replaced with the redundant memory cell MC _1R1 .

[0010]

However, in the above-described conventional semiconductor memory device, when the number of defective memory cells increases, the problem that replacement with redundant memory cells cannot be completed occurs. That is, when the two memory cells MC ₁₁ and MC _1m-1 in FIG. 3 become defective, only one of the defective memory cells can be replaced with the redundant memory cell MC _1R1 . As a result, it will not be possible to rescue them.

In order to solve such a problem, the number of redundant memory cells may be increased so that all of them can be replaced with redundant memory cells even if the number of defective memory cells increases. However, increasing the number of redundant memory cells causes an increase in the pellet area, so there is a problem that the number cannot be increased to a sufficient number.

An object of the present invention is to increase the number of defective memory cells that can be replaced without increasing the number of redundant memory cells, and thus increase the number of semiconductor memory devices that can be repaired as good products without increasing the pellet area. It is to let.

[0013]

A semiconductor memory device according to the present invention includes a memory cell region in which a plurality of memory cells are arranged,
A plurality of data line pairs formed by mutually complementary data lines connected to the memory cells, and an odd number of the plurality of sense amplifiers are arranged on one side of the memory cell region. In the semiconductor memory device, even-numbered ones are arranged on the other side of the memory cell region, and a plurality of redundant memory cells for replacing defective memory cells are arranged in the memory cell region. , The pair of complementary data lines connected to the redundant memory cell are connected to a first sense amplifier via a first switching transistor arranged on one side of the memory cell region, and the memory It is connected to the second sense amplifier via the second switching transistor arranged on the other side of the cell region.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, parts having the same functions as those in the drawings used for the explanation of the prior art are designated by the same reference numerals.

The difference from the conventional dynamic memory shown in FIG. 3 of the present embodiment is that the data lines D _R1 , BD _R1 , DR ₂ . For BD _R2 ,
The sense amplifier SA _R1 disposed on both sides of the memory cell region _{respectively, SA 'R1, SA R2,} SA' R2 and the switching transistor _{Q R1, BQ R1, Q '} R1, BQ R1,
Q _R2, BQ _R2, Q is that the _'R2, BQ' through _R2 is connected.

With such a structure, the memory cell MC
_{Even if 11} and MC _m-1 become defective, these can be replaced with the redundant memory cells MC _1R1 and MC _1R2, and it is possible to remedy those which could not be remedied in the conventional example as good products. That is, when the defective memory cell MC ₁₁ is selected, the switching transistors _{QR 1} , _{QBR 1} ,,
Q _'R1, BQ' of the _R1, Q _R1, and BQ _R1 in a conductive state activates the switching signal phi _R1, the data lines D _R1, BD
_R1 is connected to the sense amplifier SA _R1 . Sense amplifier S
After being amplified by A _R1 , the switching signal Y _R1 is activated and connected to the data input / output lines IO2 and BIO2. This time,
The switching signals φ ′ _R1 , Y ′ _R1 provided on the opposite side of the memory cell region and the switching signal Y ₁ relating to the defective memory cell MC ₁₁ remain inactive. Similarly, when the defective memory cell MC _1m-1 is selected, the switching signals φ _R2 and Y _R2 are activated to connect to the data input / output lines IO2 and BIO2.

In the present invention, the sense amplifiers related to the redundant memory cells are arranged on both sides of the memory cell area. However, by disposing the redundant memory cells themselves at the ends of the memory cell area, the sense amplifier section is The increase in the occupied area can be dealt with by making the sense amplifier part jump out.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In the figure, the same parts as those of the embodiment of FIG. 1 are designated by the same reference numerals. The first embodiment relates to an example in which the present invention is applied to a dynamic type memory in which a sense amplifier is provided for each memory cell area, but the second embodiment has two memory cell areas each having one memory cell area.
The present invention relates to an example in which the present invention is applied to a dynamic memory having a sense amplifier in the form of a shared sense amplifier that shares one sense amplifier.

That is, in FIG. 2, when the memory cell MC ₁₁ in the first memory cell region is selected, the switching transistors Q ₁₁ and BQ ₁₁ are turned on by activating the switching signal φ _4. And sense amplifier S
A ₁ is connected to the data lines D ₂₁ and BQ ₂₁ . On the other hand, when the memory cell MC _'11 of the second memory cell region is selected, the switching transistor Q _21, BQ ₂₁ data lines D ₃₁ to sense amplifier SA1 in the conduction state, BD ₃₁
Connect to.

If the sense amplifier SA1 is configured to be shared by the first memory cell region and the second memory cell region as described above, the sense amplifier for the first memory cell region and the second memory cell region are formed. The number of sense amplifiers can be reduced to half compared to the case where two sense amplifiers are used, and the pellet area can be reduced accordingly.

Also in this embodiment, the redundant memory cells MC _1R1 , MC _2R2 , ..., MC in the first memory cell region are provided.
_{nR1, MC 1R2, MC 2R2,} ..., with respect to the MC data lines connected to _{nR2 D R1, BD R1, D} R2, BD R2, the sense amplifier SA _R1 provided on the side of both the memory cell region respectively, SA ′ _R1 , SA _R2 , SA ′ _R2 and switching transistors _{QR 1} , BQ _R1 , Q ′ _R1 , BQ ′ _R1 , QR _{2
BQ R2, Q 'R2, BQ} ' through _R2 is connected. However, the switching signals φ _R1 , φ ′ _R1 , φ _R2 , and φ ′ _R2 that drive the switching transistors are activated independently of the switching signals φ ₃ and φ ₄ related to ordinary memory cells. There is.

Then, as described in the first embodiment, according to the position of the defective memory in the first memory cell area,
By connecting to the sense amplifier provided on the left side or the right side of the memory cell region, the relief rate that can be relieved as a good product can be improved.

[0025]

As described above, according to the present invention, a plurality of data line pairs each including a memory cell region in which a plurality of memory cells are arranged and complementary data lines connected to the memory cells are provided. And a plurality of sense amplifiers each connected to the plurality of data line pairs, one of the plurality of sense amplifiers having an odd number is one side of the memory cell region. A semiconductor memory device in which even-numbered memory cells are arranged on the other side of the memory cell area and a plurality of redundant memory cells for replacing defective memory cells are arranged in the memory cell area. In the above, a pair of complementary data lines connected to the redundant memory cell is connected to a first sense transistor via a first switching transistor arranged on one side of the memory cell region. Connected to the second sense amplifier via the second switching transistor arranged on the other side of the memory cell region, the redundant memory cell is connected to the redundant memory cell even if the number of defective memory cells increases. The possibility of replacement can be increased, and the repair rate at which a semiconductor memory device that should be a defective product can be repaired as a good product can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

WL word line D data line MC memory cell MC _R redundant memory cell SA sense amplifier IO data input / output line Y switching signal φ switching signal

Claims (2)

[Claims] 1. A memory cell region in which a plurality of memory cells are arranged, a plurality of data line pairs formed of mutually complementary data lines connected to the memory cells, and a plurality of sense amplifiers. Among them, the odd-numbered ones are arranged on one side of the memory cell region, the even-numbered ones are arranged on the other side of the memory cell region, and the defective memory cells are arranged in the memory cell region. In a semiconductor memory device in which a plurality of redundant memory cells for replacement are arranged, a pair of complementary data lines connected to the redundant memory cells are arranged on one side of the memory cell region. Connected to the first sense amplifier via the second switching transistor of the memory cell region, and connected to the first sense amplifier via the second switching transistor arranged on the other side of the memory cell region. A semiconductor memory device characterized by being connected to an amplifier. 2. The semiconductor memory device according to claim 1, wherein the sense amplifier is used as a common sense amplifier for two memory cell regions.