JPH071880B2 - Multiple signal separation circuit - Google Patents

Description

The present invention relates to a multiplex signal separation circuit in multiplex digital communication.

[Conventional technology]

Conventionally, in this type of multiplex signal separation circuit, the process of separating and outputting the multiplex signal has been performed by a large number of gate circuits.

[Problems to be solved by the invention]

The above-described conventional configuration has drawbacks such as complicated logic, difficulty in design, and increase in the number of parts.

[Means for solving problems]

An object of the present invention is to provide a multiplex signal separation circuit that solves the above-mentioned drawbacks. For this reason, the present invention achieves the object by converting the processing for separating and outputting the multiplexed signal into software and writing it in the ROM.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing operation timings of FIG. As shown in FIG. 1, the multiplex signal separation circuit of the present invention includes an input terminal 1 to which a multiplex signal is input, a counter 2, a RAM 3 for storing the data of the multiplex signal input in the past, and a multiplex signal. Separated address 102 and RAM3 created by signal 101 and counter 2
ROM4 that outputs separation signals 108-112 from outputs 103-107 of
A flip-flop 5 for adjusting the output timing of the separation signals 108 to 112, and a buffer 6 for transmitting the output of the flip-flop 5 to the RAM 3 at a certain fixed timing.

In this embodiment, the multiplex signal separation circuit is used in the process of checking the line status in the multiplex digital communication line. This check is performed by the value of the data (status bit) that represents the operating status of the line provided for each certain number of bits called the handling group. In this embodiment, as an input signal, the handling group is 384 Kbit / S, the data showing the operating condition of the line is 1 bit per handling group, and the communication speed is 2 Mbit / S. Of the 8 Mbit / S signal, only 8 data representing the operating condition of the line, 160 bits of data in total, are multiplexed into a frame having 256 multiple addresses. The frame structure of this signal is shown in Fig. 2 (a).
Is shown in. This frame format is defined for the communication speed of 2 Mbit / S, and it is 0-
Any format can be used as long as it can give 160 information to 255 multiple addresses.
As shown in (a), a frame in which a pattern in which multiplexed addresses 0 to 7 and 128 to 135 are vacant and the other portion is a pattern in which 8 data and 4 vacant are continuous is adopted.

Counter 2 is a 16-bit counter and operates at a frequency of 8 MHz. In order to use this 8 MHz counter as a counter with an operating frequency of 2 MHz, the lower bits of the counter 2 are ignored and the bits from the third bit are used. In particular,
The 8th bit from the 3rd bit to the 10th bit of the counter 2 is used as a multiplex address of the multiplex signal 101, that is, the address of the RAM 3, and the 6th bit from the 11th bit to the 16th bit is used as a signal representing the number of frames. At the same time, the separation address 102 of the multiplexed signal is generated by 3 bits from the 11th bit to the 13th bit.

By the way, FIG. 3 (a) shows the multiplexed signal 10 shown in FIG. 2 (a).
The data of the eighth time slot (address 8) in the frame structure of 1 is extracted for 48 frames as shown in FIG. 4 and written in order from the first frame. Since the multiplexed signal 101 has a structure in which the contents of the first frame to the eighth frame are repeated 6 times, the same description is made in FIG. 3 (a). Here, among the repeated 8 frame data, 5 frames from the 2nd frame to the 6th frame are significant in the present embodiment, and the data of each frame respectively represent the operating condition of the line. The contents of the other 3 frames are not limited,
Three time slots are prepared for ease of post-processing.

RAM3 always stores the latest data showing the operating status of the 160 multiplexed lines. After this latest data is written to RAM3, the address of RAM3 changes by 255 to become the same address of the next frame, and it is output to RMO4 at the same time as the multiplex signal 101 which is new data, and then becomes the latest data through the buffer 6. It is stored until it is rewritten. The reason why the data for each line is stored in RAM3 is that one of the five meaningful data is updated per frame input, so the remaining four data are always provided to give a 5-bit output. This is because it needs to be saved. The storage is performed by the address given from the counter 2.

The RMO 4 outputs the data representing the latest operation status of the input line from all of the multiplexed signal 101, the separation address 102, and the data 103 to 107 representing the past status from the RAM 3. This processing is performed by the third step by the pre-written table in ROM4.
It is performed as shown in the figure. Figure 3 (g) shows multiplex signal 1
The separated address 102 corresponding to the time slot 8 (address 8) of 01 is arranged and written for 48 frames as in the case of FIG. 3 (f). As described above, the 48 frames, which are one delimiter of the data indicating the operating condition of the line, are configured such that the contents of the first 8 frames are repeated 6 times. Therefore, it is sufficient to process the first 8 frames.
2 is created by a gate circuit (not shown) provided between the counter 2 and the ROM 4 so as to be zero from the 9th frame to the 48th frame. The RMO4 is composed of a table that rewrites the data corresponding to the separation address among the five data input from the RAM3 and outputs the five data to 108 to 112 as the data indicating the operation status of the new line. There is. The correspondence between the separation address 102 and the data to be rewritten is shown in the table shown in FIG. 5, and the actual operation is shown in FIG. In FIG. 5, the value of the separation address 102 is 0,6,7.
In the case of, it means that the input signal from the RAM 3 is output as it is. As a specific example of the output of RMO4, in the third frame, when there are 8 multiplexed addresses and 2 separated addresses,
As shown in Fig. 3 (d), ST1−
b is rewritten and output from ROM4 ST1-a, ST1-b, ST1-
c ', ST1-d', ST1-e '. In FIG. 3, ′
The data with (dash) shows the data before being rewritten.

The flip-flop 5 retimes the output signal of the ROM 4 as shown in FIG. 2 (d) and outputs it to the output terminals 7 to 11 and the buffer 6. This processing is performed in order to make the output of this circuit easy to use in other circuits by eliminating the time lag in the output of the ROM 4 and outputting.

The buffer 6 supplies the data input from the flip-flop 5 to the RAM 3 according to the pulse shown in FIG. 2 (e). This pulse is created by using the least significant 2 bits of the counter 2, and the buffer 6 supplies data to the RAM 3 when the pulse becomes low level.

The output of this circuit is used, for example, for line maintenance and inspection.

〔The invention's effect〕

As described above, the present invention can realize a multiple signal separation circuit with a small number of parts by performing the processing that was conventionally performed by a large number of gate circuits in the separation of multiple signals with simple hardware such as ROM or RAM.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
(a), (b), (c), (d), (e) and Fig. 3 (a), (b), (c),
(d), (e), (f) and (g) are timing charts showing the operation of FIG. 1, and FIG. 4 explains the conversion method from FIG. 2 (a) to FIG. 3 (a). FIG. 5 and FIG. 5 are diagrams showing a correspondence table of the separated address and the rewritten data. In FIG. 1, 1 ... Multiple signal input terminal, 2 ... Counter, 3 ... RA
M, 4 ... ROM, 5 ... D-flip-flop, 6 ... buffer, 7,8,9,10,11 ... output terminals.

Claims (1)

[Claims] 1. An input terminal to which a signal having a multiplex frame structure is input, a counter which operates in synchronization with the input signal, and a separate signal until the output of the counter is used as an address and a new signal is rewritten. Of the signals stored in the random access memory, the data corresponding to the separation address is rewritten and output from the random access memory storing the input signal, the input signal, and the separation address output from the counter. A read-only memory and a buffer memory arranged between the read-only memory and the random access memory and supplying an output signal of the read-only memory to the random access memory at a predetermined timing. And a multiple signal separation circuit.