US20060007245A1

US20060007245A1 - Image composing system and a method thereof

Info

Publication number: US20060007245A1
Application number: US11/223,369
Authority: US
Inventors: Shigeru Muraki; Masato Ogata
Original assignee: Individual
Current assignee: National Institute of Advanced Industrial Science and Technology AIST; Mitsubishi Precision Co Ltd
Priority date: 2002-04-26
Filing date: 2005-09-09
Publication date: 2006-01-12
Also published as: JP2003323635A; US20030201998A1; US6956585B2; JP4079680B2

Abstract

The present invention provides an image composing apparatus that can composite images at high speed and in which the apparatus configuration can be easily expanded as the number of images to be composed increases. Sub-images generated by node computers are synchronized each other by a synchronizing section. Then, each pair of synchronized sub-image data is composed into a single sub-image in a first-layer image composing section, comprising a plurality of image composing circuits each for composing two sub-images, and the resulting sub-images are composed iteratively through a second-layer image composing section, a third-layer image composing section, and so on, that have the same configuration as the first-layer image composing section.

Description

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a divisional of U.S. application Ser. No. 10/291,854, filed Nov. 8, 2002, which claims priority of Japanese patent application number 2002-126952, filed on Apr. 26, 2002, priority of which are claimed herein.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to an image composing apparatus and method, and more particularly an image composing apparatus and method that can compose images at high speed and in which the apparatus configuration can easily be expanded in proportion to the number of images to be composed.

PRIOR ART

To intuitively grasp the results of computer processing, the results must be presented in visible form. However, as the scale of processing becomes larger, it becomes difficult to generate necessary images using a single computer. Therefore, it is often practiced to compose images using a plurality of computers.
FIG. 1 is a block diagram of an image composing apparatus proposed in the prior art, which comprises N node computers F₁, F₂. . . F_nand an N×N crossbar switch S for enabling the N node computers F₁, F₂. . . F_Nto communicate with each other.
Each of image composing boards C₁, C₂. . . C_Nwhich are dedicated cards for composing images, is connected to a PCI bus on each node computer F_n, and each of the image composing boards C₁, C₂. . . C_Nare connected to each other via the crossbar switch S.
In the image composing apparatus having the above configuration, the image composing board C_non one node computer F_ncomposites an image generated in itself with an image generated in the image composing board C_m(m≈n) on another node computer F_m, and the composed image is transferred to the third node computer F_kvia the crossbar switch S. This process is repeated till a final image is generated.
The above image composing apparatus uses a method in which the images generated by separate node computers are composed together based on a parameter called “Z value” that denotes an image composing order. Though the apparatus can respond flexibly to increasing the number of node computers, it involves following problems.
(1) The Z value denoting the depth from a viewpoint must be added for data of each pixel, but since the Z value must be highly accurate compared with other information (red component R, green component G, blue component B, and transparency α), adding the Z value almost doubles the number of bits in the image data, and the amount of image data to be transmitted increases.
(2) To avoid collisions during transferring image data, a waiting time is necessary, and this waiting time increases the time required for transferring image data.
(3) In order to reduce the image data transferring time, the hardware configuration must be increased, because the crossbar switch, for example, should be specially designed to match with each node computer.
Therefore, in the above image composing apparatus, when the number of node computers is increased.
(1) The scale of the crossbar switch may exceed the practically feasible scale as it increases as the square of the number of node computers.
(2) If the number of node computers is limited to the practically feasible number, the time required for establishing synchronization between the images to be composed increases, and an image composing time increases.

SUMMARY OF THE INVENTION

The present invention has been devised in view of the above problems and an object of the invention is to provide an image composing apparatus and method that can compose images at high speed and in which the apparatus configuration can be easily expanded as the number of images to be composed increases.
According to an image composing apparatus and method of a first invention, N (2≦N) sub-images are merged into a single image based on an occlusion relationship between the N sub-images.
According to an image composing apparatus and method of a second invention, the occlusion relationship is expressed in the form of a binary space-partitioning tree.
According to an image composing apparatus and method of a third invention, input sub-images are composed to generate an output sub-image by iteratively composing two sub-images into one image based on the occlusion relationship between two sub-images.
According to an image composing apparatus and method of a fourth invention, the two sub-image composing process compares priorities which denote the occlusion relationship between the two sub-images, and generates a composed image based on the result of the priority comparison by composing one sub-image which is defined as a first sub-image with another sub-image which is defined a second sub-image.
According to an image composing apparatus and method of a fifth invention, the two sub-images are composed together in accordance with the following equation. $\begin{matrix} I {(R, G, B)}_{M} = I {(R, G, B)}_{1} * {I (α)}_{1} + I {(R, G, B)}_{2} \\ I {(α)}_{M} = I {(α)}_{1} * I {(α)}_{2} \end{matrix}$
Where I(R,G,B)_Mare the RGB components of the composed image, I(R,G,B)₁are the RGB components of the first sub-image, I(R,G,B)₂are the RGB components of the second sub-image, I(α)_Mis the transparency of the merged image, I(α)₁is the transparency of the first sub-image, and I(α)₂is the transparency of the second sub-image.
According to an image composing apparatus and method of a sixth invention, the sub-images are synchronized to each other before merging the sub-images.
According to an image composing apparatus and method of a seventh invention, N sub-images are sequentially stored in N FIFO storing means, and when the head of any one of the N sub-images arrives at any one of the N FIFO storing means, an instruction to output the stored sub-images in the order in which the sub-images were stored is issued to the N FIFO storing means.
According to an image composing apparatus and method of an eighth invention, the plurality of sub-image data have frame structures which contain a priority information at the top of the frame and a sub-image information at the end of the frame.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the configuration of a conventional image composing apparatus.
FIG. 2 is a diagram showing the configuration of a composed image generating system using an image composing apparatus according to the present invention.
FIG. 3 is a diagram showing the configuration of the image composing apparatus according to the present invention.
FIG. 4 is a timing diagram for data transfer between the image composing apparatus and node computers.
FIG. 5 is a sub-image output-timing diagram of the node computers.
FIG. 6 is a diagram showing the configuration of a synchronization circuit.
FIG. 7 is a diagram showing the configuration of a control signal generating circuit.
FIG. 8 is a diagram showing the format of sub-image data.
FIG. 9 is a bit allocation diagram for time slots.
FIG. 10 is a diagram for explaining a method of partitioning space into subspaces.
FIG. 11 is diagram showing a binary space partitioning tree representation.
FIG. 12 is a diagram for explaining an image blending process.
FIG. 13 is a diagram showing the configuration of an image merging circuit.
FIG. 14 is a diagram showing the configuration of a multi-layer image composing apparatus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 is a diagram showing the configuration of a composed image generating system using an image composing apparatus according to the present invention. As shown, the composed image generating system 2 comprises a server 20 which controls the entire apparatus, a display device (for example, a CRT) 21 which displays an image, a plurality of nodes (in the present embodiment, eight nodes) 231 to 238 which generate sub-image signals for a plurality of subspaces created by dividing the three-dimensional space in which an analysis model is constructed, and the image composing apparatus 24 which composes the outputs of the nodes 231 to 238 and transmits a composed result to the server 20.
The server 20 comprises a CPU 201, a memory 202 which stores a program to be executed by the CPU 201 and the result of processing performed by the CPU 201, a graphics board (GB) 203 which outputs an image signal to the display apparatus 21, and an interface board (IFB) 204 for interfacing with the image composing apparatus 24.
The nodes 231-238 have an identical configuration, and each node comprises a CPU 23 b which performs simulation for the subspace in which a portion of an analysis target is constructed, a memory 23 b which stores a simulation program to be executed by the CPU 23 b and the simulation result performed by the CPU 23 b, an image generating engine board (VGB) 23 c which generates an image representing the result of the simulation for the subspace, and an interface board (IFB) 23 d for interfacing with the image composing apparatus 24.
FIG. 3 is a diagram showing the configuration of the image composing apparatus, according to the present invention, which comprises a synchronizing section 240, a first-layer image composing section 241, a second-layer image composing section 242, a third-layer image composing section 243, and an image combining circuit 244.
FIG. 4 is a data transferring timing diagram between the image composing apparatus and the node computers. As shown, the image composing apparatus 24 receives a parameter necessary for image generation from the server and distributes the parameter to the respective node computers 231-238 every predetermined period, and each of the node computers 231-238 receives the parameter and generates a sub-image.
After generating sub-images, the node computers 231-238 transfer the sub-images to the image composing apparatus 24, which composes the sub-images output from the node computers 231-238 and transfers the composed image to the display device 21 though the server 20.
Because each of the node computers 231-238 generally works independently, synchronization of the timings when the sub-images arrive at the image composing apparatus 24 is not guaranteed.
FIG. 5 is a sub-image output timing diagram of the node computers, and this shows a case where the first sub-image of #n frame is output from the first node computer 231 and the last sub-image of #n frame is output from the eighth node computer 238.
In this case, if each of the node computers 231-238 stores the entire of #n frame, and begins to transfer the #n frame to the first-layer image composing section 241 after the last part of the #n frame output from the last node computer (in this example, the eighth node computer 238) is stored, synchronization among the sub-images can be achieved.
However, storing the entire of #n frame requires not only a large capacity of memory, but also long time to store the entire of #n frame.
Therefore, the image composing apparatus of the present invention accomplishes not only synchronizing among sub-images, but also shortening the synchronizing time and minimizing the memory capacity, by providing a synchronizing section 240 at the interface of the node computers, and beginning to transfer the frame of the sub-image to the first-layer image composing section 241 at the timing when the beginning parts of the sub-images frame output from node computers are aligned.
As shown in FIG. 3, the synchronizing section 240 in the image composing apparatus of the present invention comprises a control signal generating circuit A and four synchronization circuits B₁-B₄which have identical configurations.
FIG. 6 is a diagram showing the configuration of each synchronization circuit, and FIG. 7 is a diagram showing the configuration of the control signal generating circuit.
As shown, the synchronization circuit B_ihas two channels: the first channel comprises a FIFO memory 611 and a command decoder 612 connected in parallel with the FIFO memory 611, while the second channel comprises a FIFO memory 621 and a command decoder 622 connected in parallel with the FIFO memory 621.
The first channel works as follows. The FIFO memory 611 sequentially stores the pixel data of the sub-image frame output from the node computer connected to the first channel until READ READY output from the control signal generating circuit A has been received, and outputs the pixel data (I_X) in the same order when they were stored.
The command decoder 612 extracts a priority set (a channel enable and a set priority) contained in the sub-image frame output from the node computer connected to the first channel, and a frame start command and a status sense contained in the frame data. The start command is transferred to the control signal generating circuit A and a 9-bit priority value (P_X) contained in the set priority is transferred to the first-layer image merging section.
The operation of the second channel is the same as that of the first channel, except that the pixel data output from the FIFO memory 621 is I_Yand the priority value is P_Youtput from the command decoder.
FIG. 8 is a diagram showing the format of the sub-image frame output from each node computer, and FIG. 9 is a bit allocation diagram for time slots. Each of the frame computers 231-238 outputs a hardware initialization frame to initialize the image composing apparatus at first, and then sequentially outputs the sub-image frames.
The hardware-initializing frame contains a FIFO reset slot and four dummy slots, and resets the FIFO memory in the synchronization circuit.
The image frame comprises the priority set and frame data, and the priority set contains a channel enable slot and a set priority slot.
The channel enable slot indicates that the channel is in use, and the set priority slot carries the priority given to the sub-image generated by the node computer.
The frame data comprises a frame start slot, a status sense slot, a predetermined number of pixel data slots, and a frame end slot.
The frame start slot denotes the beginning of the frame data, and the frame end slot denotes the end of the frame data.
Each of the pixel data slots stores the red, green, and blue components and the transparency (α value) of each pixel in the sub-image.
Each slot consists of 36 bits, which are allocated as shown in FIG. 9 according to the kind of the slot.
For example, in the set priority slot, the priority is set by using the lower 9 bits in No. 0-15 bits, and “4” is set in No. 24-31 bits and “2” in No. 32-35 bits to show that this slot is a set priority slot.
Likewise, in the pixel data slot, “1” is set in No. 32-35 bits to show that this slot is a pixel data slot. Further, No. 24-31 bits store the red component, No. 16-23 bits store green component, No. 8-15 bits store the blue component, and No. 0-7 bits store the transparency.
The control signal generating circuit A shown in FIG. 7 comprises eight-input AND gate 7, and the frame start slots extracted by the command decoders in the respective synchronization circuits are transferred to the inputs of AND gate 7.
Then, when the eight frame start slots of #n frame are detected, a FIFO read signal, that is, the output of the AND gate 7, becomes “ON”, whereupon the frame data stored in the FIFO memories in the synchronization circuits are read out in the same order when they were stored, and are transferred to the first-layer image composing section.
The pixel data are maintained in the FIFO memories until all of the starting portions of the eight #n frames output from the node computers 231-238 arrive at the synchronizing section. When the starting portion of the eighth #n frame arrives at the synchronizing section, the control signal generating circuit A sets the FIFO read signal ON, and the data of the eight frames is simultaneously transferred to the first-layer image merging section 241. The synchronization among the frame data is accomplished.
Since a single clock controls the image composing apparatus 24, synchronization is guaranteed in the processing after the first-layer image merging section 241.
The first-layer image composing section 241 comprises four image composing circuits C₁-C₄, the second-layer image merging section 242 comprises two image composing circuits C₅and C₆, and the third-layer image composing section 243 comprises one image merging circuit C₇. The image composing circuits C_i(1≦i≦7) have identical configurations.
In the first-layer image composing section 241, the first image composing circuit C₁composes the sub-images generated by the first node computer 241 and the second node computer 242 after being synchronized each other. Likewise, the sub-images generated by the third node computer 243 and the fourth node computer 244 are composed in the second image composing circuit C₂, the sub-images generated by the fifth node computer 245 and the sixth node computer 246 are composed in the third image composing circuit C₃, and the sub-images generated by the seventh node computer 247 and the eighth node computer 248 are composed in the fourth image composing circuit C₄.
In the second-layer image composing section, the sub-images output from the first image composing circuit C₁and the second image composing circuit C₂are composed in the fifth image composing circuit C₅, while the sub-images output from the third image composing circuit C₃and the fourth image composing circuit C₄are composed in the sixth image composing circuit C₆.
In the third-layer image composing section, the sub-images output from the fifth image composing circuit C₅and the sixth image composing circuit C₆are composed by the seventh image composing circuit C₇.
Hereafter, the sub-image composing method to be employed in the image composing apparatus of the present invention will be described.
FIG. 10 is a diagram for explaining how an image space is partitioned into eight subspaces V₁to V₈. The sub-image for the respective subspace V_iis generated by each of the node computers 231 to 238. The number of subspaces is not specifically limited, but to make effective use of the image merging circuits, it will be advantageous to divide the image space into a plurality of subspaces, in particular, 2³ⁿsubspaces (where n is a positive integer).
FIG. 11 is a binary space partitioning tree representation of the subspaces, showing the arrangement of the subspaces Vi as viewed from the viewpoint.
Because the image I₁corresponding to the subspace V₁is closest to the viewpoint, priority “1” is assigned, and other priorities are assigned in the order of the images I₃, I₂, I₄, I₆, I₈, I₅and I₇. The priority can be determined by discriminating the sign of
a _m X _e +b _m Y _e +c _m Z _e +d _m
with respect to the planes separating the respective subspaces. Here, (X_e, Y_e, Z_e) are the coordinates of the viewpoint, and (a_m, b_m, c_m, d_m) are the coefficients determined according to the planes separating the respective subspaces.
FIG. 12 is a diagram for explaining how the sub-images I₁to I₈are composed. The eight sub-images I₁to I₈can be composed by iteratively composing two sub-images in consideration of the fact that higher priority is given to the sub-images closer to the viewpoint.
According to the image composing apparatus of the present invention, each sub-image is given priority instead of the Z value, and image composing circuits for composing two sub-images in consideration for the priority are arranged in a layered structure to obtain high-speed image composition and high expandability.
FIG. 13 is a diagram showing the configuration of each image composing circuit C_i, which comprises a comparator 131, a resistor 132, an interchanger 133, a composer 134, and a delay 135.
The comparator 131 compares the two priority values P_Xand P_Ytransferred from the synchronization circuit or the image merging circuits at the preceding stage, controls the interchanger 133 based on the result of the comparison, and outputs the smaller priority value (higher priority) as P_Zthrough the resistor 132.
Based on the result of the comparison from the comparator 131, the interchanger 133 interchanges the two pixel data I_Xand I_Ytransferred from the synchronization circuit or the image merging circuits at the preceding stage.
For example, when the value of the set priority P_Yfor the sub-image I_Yis smaller than the value of the set priority P_Xfor the sub-image I_X, that is, when the sub-image I_Yis given higher priority, cross paths are selected, and the sub-images I_Xand I_Yare set as follows.
I_Y→I_A
I_X→I_B
Conversely, when the value of the set priority P_Yfor the sub-image I_Yis larger than the value of the set priority P_Xfor the sub-image I_X, that is, when the sub-image I_Xis given higher priority, then straight paths are selected, and the sub-images I_Xand I_Yare set as follows.
I_X→I_A
I_Y→I_B
The composer 134 generates composed pixel data I_Zby composing the two pixel data I_Aand I_Bin accordance with the composing equation shown below. $\begin{matrix} I {(R, G, B)}_{z} = I {(R, G, B)}_{A} + {I (α)}_{A} * + I {(R, G, B)}_{B} \\ I {(α)}_{z} = I {(α)}_{A} * I {(α)}_{B} \end{matrix}$
where I(R,G,B)_Zis the red, green, and blue component data of the composed pixel data I_Z, and I(α)_Zis the transparency of the composed pixel data I_Z.
Finally, the composite pixel data I_Zis generated by storing I(R,G,B)_Zin No. 31-8 bits and I(α)_Zin No. 7-0 bits, and is output.
The high four bits of the 36-bit pixel data are set to “1” for denoting that the data is pixel data, and the bits to be processed by the interchanger 133 and the composer 134 are the low 32 bits. Therefore, the high four bits are directly transferred through the delay 135 to the output side of the composer 134 and combined with the output of the composer 134 to reproduce the 36-bit pixel data. The delay time of the delay is set equal to the processing time required in the interchanger 133 and the composer 134.
As described above, the seven image composing circuits are arranged in three layers and the eight sub-images are composed to one image.
However, as the pixel data and the priority value are separately processed in each image composing circuit in the image composing circuit in the first-layer-third-layer, the pixel data and the priority value are also separately output from the image composing circuit C₇in the third-layer image composing section 243.
Therefore, to standardize the configuration of the image composing apparatus of the present invention, the image combing circuit 244 (FIG. 3) arranged at the final stage of the image composing apparatus adds the frame start and the frame sense at the head of the pixel data output from the image merging circuit C₇and the frame end at the tail of the data to reconstruct the data format shown in FIG. 8. Further, the priority set determined based on the priority value output from the image merging circuit C₇is added in the front of the frame data.
By applying the above configuration, the image composing apparatus of the present invention (in the above embodiment, the apparatus for composing eight sub-images into one image) produces the output frame of the same format as the input frame, and it becomes possible to increase the number of images to be composed by arranging the above image composing apparatuses in a layered structure.
FIG. 14 is a configuration of a multi-layer sub-image composing apparatus constructed by arranging 8-input and 1-output image composing apparatuses in a layered structure. When the number of sub-images to be input is denoted by N, the number of layers S is given by the following equation.
S=Ceil(log₂ N)
While the above description has dealt with an image composing apparatus for composing sub-images electrically, a plurality of display devices may be arranged side by side and the sub-images may be composed visually by displaying the outputs of the synchronizing section directly on the respective display apparatuses and thus operating the plurality of display devices as a single display apparatus.
According to the image composing apparatus and method of the present invention, as the sub-images are composed based on the occlusion relationship between them, it becomes possible to easily cope with an increase in the number of sub-images to be merged.

Claims

1. An image composing apparatus for merging a plurality of subspace images into a single image, comprising:

a subspace image input means for receiving said plurality of subspace images via a plurality of subspace image transmitting lines in parallel;

a synchronizing means for synchronizing said plurality of subspace images received at said subspace image input means; and

an image merging means for processing said plurality of subspace images synchronized by said synchronizing means in parallel to merge said plurality of subspace images into a single image.

2. An image composing apparatus as claimed in claim 1, wherein said synchronizing means comprises:

a plurality of FIFO memories for storing said plurality of subspace images and outputting said stored subspace images in the order in which said subspace images were stored; and

a control means for generating an instruction that causes said plurality of FIFO memories to output said stored subspace images in the order in which said subspace images were stored when a head of a last one of said subspace images arrives at one of said FIFO memories.

3. An image composing apparatus as claimed in claim 1, wherein said subspace image merging means merges said plurality of subspace images based on priorities indicating an occlusion relationship between said plurality of subspace images.

4. An image composing apparatus as claimed in claim 3, wherein said priorities are expressed in a form of a binary space-partitioning tree.

5. An image composing apparatus as claimed in claim 3, wherein said subspace images respectively include data indicating said priorities for every frame.

6. An image composing method for merging a plurality of subspace images into a single image, comprising:

a subspace image input step for receiving said plurality of subspace images via a plurality of subspace image transmitting lines in parallel;

a synchronizing step for synchronizing said plurality of subspace images received at said subspace image input step; and

an image merging step for processing said plurality of subspace images synchronized at said synchronizing step in parallel to merge said plurality of subspace images into a single image.

7. An image composing method as claimed in claim 6, wherein said synchronizing step comprises:

a FIFO storing step for storing said plurality of subspace images and outputting said stored subspace images in the order in which said subspace images were stored; and

a FIFO output step for generating an instruction that causes outputs of said plurality of subspace images stored at said FIFO storing step in the order in which said subspace images were stored when a head of a last one of said subspace images arrives.

8. An image composing method as claimed in claim 6, wherein at said subspace image merging step, said plurality of subspace images are merged based on priorities indicating an occlusion relationship between said plurality of subspace images.

9. An image composing method as claimed in claim 8, wherein said priorities are expressed in a form of a binary space-partitioning tree.

10. An image composing method as claimed in claim 8, wherein said subspace images respectively include data indicating said priorities for every frame.