JPH071876B2 - Decoding device for BCH code - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BCH code decoding device, and more particularly, to a decoding device for obtaining an error location polynomial and an error evolution polynomial using the Euclidean algorithm.

[Background Art and its Problems] An outline of the decoding method of the Reed-Solomon code, which is one of the BCH codes, will be described. Here, the code length is n, the number of information symbols is k, and the minimum distance d is (n−k + 1 = 2t +
1) and the generator polynomial is The Reed-Solomon code (correction of t symbols) on GF (2 ^m ) will be described.

First received word _{(r 0, r 1, r} 2, ... r n-1) from the syndrome Sj (j = 0,1, ... d -2) obtained.

Next, using the syndrome, the error location polynomial σ (z) and the error evolution polynomial ω (z)
Ask for. As one of the methods, there is a method using Euclid's mutual division method.

Obtained error location polynomial (σ (z) = 0)
Solve to find the error location Xi. Then, the error location Xi and the error evaluation polynomial ω
The error value Yi is obtained from (z).

The error location polynomial σ (z) and the error evolution polynomial ω (z) described above are Euclidean mutual division methods for finding the greatest common divisor polynomial of z ^2t and S (z), where S (z) is a syndrome polynomial. It has been proved that it can be found in the process. This is the next algorithm.

First, the initial value in the register And set. The following operations are performed on these polynomials to obtain ri (z) and Ui (z).

r _i-2 (z) ÷ r _i-1 (z) = qi (z) ... r _i (z) Ui (z) = U _i-2 (z) + U _i-1 (z) qi (z) however, than the degree of r _i (z), the degree of r _i-1 (z) is large. This calculation is repeated, and when the order of r _i (z) becomes smaller than t, the calculation is stopped. At this time, the error location polynomial σ (z) and the error evaluation polynomial ω (z) are obtained by the following equation.

σ (z) = Ui (z) / Ui (0) ω (z) = ri (z) / Ui (0) A conventional decoder for implementing the above algorithm is
The shift operation of the register was necessary. As hardware for performing a shift operation, a configuration is known in which a plurality of registers are connected to a data bus, data is taken out from the register to be shifted to the data bus, and is written in an adjacent register. This method has a drawback in that steps are required as many as the number of registers to be shifted. As other hardware, a data selector is inserted between the stages of a plurality of registers so that the data from the data bus and the data from the register of the previous stage can be selected by the data selector. There is a configuration that selects data from a register. According to this hardware, the shift operation can be performed in one step, but the data selector causes a problem that the scale of the hardware becomes large. For these reasons, in implementing the decoder,
It is preferable that no shift operation is required.

"Object of the Invention" An object of the present invention is to provide a decoding device for a BCH code which does not require a shift operation of a register. According to the present invention, the hardware of the decoder can be simplified and the decoding speed can be improved.

SUMMARY OF THE INVENTION The present invention relates the contents of the first and second register groups to the dividend and divisor, and uses the contents of the first and second register groups by the Euclidean algorithm to calculate the error location polynomial In a BCH code decoding device configured to obtain an error evaluation polynomial, the values of the respective registers of the first and second register groups are supplied to perform a product-sum operation, and an operation means for writing the operation result into the register. Of the register group, indicating means for indicating the position of the boundary, zero detecting means, first and second register groups, calculating means, and control means for controlling the operation of the indicating means. As the initial value of the first register group (1,100 ... 00)
(However, indicates the position of the boundary between U and r), and sets (00, S (z)) as the initial value of the second register group (however, indicates the boundary between U and S (z). Position (S (z) indicates a syndrome polynomial), (a) the register on the right side of the boundary position in each register group is divided, and (b) on the right side of the boundary position, one register group is set. The value of the register of is multiplied by the division result, the value added to the value of the other corresponding register is written to the other register, and (c) on the left side of the boundary position, the value of the register of the other register group is divided. The result is multiplied and the value added to the value of the corresponding one register is written in the one register. (D) It is detected by the zero detection means that the value of the register on the right side of the boundary position becomes 0. Then the position of the boundary up to a non-zero position Shifting to the right, a decoder for BCH codes, characterized in that repeating the process of (a) to (d).

[Embodiment] A decoding process according to an embodiment of the present invention will be described below. In this embodiment, (t = 3), the present invention is applied to a Reed-Solomon code on GF (2 ⁴ ).

In FIG. 1, 31 indicates a register group consisting of (2t + 2 = 8) registers of 4 bits each, and 32 indicates a register group consisting of 8 registers of 4 bits each. The contents of each register of these register groups 31 and 32 are supplied to the arithmetic circuit of GF (2 ⁴ ) via the bus buffer and the data bus, and the arithmetic result is supplied to each register via the data bus and the bus buffer. It

FIG. 1A shows a state where initial values are set in the register groups 31 and 32. α is the root of (x ⁴ + x + 1 = 0), and (α
¹⁵ = 1), and 0 and 1 are the zero element and the identity element on GF (2 ⁴ ), respectively. In the register group 31, as an initial value,
(U _o (z) = 1, _r-1 (z) = z ⁶ ) That is, (1,1000000) is set. In the register group 32, (U _-1
(Z) = 0, S (z) is set. The comma "," is
Data position information, which is the register group in the initial state
The comma in 31 represents the boundary between U and r, and the comma in register group 32 represents the boundary between U and S (z). In the example shown in FIG. 1, the following is assumed as an example of the syndrome polynomial.

r ₀ (z) = S (z) = α ⁷ z ⁵ + α ⁷ z ⁴ + α ¹¹ z ³ + α ¹¹ z ² + α ¹⁴ z + α ⁴ Using the Euclidean algorithm, the error location polynomial σ (z) and the error evalu Ace polynomial ω
To obtain (z), (r _i-2 (z) ÷ r _i-1
Calculation of (z) = qi (z) ... ri (z) is performed.

r _-1 (z) ÷ r ₀ (z) = q ₁ (z) ... r ₁ (z) q ₁ (z) = α ⁸ z + α ⁸ r ₁ (z) = α z ⁴ + α ³ z ² + α ² z + α ¹² r ₀ (z) ÷ r ₁ (z) = q ₂ (z) …… r ₂ (z) q ₂ (z) = α ⁶ z ⁶ + α ⁶ r ₂ (z) = α ² z ³ + z ² + α ² z + α ⁷ r ₁ (z) ÷ r ₂ (z) = q ₃ (z) …… r ₃ (z) q ₃ (z) α ¹⁴ z + α ¹² r ₃ (z) = α ⁸ z ² + z + α ⁶ This operation Can be represented by a calculation as shown in FIG. Since the degree of r ₃ (z) is smaller than (t = 3), the above calculation is completed at this stage.

In addition, as shown below, (Ui (z) = U _i-2 (z) + U
_i-1 (z) qi (z)) is calculated.

U ₁ (z) = U ₋₁ (z) + U ₀ (z) q ₁ (z) = α ⁸ z + α ⁸ U ₂ (z) = U ₀ (z) + U ₁ (z) q ₂ (z) = α ¹⁴ z ² + α ³ U ₃ (z) = U ₁ (z) + U ₂ (z) q ₃ (z) = α ¹³ z ³ + α ¹¹ z ² + z + α ² and σ (z) = U ₃ (z) / U ₃ (0) = U ₃ (z) / α ² = α ¹¹ z ³ + α ⁹ z ² + α ¹³ z + 1 ω (z) = r ₃ (z) / U ₃ (0) = r ₃ (z) / α ^The error location polynomial σ (z) and the error evolution polynomial ω (z) are obtained by ² = α ⁶ z ² + α ¹³ z + α ⁴ .

The register groups 31 and 32 are used to obtain the above-mentioned ri (z) and Ui (z). The contents of each register of the register group 31 are T ₀ , T ₁ , T ₂ , ... T ₇ in order from the right side, and the contents of each register of the register group 32 are B ₀ , B ₁ , B ₂ ,
And ...... B _7.

As shown in FIG. 1A, after setting the initial values in the registers, the contents of the registers T ₆ and B ₅ on the right side of the comma positions of the register groups 31 and 32 are supplied to the arithmetic circuit for division. The value of A is calculated and held. In FIG. 1A, (A = 1 ÷
α ⁷ = α ⁸ ). The content of each register of the register group 32 is multiplied by this A, the content Ti of the corresponding register (upper register) of the register group 31 is added to the multiplication output, and this addition output is written to the register group 31. In the rightmost pair of registers T ₁ and B ₀ in FIG. 1A, 0 and α ⁴ are supplied to the arithmetic circuit, and (α ³ × α ⁴ + 0 = α ¹² ) is obtained, which is shown in FIG. 1B. As shown in, the second register from the right end of the register group 31
Written to T ₁ . That is, assuming that the difference between the comma positions of the register groups 31 and 32 is a, the register group 31 has (Ti + A
The result of (× Bi _−a ) or (Ti + A × Bi _{+ a} ) is written in the register Ti.

Also, from the left end of the register group 31 to the comma position,
The calculation of (B _i + A × T _{i + a} ) is performed by the calculation circuit, and the output is set in the register B _i of the register group 32. Therefore, as shown in FIG. 1B, α ⁸ is set to B ₆ . The position of the comma is shifted to a position other than 0 when the content of the register on the right side of the comma becomes 0. The position of the comma is indicated by the counter. In the state shown in FIG. 1B, T ₅ and B ₅ are supplied to the arithmetic circuit to obtain (A = 1 ÷ α ⁷ = α ⁸ ), and the same arithmetic operation and register rewriting as described above are performed. Then, as shown in FIG. 1C, r ₁ (z) and
U ₁ (z) is required.

Then, again, a division operation similar to the division operation performed in the order of FIG. 1A, FIG. 1B, and FIG. 1C is performed as shown in FIG. 1C, FIG. 1D, and FIG. 1E. Done. Here, as shown in FIG. 1C, since the comma positions of the register groups 31 and 32 are reversed, the contents of each register of the register group 31 are set to Bi, and the contents of each register of the register group 32 are set to Bi. The contents are treated as Ti and processed. Therefore, in the state of FIG. 1C, T ₅ and
B ₄ is supplied to the arithmetic circuit to obtain (A = α ⁷ ÷ α = α ⁶ ). Also, the rightmost pair of registers T _{1 in} FIG.
And B ₀ , α ¹⁴ and α ¹² are supplied to the arithmetic circuit, and α ¹²
× α ⁶ + α ¹⁴ = 1 is obtained, and register T of register group 32
Written to ₁ . On the left side of the comma, (B _i + A × T _{i + a} ) is obtained by the arithmetic circuit, and the output is written in B _{i of the} register group 31. Thereafter, the second division is completed in the state shown in FIG. 1E, and r ₂ (z) and U ₂ (z) are obtained. The contents of the register groups 31 and 32 correspond to the calculation process shown in FIG.

FIGS. 1E, 1F and 1G show the contents of the register groups 31 and 32 when the third division operation is performed.
R ₃ (z) and U ₃ (z) are obtained as shown in. This time,
From the comma position of the register group 31, it is detected that the order of r ₃ (z) is smaller than (t = 3), and from the contents of the register groups 31 and 32, as described above, the error location polynomial and An error evaluation polynomial can be obtained.

That is, the value of the rightmost third register of the register group 31 represents r ₃ (z), the value of the leftmost register of the register group 32 represents U ₃ (0), and the value of the register group 32 is The value of the register from the leftmost position to the comma position represents U ₃ (z), and the equations σ (z) = U ₃ (z) / U ₃ (0) and ω (z) = r ₃ ( The error location polynomial σ (z) and the error evaluation polynomial ω (z) are obtained by calculating z) / U ₃ (0).

FIG. 3 shows the configuration of the Reed-Solomon code decoder according to the embodiment of the present invention.

In FIG. 3, 1,2,3,4,5,6,7,8 denote 4-bit registers, respectively, and the registers 1 to 8 form a register group 31. Similarly, each 4-bit register
A register group 32 is configured by 9,10,11,12,13,14,15,16. Each of the registers is connected to the data bus 17 via a bidirectional bus buffer. To the data bus 17, a GF (2 ⁴ ) operation circuit 18 and a zero detection circuit 19 are connected. The zero detection circuit 19 generates detection data for shifting the position of the comma.

Reference numeral 20 is a counter that generates an output corresponding to the comma position of the register group 31, and 21 is a counter that generates an output corresponding to the comma position of the register group 32. Counter 20
The outputs of 21 and 21 are supplied to the arithmetic circuit 22, and the counter 20 and
Each of the outputs of 21 is supplied to comparison circuits 23 and 24. The subtraction circuit 22 is for detecting the positional relationship between the commas of the two register groups 31 and 32. The comparison circuits 23 and 24 are
This is for detecting that the order of the remainder r _i (z) is smaller than t from the position of the comma of the register groups 31 and 32.

The outputs of the zero detection circuit 19, the subtraction circuit 22, and the comparison circuits 23 and 24 are supplied to the ROM 25 for specifying the jump destination. The control signals for controlling the registers 1 to 16 and the bus buffers added to the registers 1 to 16 and the arithmetic circuit 18 are generated by decoding the microinstructions read from the program ROM 26 by the command decoder 27. To do. An address is supplied from the program counter 28 to the program ROM 26. The program counter 28 is supplied with the jump address from the ROM 25 for specifying the jump destination. The output of the zero detection circuit 19 or the like is used as the condition data for generating the jump address.

[Advantages of the Invention] According to the present invention, the setting of the initial value is made different from the conventional one so that the register shift operation is not performed.
An error location polynomial and an error evolution polynomial can be obtained. Therefore, according to the present invention, it is possible to solve the problems that the circuit scale of the decoder becomes large and the number of steps for decoding increases.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing changes in the contents of a register used for explaining one embodiment of the present invention, and FIG. 2 is a schematic diagram showing an arithmetic process used for explaining one embodiment of the present invention. FIG. 3 is a block diagram of an example of a decoder to which the present invention is applied. 17 ... Data bus, 18 ... Arithmetic circuit, 26 ... Program
ROM, 31,32 ... Registers.

Claims (1)

[Claims] 1. An error location polynomial and an error evaluation are performed by making the contents of the first and second register groups correspond to a dividend and a divisor, and using the contents of the first and second register groups by Euclidean mutual division method. In a BCH code decoding device for obtaining a polynomial, the values of the respective registers of the first and second register groups are supplied to perform a product-sum operation, and operation means for writing the operation result into the register, And a zero detecting means, the first and second register groups, the computing means, and a control means for controlling the operation of the instructing means. The control means sets (1,100 ... 0) as an initial value of the first register group.
0) (however, indicates the position of the boundary between U and r) and sets (00, S (z)) as the initial value of the second register group.
(However ,, indicates the position of the boundary between U and S (z), and S
(Z) indicates the syndrome polynomial), (a) divides the value of the register on the right side of the boundary position in each register group, and (b) registers of one register group on the right side of the boundary position. Is multiplied by the above division result, and the value obtained by adding to the value of the other corresponding register is written to the other register. (C) On the left side of the boundary position, the value of the register of the other register group is added to the above value. A value obtained by multiplying the result of division and adding the value of the corresponding one register to the one register, and (d) the value of the register on the right side of the boundary position becomes 0 by the zero detecting means. 0 when detected
An apparatus for decoding a BCH code, characterized in that the position of the boundary is shifted to the right to a position other than that, and the processes of (a) to (d) are repeated.