JPH071866B2 - Resistive coupling type Josephson logic circuit - Google Patents
Resistive coupling type Josephson logic circuitInfo
- Publication number
- JPH071866B2 JPH071866B2 JP59200215A JP20021584A JPH071866B2 JP H071866 B2 JPH071866 B2 JP H071866B2 JP 59200215 A JP59200215 A JP 59200215A JP 20021584 A JP20021584 A JP 20021584A JP H071866 B2 JPH071866 B2 JP H071866B2
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- Japan
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- circuit
- resistance
- input
- output
- coupling type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はジョセフソン素子を用いた回路、特に複数個の
信号の論理和を取る回路に関するもので、入出力信号の
結合を除く入出力分離信号波形の整形等にも用いられる
ジョセフソン論理回路に関するものである。Description: TECHNICAL FIELD The present invention relates to a circuit using a Josephson element, and more particularly to a circuit for taking a logical sum of a plurality of signals, which is an input / output separation device except for coupling of input / output signals. The present invention relates to a Josephson logic circuit also used for shaping a signal waveform.
（従来技術とその問題点） ジョセフソン素子と抵抗とを用いたジョセフソン論理和
回路として、特開昭56-30778号、特開昭57-4622号、特
開昭58-46727号および米国特許第4275314号等に記載さ
れている抵抗結合型論理回路がある。これらの回路は、
注入された入力信号電流により所望の論理を行い、出力
回路に電流を送出する回路である。ところで従来の上記
回路は、入力電流と出力電流の比即ち信号感度、動作速
度、動作領域、回路構成、素子寸法において、それぞれ
差異がある。(Prior Art and Its Problems) As a Josephson OR circuit using a Josephson element and a resistor, Japanese Patent Laid-Open Nos. 56-30778, 57-4622, 58-46727 and US Pat. There is a resistance coupling type logic circuit described in Japanese Patent No. 4275314. These circuits are
It is a circuit that performs a desired logic by the injected input signal current and sends the current to the output circuit. By the way, the above-mentioned conventional circuits differ from each other in the ratio of the input current and the output current, that is, the signal sensitivity, the operating speed, the operating region, the circuit configuration, and the element size.
これらの抵抗結合型論理和回路の中で特開昭58-46727号
に開示されている回路は、ターンオン時間が他の回路に
比して小さく（曽根、信学技報ED83-51,第83巻，第100
号，第39頁、1983年８月発行）、信号感度、動作領域に
関しても他の回路より優れている。第３図は、特開昭58
-46727号に開示されている抵抗結合型論理和回路の一列
を示したものである。この回路は、抵抗401〜405と、入
出力分離用ジョセフソン素子411及びスイッチング用ジ
ョセフソン素子412,413とから構成される。ゲート電流
は端子421から抵抗405を介して与えられる。入力線422
に入力信号が加えられるとジョセフソン素子412,413,41
1が順次スイッチオンし、出力線423に出力が現れる。Among these resistance-coupling type OR circuits, the circuit disclosed in Japanese Patent Laid-Open No. 58-46727 has a smaller turn-on time than other circuits (Sone, IEICE Technical Report ED83-51, No. 83). Volume, 100
No., page 39, issued in August 1983), it is superior to other circuits in terms of signal sensitivity and operating range. FIG.
1 shows a line of the resistance-coupling type OR circuit disclosed in No. 46727. This circuit is composed of resistors 401 to 405, an input / output separation Josephson element 411 and switching Josephson elements 412, 413. The gate current is given from the terminal 421 through the resistor 405. Input line 422
When an input signal is applied to the Josephson device 412,413,41
The 1's are sequentially switched on and the output appears on the output line 423.
しかし、第３図に示した従来の抵抗結合型論理和回路
は、回路素子数が多く、回路の大きさが小さくできない
という問題があった。さらに、実際の回路パターン形状
からも回路の大きさが制約されていた。即ち、基部電極
層、抵抗体層、絶縁体層、対向電極層の各層間の製造上
の位置合せ精度の制約から、パターンの合せ部分が必要
であり、その形成のためにある程度のスペースを要す
る。第３図に示した抵抗結合型論理和回路のパターン図
を第４図に示す。回路パターンは、抵抗パターン501,50
2と、基部電極511〜516と接合窓521〜523と対向電極53
1,532と、図には示されていないが、接地面、接地用コ
ンタクト、接地面と基部電極間絶縁層などからなってい
る。第３図の抵抗401〜405は、基部電極にはさまれた抵
抗部541〜545で形成され、ジョセフソン素子411〜413は
接合窓521〜523にそれぞれ対応している。基部電極511
は信号入力端子、基部電極513は出力端子、基部電極516
はゲート電流注入端子、基部電極515は接地端子であ
る。However, the conventional resistance-coupling type OR circuit shown in FIG. 3 has a problem that the number of circuit elements is large and the circuit size cannot be reduced. Furthermore, the size of the circuit is restricted by the actual circuit pattern shape. That is, the pattern alignment portion is required due to the limitation of the manufacturing alignment accuracy among the base electrode layer, the resistor layer, the insulator layer, and the counter electrode layer, and a certain amount of space is required for its formation. . A pattern diagram of the resistance-coupling type OR circuit shown in FIG. 3 is shown in FIG. Circuit pattern is resistance pattern 501, 50
2, base electrodes 511 to 516, bonding windows 521 to 523, and counter electrode 53
1,532, which is not shown in the figure, is composed of a ground plane, a ground contact, an insulating layer between the ground plane and the base electrode, and the like. Resistors 401 to 405 in FIG. 3 are formed by resistance portions 541 to 545 sandwiched by base electrodes, and Josephson elements 411 to 413 correspond to junction windows 521 to 523, respectively. Base electrode 511
Is a signal input terminal, base electrode 513 is an output terminal, base electrode 516
Is a gate current injection terminal, and the base electrode 515 is a ground terminal.
このように第３図に示す従来の抵抗結合型回路では、素
子数が多いこと及び、そのための層間の合せ余裕を必要
とする、という理由から回路の小型化高集積化には限界
があった。As described above, the conventional resistance-coupling circuit shown in FIG. 3 has a limit in miniaturization and high integration of the circuit because of the large number of elements and the need for a margin for alignment between layers. .
また、接合窓522と接合窓523の間隔551が小さくならな
い。Further, the gap 551 between the joining window 522 and the joining window 523 does not become small.
（発明の目的） 本発明の目的は、上記した抵抗結合型論理和回路の欠点
を除き、回路の小型化高集積化を図ることにある。(Object of the Invention) An object of the present invention is to reduce the size of the circuit and to increase the degree of integration, except for the above-mentioned drawbacks of the resistance-coupling type OR circuit.
（発明の構成） 本発明は抵抗と一方の端が接地されたジョセフソン素子
とを直列接続した３個以上の回路枝と、前記回路枝の抵
抗の他端を互いに接続した接続点にゲート電流を注入す
る手段と、前記回路枝のいずれか１個の回路枝の抵抗と
ジョセフソン素子の接合点に接続された入出力分離ジョ
セフソン素子と、前記入出力分離ジョセフソン素子の他
端に接続された信号入力線と、前記信号入力線と前記入
出力分離ジョセフソン素子の結合点に接続され他端が接
地された入力抵抗と、前記回路枝のいずれか１個の回路
枝から出力信号を取り出す手段とから構成され、前記信
号入力線に電流を注入して前記出力手段に出力信号を発
生させるように構成したことを特徴とする抵抗結合型ジ
ョセフソン論理回路である。(Structure of the Invention) The present invention relates to a gate current at three or more circuit branches in which a resistor and a Josephson element whose one end is grounded are connected in series, and a connection point where the other ends of the resistors of the circuit branches are connected to each other. Means for injecting, an input / output isolation Josephson element connected to a junction point between the resistance of any one of the circuit branches and the Josephson element, and connected to the other end of the input / output isolation Josephson element A signal input line, an input resistor connected to the connection point of the signal input line and the input / output separation Josephson element and the other end of which is grounded, and an output signal from any one of the circuit branches. And a take-out means for injecting a current into the signal input line to generate an output signal at the output means.
（実施例） 以下に本発明の実施例を図によって説明する。(Example) Below, the Example of this invention is described by figures.
（実施例１） 第１図は本発明の第一の実施例を示す図である。本発明
による抵抗結合型ジョセフソン論理回路は、一方の端が
接地されたスイッチング用ジョセフソン素子101,102,10
3と、抵抗111,112,113がそれぞれ直列接続された回路枝
と、ジョセフソン素子101と抵抗111との接合点に接続さ
れた入出力分離のためのジョセフソン素子104と、一方
の端が接地された入力抵抗114とから構成されている。
回路へのゲート電流は、端子121に接続された電源から
抵抗115を介して注入される。入力信号は信号入力線122
から入力され、ジョセフソン素子101,102,103,104を順
次電圧状態へスイッチオンさせる。ジョセフソン素子10
1〜104のスイッチオンにより、信号出力線123へゲート
電流が流れて出力信号が得られる。回路がスイッチオン
した時、入力信号と出力信号とは、ジョセフソン素子10
4がスイッチオンしているので互いに干渉せず、入出力
信号の分離が行なわれる。この時入力信号電流は、入力
抵抗114へ流れ込む。第１図に示す抵抗結合型回路の抵
抗111,112,113の抵抗値R1，R2，R3は、第３図に示す従
来の抵抗結合型回路の抵抗402〜404の抵抗値r1〜r3に対
して次式の値に設定し、抵抗値R3の値をほぼ抵抗値R2の
値とほぼ等しくすると、本発明の回路は第３図の回路よ
り出力電流の値がおよそ５割増加したような特性を示
す。即ち本発明の回路の電気的性能は従来の回路と同様
である。(Embodiment 1) FIG. 1 is a diagram showing a first embodiment of the present invention. The resistance-coupling type Josephson logic circuit according to the present invention has a switching Josephson element 101, 102, 10 whose one end is grounded.
3, a circuit branch in which resistors 111, 112 and 113 are respectively connected in series, a Josephson element 104 for input / output separation connected to a junction point between the Josephson element 101 and the resistor 111, and an input whose one end is grounded. It is composed of a resistor 114.
Gate current to the circuit is injected through resistor 115 from a power source connected to terminal 121. Input signal is signal input line 122
Input, and the Josephson devices 101, 102, 103, 104 are sequentially switched on to the voltage state. Josephson element 10
When the switches 1 to 104 are turned on, a gate current flows through the signal output line 123 and an output signal is obtained. When the circuit is switched on, the input and output signals are
Since 4 is switched on, the input and output signals are separated without interfering with each other. At this time, the input signal current flows into the input resistor 114. The resistance values R 1 , R 2 and R 3 of the resistances 111, 112 and 113 of the resistance coupling type circuit shown in FIG. 1 are set to the resistance values r 1 to r 3 of the resistances 402 to 404 of the conventional resistance coupling type circuit shown in FIG. On the other hand, when the value of the resistance value R 3 is set to be substantially equal to the value of the resistance value R 2 by setting the value of the following equation, the circuit of the present invention increases the output current value by about 50% from the circuit of FIG. It shows such characteristics. That is, the electrical performance of the circuit of the present invention is similar to conventional circuits.
第１の実施例では、従来の第３図の抵抗結合型論理和回
路の抵抗404に相当する部分の抵抗が除かれている。 In the first embodiment, the resistance of the portion corresponding to the resistance 404 of the conventional resistance-coupling type OR circuit of FIG. 3 is removed.
第１の実施例の抵抗結合型論理和回路のパターン図を第
２図に示す。従来例の回路のパターン図第４図とほぼ同
様に、第１図の実施例の回路は、抵抗パターン201,202
と、基部電極211〜217と、接合窓221〜224と、対向電極
231,232と、図には示されていないが、接地面、接地用
コンタクト、接地面に対する絶縁層などから構成されて
いる。第１の実施例の抵抗111〜114は、基部電極にはさ
まれた抵抗部241〜244で形成され、ジョセフソン素子10
1〜104は、接合窓221〜224の所に形成される。基部電極
211は信号入力線122、基部電極214は信号出力線123、基
部電極216はゲート電流入力端子121、基部電極217は接
地端子に対応する。第１の実施例においては、接合窓22
1と接合窓222の間隔251は、抵抗素子が除かれたことに
より、抵抗素子の部分だけでなく、基部電極との接触部
分も小さくなったため、第４図に示す従来例の1/3に短
縮された。しかも、抵抗R1，R2が小さくなったので、抵
抗部241,242も小さくなり、回路全体を小形化できる。
また、接合窓222と接合窓223の間隔252も間隔251と同様
に短縮され、抵抗R3も抵抗R1，R2と同様小型化が図られ
る。FIG. 2 shows a pattern diagram of the resistance coupling type OR circuit of the first embodiment. A pattern diagram of the circuit of the conventional example. Similar to FIG. 4, the circuit of the embodiment of FIG.
, Base electrodes 211-217, bonding windows 221-224, and counter electrodes
231, 232, and a ground plane, a ground contact, and an insulating layer for the ground plane, which are not shown in the figure. The resistors 111-114 of the first embodiment are formed by the resistor parts 241-244 sandwiched between the base electrodes, and the Josephson device 10
1 to 104 are formed at the bonding windows 221-224. Base electrode
Reference numeral 211 corresponds to the signal input line 122, base electrode 214 corresponds to the signal output line 123, base electrode 216 corresponds to the gate current input terminal 121, and base electrode 217 corresponds to the ground terminal. In the first embodiment, the bonding window 22
The distance 251 between 1 and the bonding window 222 is reduced to 1/3 of that of the conventional example shown in FIG. 4 because not only the resistance element portion but also the contact portion with the base electrode is reduced by removing the resistance element. It was shortened. Moreover, since the resistances R 1 and R 2 are reduced, the resistance portions 241 and 242 are also reduced, and the entire circuit can be downsized.
Further, the distance 252 between the bonding window 222 and the bonding window 223 is also shortened in the same manner as the distance 251 and the resistance R 3 is also downsized similarly to the resistances R 1 and R 2 .
（発明の効果） 以上本発明の抵抗結合型ジョセフソン論理回路によれ
ば、従来の回路に対して、回路特性を下げることなく素
子数を減らすことができ、回路の小形化、高集積化を達
成できる効果を有するものである。(Effects of the Invention) As described above, according to the resistance-coupling type Josephson logic circuit of the present invention, the number of elements can be reduced as compared with the conventional circuit without lowering the circuit characteristics, and the circuit can be downsized and highly integrated. It has an achievable effect.
第１図は、本発明の第１の実施例を示す回路図、第２図
は、第１の実施例の抵抗結合型論理回路の回路パターン
例を示す図、第３図は従来の抵抗結合型論理和回路の回
路図、第４図は、従来の抵抗結合型論理和回路の回路パ
ターン例を示す図である。 101,102,103:スイッチング用ジョセフソン素子、104:入
出力分離用ジョセフソン素子、111〜113,115:抵抗、11
4:入力抵抗、121:ゲート電流注入端子、122:信号入力
線、123:信号出力線、201,202:抵抗パターン、211〜21
7:基部電極、221〜224:接合窓、231,232:対向電極、241
〜245:抵抗部、251,252:接合窓の間隔、401〜405:抵
抗、411:入出力分離用ジョセフソン素子、412,413:スイ
ッチング用ジョセフソン素子、421:バイアス電流注入端
子、422:信号入力線、423:信号出力線、511〜516:基部
電極、521〜523:接合窓、531,532:対向電極、541〜545:
抵抗部、551:接合窓の間隔。FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing an example of a circuit pattern of a resistance coupling type logic circuit of the first embodiment, and FIG. 3 is a conventional resistance coupling. FIG. 4 is a circuit diagram of a type logical sum circuit, and FIG. 4 is a diagram showing a circuit pattern example of a conventional resistance coupling type logical sum circuit. 101,102,103: Josephson element for switching, 104: Josephson element for input / output separation, 111 to 113,115: resistor, 11
4: Input resistance, 121: Gate current injection terminal, 122: Signal input line, 123: Signal output line, 201, 202: Resistance pattern, 211-21
7: base electrode, 221-224: bonding window, 231, 232: counter electrode, 241
~ 245: Resistance part, 251, 252: Junction window spacing, 401 ~ 405: Resistance, 411: Input / output separation Josephson element, 412, 413: Switching Josephson element, 421: Bias current injection terminal, 422: Signal input line, 423: signal output line, 511 to 516: base electrode, 521 to 523: bonding window, 531, 532: counter electrode, 541 to 545:
Resistor, 551: Bond window spacing.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−46727（ＪＰ，Ａ) 特開 昭57−132431（ＪＰ，Ａ) Ｅ．Ａ．ギルミン著、山田直平 外５名 訳「回路網基礎学」（昭和34年３月10日) 無線従事者教育協会発行 Ｐ．134−Ｐ. 145 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-58-46727 (JP, A) JP-A-57-132431 (JP, A) E. A. Gilmin, Translated by Naohei Yamada, 5 people, "Basics of circuit network" (March 10, 1959) Published by Wireless Workers Education Association 134-P. 145
Claims (1)
素子とを直列接続した３個以上の回路枝と、前記回路枝
の抵抗の他端を互いに接続した接続点にゲート電流を注
入する手段と、前記回路枝のいずれか１個の回路枝の抵
抗とジョセフソン素子との接合点に接続された入出力分
離ジョセフソン素子と、前記入出力分離ジョセフソン素
子の他端に接続された信号入力線と、前記信号入力線と
前記入出力分離ジョセフソン素子との結合点に接続され
他端が接地された入力抵抗と、前記回路枝のいずれか１
個の回路枝から出力信号を取り出す手段とから構成さ
れ、前記信号入力線に電流を注入して前記出力手段に出
力信号を発生させるように構成したことを特徴とする抵
抗結合型ジョセフソン論理回路。1. A gate current is injected into three or more circuit branches in which resistors and a Josephson element whose one end is grounded are connected in series, and a connection point in which the other ends of the resistors of the circuit branches are connected to each other. Means, an input / output separation Josephson element connected to a junction between a resistance of any one of the circuit branches and a Josephson element, and connected to the other end of the input / output separation Josephson element. Any one of a signal input line, an input resistance connected to a connection point between the signal input line and the input / output separation Josephson element and having the other end grounded, and one of the circuit branches
And a means for taking out an output signal from each of the circuit branches, wherein a current is injected into the signal input line to generate an output signal at the output means. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59200215A JPH071866B2 (en) | 1984-09-25 | 1984-09-25 | Resistive coupling type Josephson logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59200215A JPH071866B2 (en) | 1984-09-25 | 1984-09-25 | Resistive coupling type Josephson logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6178224A JPS6178224A (en) | 1986-04-21 |
| JPH071866B2 true JPH071866B2 (en) | 1995-01-11 |
Family
ID=16420722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59200215A Expired - Lifetime JPH071866B2 (en) | 1984-09-25 | 1984-09-25 | Resistive coupling type Josephson logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071866B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2579058A (en) | 2018-11-16 | 2020-06-10 | Inst Jozef Stefan | Memory device and method for its operation |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57132431A (en) * | 1981-02-09 | 1982-08-16 | Nippon Telegr & Teleph Corp <Ntt> | Superconductive logical gate |
| JPS5846727A (en) * | 1981-09-14 | 1983-03-18 | Nec Corp | Current injection type logical gate circuit using josephson effect |
-
1984
- 1984-09-25 JP JP59200215A patent/JPH071866B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| Ｅ．Ａ．ギルミン著、山田直平外５名訳「回路網基礎学」（昭和３４年３月１０日）無線従事者教育協会発行Ｐ．１３４−Ｐ．１４５ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6178224A (en) | 1986-04-21 |
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