JPH071861B2 - Switch Tokiya Passita Biquadratic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a switched capacitor (SC) wave device and an SC equalizer suitable for LSI implementation and having a small DC offset amount.

(Background Art) With the development of LSIs for various parts, there is a strong demand for LSIs for wave devices and equalizers. As a method that satisfies this condition, there is a method of forming a wave filter or an equalizer using a switched capacitor (hereinafter referred to as SC) by MOS technology, and the following three methods are generally known.

(B) Factor the transfer function into a biquadratic form and use SC
Realized by.

(B) First, design the LC ladder circuit,
Calculate the current relationship. This is realized by an integrating circuit using SC.

(C) Similar to (b), first design an LC ladder circuit, and set the inductor (L) to SC and operational amplifier (OP-AMP).
Realized by.

Each of the above three methods has advantages and disadvantages, but the method (a) that can realize various characteristics by one circuit is most often used, and is constituted by the biquadratic type shown in FIG. In the following, the elements forming the biquadratic circuit are all considered to be ideal elements and the discussion will proceed. Transfer function of the circuit shown in FIG.
T ₁ (Z ^-1 ) is given by the following equation.

Here, D = C ₁ (K ₁ + C ₂ ) + (K ₂ K ₄ + K ₂ K ₃ -C ₁ K ₁ -2C ₁ C ₂ ) Z ^-1 + (C ₁ C ₂ -K ₂ K ₃ ) Z ^-2 N ₁ = C ₁ K ₇ + (K ₂ K ₅ -C ₁ K ₇ -C ₁ K ₈ ) Z ^-1 + (C ₁ K ₇ -K ₂ K ₆ ) Z ^-2 .

In addition, the transfer function T ₂ (Z ^-1 ) from V _in to the output V ₁ of OP-AMP1
Is given by

Where N ₂ = K ₄ K ₇ + K ₃ K ₇ -K ₁ K ₅ -K ₅ C ₂ + (K ₁ K ₆ + C ₂ K ₆ C ₂ K ₅ -K ₄ K ₈ -K ₃ K _{8 ^{-K 3 K 7) Z -1 +}} (K 3 K 8 -C 2 C 6) is Z ^-2.

FIG. 2 shows an RC equivalent circuit when the clock frequency ( _c ) is sufficiently higher than the applied frequency (). The transfer function T ₃ (s) of this circuit is as follows.

Where Y ₁ = sC ₁ , Y ₂ = (1 + sC ₃ R ₄ ) / R ₄ , Y ₃ = 1 / R ₅ , Y ₄ = sC ₄ , Y ₅ = sC ₂ , Y ₆ = 1 / R ₂ , Y ₇ = 1 / R ₇ , Y ₈ = sC ₅ .

Next, the offset will be described. Generally, an offset is roughly classified into one that flows into an input terminal and one that arises from the circuit itself. Here, it is limited to those generated from the circuit itself. FIG. 3 is an equivalent circuit when focusing on the DC offset amount. Here, E _in (1) and E _in (2) are DC offset electromotive voltages, and R _in (1) and R _in (2) are DC offset drive resistances. E
The relationship between _in (1), E _in (2) and V _out (S) is calculated as follows.

Therefore, the DC offset amount of this circuit is
You can set s = 0. That is, DC offset voltage V _out (0)
Is as follows.

Therefore, for the amount of DC offset generated in this circuit,
It can be seen that the amount of DC offset existing at the (-) input terminal of OP-AMP2 has no effect. The DC offset amount V _out (0) is proportional to R ₄ . Therefore, when designing a wave or equalizer using this circuit, R ₄ should be minimized.

(Object of the Invention) The present invention eliminates these drawbacks, and in the switched-capacitor biquadratic circuit, the circuit can be designed by paying attention to the frequency domain characteristic or the time domain characteristic and also the DC offset amount. The purpose is to reduce the amount of DC offset generated from the circuit itself.

The present invention will be described in detail below.

(Structure and Action of the Invention) FIG. 4 shows all possible combinations of elements as a general form of an SC biquad circuit to explain the present invention. The transfer function T ₄ (Z ⁻¹ ) of this circuit diagram is given by the following equation.

Where d ₀ = K ₁ K ₂ + K ₂ C ₁ + K ₁ C ₂ + C ₁ C ₂ -K ₃ K ₆ -K ₃ K ₈ -K ₅ K ₆ -K ₅ K ₈ d ₁ = K ₃ K ₇ + K ₃ K ₈ + K ₄ K ₆ + K ₄ K ₈ + K ₅ K ₆ + K ₅ K ₇ + 2K ₅ K ₈ -K ₂ C ₁ -K ₁ C ₂ -2C ₁ C ₂ d ₂ = C ₁ C ₂ -K ₄ K ₇ -K ₄ K ₈ -K ₅ K ₇ -K ₅ K ₈ n ₀ = K ₃ K ₉ + K ₃ K ₁₁ + K ₅ K ₉ + K ₅ K ₁₁ -K ₁ K ₁₂ -K ₁ K ₁₄ -K ₁₂ C ₁ -K ₁₄ C ₁ n ₁ = K ₁ K ₁₃ + K ₁ K ₁₄ + K ₁₂ C ₁ + K ₁₃ C ₁ + 2K ₁₄ C ₁ -K ₃ K ₁₀ -K ₃ K ₁₁ -K ₄ K ₉ -K ₄ K ₁₁ -K ₅ K ₉ -K ₅ K ₁₀ -2K ₅ K ₁₁ n ₂ = K ₄ K ₁₀ + K ₄ K ₁₁ + K ₅ K ₁₀ + K ₅ K ₁₁ -K ₁₃ C ₁ -K ₁₄ C ₁ .

Also, the transfer function T ₅ (Z ^-1 ) from V _in to the output V ₁ of OP-AMP1
Is given by

Where m ₀ = K ₆ K ₁₂ + K ₆ K ₁₄ + K ₈ K ₁₂ + K ₈ K ₁₄ -K ₂ K ₉ -K ₉ C ₂ -K ₂ K ₁₁ -K ₁₁ C ₂ m ₁ = K _{9 C 2 + K 2 K 10 K} 10 C 2 + K 2 K 11 + 2K 11 C 2 -K 6 K 13 -K 7 K 12 -K 7 K 14 -
K ₈ K ₁₃ -2K ₈ K ₁₆ m ₂ = K ₇ K ₁₃ + K ₇ K ₁₄ + K ₈ K ₁₃ + K ₈ K ₁₄ -K ₁₀ C ₂ -K ₁₁ C ₂ -K ₆ K ₁₄ . Similar to the case of the equation (3), the transfer function of the RC equivalent circuit of FIG. 4 is obtained. That is, RC in Fig. 4 when c >>
The equivalent circuit is shown in FIG. This transfer function T ₆ (s) is given by the following equation. However, R = 1 / (f _c K).

Where Y ₁ = (1 + sC ₁ R ₁ ) / R ₁ , Y ₂ = (1 + sC ₄ R ₆ ) / R ₆ , Y ₃ = 1 / R ₇ , Y ₄ = (1 + sC ₄ R ₉ ) / R ₉ , Y ₅ = 1 / R ₁₀ , Y ₆ = (1 + sC ₂ R ₂ ) / R ₂ , Y ₇ = (1 + sC ₃ R ₃ ) / R ₃ , Y ₈ = 1 / R ₄ and Y ₉ = (1 + sC ₆ R ₁₂ ) / R ₁₂ , and Y ₁₀ = 1 / R ₁₃ .

Next, the DC offset amount will be described. FIG. 6 is an RC equivalent circuit for FIG. 5 when focusing on the DC offset amount. Similar to the case of the equation (4), the DC offset electromotive forces are E _in (1) and E _in (2). Set the drive resistance of E _in (1), E _in (2) to R
_{If in} (1), R _in (2), then E _in (1), E _in (2) and output voltage V
The relationship of _out (s) is as follows.

Therefore, the DC offset voltage can be obtained by setting s = 0 in the equation (9) and becomes as follows.

Therefore, the characteristic of this circuit is that the DC offset voltage V _out (0) is expressed by E _in (1) and E _in (2), and the relationship is set to an appropriate value, as can be seen from the equation (9). In this case, V _out (0) can be decreased and can be made zero.

When designing wave filters or equalizers using SC biquadratic circuits, design methods that focus on frequency domain characteristics or time domain characteristics are used. The present invention provides a circuit that can be designed by paying attention to the above-mentioned frequency domain characteristic or time domain characteristic as well as the DC offset amount.

That is, according to the present invention, a first operational amplifier having an integrating capacitance (C ₁ ) and having a non-inverting input terminal connected to a common potential point,
A second operational amplifier having an integrating capacitance (C ₂ ) and a non-inverting input terminal connected to a common potential point; a signal input terminal;
A first capacitor (K ₁₄ ) fixedly connected to the inverting input terminal of the operational amplifier; and a fixed capacitor between the output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier. A second capacitor (K ₅ ), a third capacitor (K ₁₀ ), a fourth capacitor (K ₃ ), one end of the third capacitor (K ₁₀ ) and the fourth capacitor connected to
A fifth capacitor (K ₁ ) fixedly connected to one end of (K ₃ ).
And a sixth capacitor (K ₇ ) and the signal input terminal and a common potential point are switched to connect to the other end of the third capacitor (K ₁₀ ).
The switching means (SW ₁ ) and the inverting input terminal of the first operational amplifier and a common potential point are switched to switch the third capacitance.
Second switching means (SW ₂ ) connected to the one end of (K ₁₀ ).
And a third switching means (SW ₃ ) for switching the output terminal of the first operational amplifier and a common potential point to connect to one end of the fourth capacitor (K ₃ ), and the inverting input of the second operational amplifier. A fourth switching means (SW ₄ ) for switching the terminal and the common potential point to connect to the other end of the fourth capacitor (K ₃ ), and the inverting input terminal of the first operational amplifier and the common potential point. The fifth switching means (SW ₅ ) connected to one end of the sixth capacitance (K ₇ ) and the output terminal of the second operational amplifier and a common potential point to switch the other of the sixth capacitance (K ₇ ). A sixth switching means (SW ₆ ) connected to the terminal, a signal is input from the signal input terminal and output from the output terminal of the second operational amplifier, and all the switching means are driven by a two-phase clock. And the first and sixth switchings An SC biquad circuit is provided in which the set of means and the set of the second, third, fourth and fifth switching means are connected to a common potential point in anti-phase relationship.

Further, according to the present invention, the first operational amplifier having the integrating capacitance (C ₁ ) and the non-inverting input terminal connected to the common potential point, and the integrating capacitor (C ₂ ) having the non-inverting input terminal are common. A second operational amplifier connected to the potential point, a first capacitance (K ₁₄ ) fixedly connected between the signal input terminal and the inverting input terminal of the second operational amplifier, and the first operational amplifier an output terminal and the second operational amplifier the inverting fixedly connected second capacitance between the input terminal of the (K _5), a third capacitor (K _10), and a fourth capacitor (K _3), The fifth capacitor (K ₁ ), the sixth capacitor (K ₇ ), the signal input terminal and the common potential point are switched, and the third capacitor is switched.
A first switching means (SW ₁ ) connected to one end of (K ₁₀ ),
Second switching means (SW ₂ ) for switching the inverting input terminal of the first operational amplifier and a common potential point to connect to the other end of the third capacitance (K ₁₀ ); and an output terminal of the first operational amplifier. a third switching means for connecting by switching the common potential point to one end of the fourth capacitor _{(K 3) (SW 3)} , the switching between the common potential point and the inverting input terminal of said second operational amplifier first 4 one end of the capacitor fourth switching means (SW ₄₎ and said inverting input terminal and the switching between the common potential point sixth capacitance of the first operational amplifier (K ₇₎ which connects to the other end of the (K ₃₎ The fifth switching means (SW ₅ ) connected to the sixth switching means (SW ₆ ) and the output terminal of the second operational amplifier and the common potential point are switched and connected to the other end of the sixth capacitance (K ₇ ). )
A seventh switching means (SW ₇ ) for switching the inverting input terminal of the first operational amplifier and a common potential point to connect to one end of the fifth capacitor (K ₁ ); By switching the output terminal and the common potential point, the fifth capacitor (K
₈ ) switching means (SW ₈ ) connected to one end of ₁ ), a signal is input from the signal input terminal and output from the output terminal of the second operational amplifier, and all the switching means are two-phase. A set driven by a clock and having a reverse phase relationship between the set of the first and sixth switching means and the set of the second, third, fourth, fifth, seventh and eighth switching means An SC biquad circuit connected to a common potential point at is provided.

According to such a circuit configuration, not only the DC offset amount can be reduced, but also the number of constituent elements is small, so that the area occupied by the chip is reduced and the characteristics are improved.

(Embodiment) FIGS. 7 and 8 are circuit diagrams showing first and second embodiments of a switched capacitor biquadratic circuit according to the present invention, respectively. First, the configuration of the first embodiment of the present invention shown in FIG. 7 will be described. In the figure, reference numerals ₁ and ₂ denote first and second operational amplifiers 2 having integrating capacitors C ₁ and C ₂ , respectively.
And these non-inverting input terminals are grounded as a common potential point. A capacitor K ₁₄ is connected in series between the signal input terminal 3 and the inverting input terminal of the second operational amplifier 2,
A capacitance K ₅ is connected between the output terminal of the operational amplifier 1 and the inverting input terminal of the second operational amplifier 2. Switch SW ₁
Switches between the signal input terminal 3 and the common potential point to switch the capacitance K ₁₀
Connect to one end of. The switch SW ₂ switches between the inverting input terminal of the first operational amplifier 1 and the common potential point and connects it to the other end of the capacitor K ₁₀ . The switch SW ₃ switches between the output terminal of the first operational amplifier 1 and the common potential point and connects it to one end of the capacitor K ₃ . The switch SW ₄ switches between the inverting input terminal of the second operational amplifier and the common potential point and connects it to the other end of the capacitor K ₃ . The switch SW ₅ switches between the inverting input terminal of the first operational amplifier 1 and the common potential point, and connects it to the capacitor K ₇ . The switch SW ₆ switches between the output terminal of the second operational amplifier 2 and the common potential point, and connects it to the capacitor K ₇ . Further, the capacitance K ₁ is connected in series between the movable switch terminal of the switch SW _{1 and} the movable switch terminal of the switch SW ₃ .

On the other hand, the second embodiment shown in FIG. 8 is the switch shown in FIG.
While SW ₂ and SW _{3 also} serve to switch the capacitance K ₁ , switches SW ₇ and SW ₈ are newly provided as shown in FIG. 8 to switch the capacitance K ₁ to the switches SW ₇ and SW _8. The other construction is the same as that of the first embodiment and exhibits exactly the same characteristics.

In FIGS. 7 and 8, a signal is input from the signal input terminal 3 and output from the signal output terminal 4. Further, in FIG. 7, all the switches SW _{1 to} SW ₆ are driven by a two-phase clock, and the set consisting of the switches SW ₁ and SW ₆ and the switch SW _{2 are}
It is connected to the common potential point in anti-phase with the group consisting of ~ SW ₅ . On the other hand, in FIG. 8, all the switches SW _{1 to} SW ₈ are driven by a two-phase clock, and the set consisting of the switches SW ₁ and SW ₆ and the set consisting of the switches SW _{2 to} SW ₅ , SW ₇ , and SW _8. And are connected to the common potential point in the opposite phase. The transfer function T ₇ (z ⁻¹ ) of FIG. 7 or FIG. 8 is expressed by the equation (6) as K ₂ = K ₄ = K ₆ = K ₈ = K ₉ = K ₁₁ = K ₁₂ = K ₁₃ = 0. Obtained by placing.

Where d ₀ = C ₁ C ₂ + K ₁ C ₂ , d ₁ = K ₃ K ₇ + K ₅ K ₇ -K ₁ C ₂ -2C ₁ C ₂ , d ₂ = C ₁ C ₂ -K ₅ K ₇ ,, n ₀ = K ₁₄ C ₁ + K ₁ K ₁₄ , n ₁ = K ₃ K ₁₀ + K ₅ K ₁₀ -K ₁ K ₁₄ -2K ₁₄ C ₁ ,, n ₂ = K ₁₄ C ₁ -K ₅ K ₁₀ Is.

Further, the transfer function T ₈ (s) in the s region is exactly the same as in the case of T ₇ (z ⁻¹ ) in the formula (8), and R ₂ = R ₄ = R ₆ = R ₉ = R ₁₂ = R ₁₃ = ∞, C ₄ = C ₅ = 0. However, R = 1 / (f _c K).

here, Is.

Next, the DC offset V _out (0) of the circuit of FIG. 7 or FIG.
Is as follows from equation (10).

Generally, when a wave filter or equalizer is realized by SC biquadratic circuit, as a DC offset source generated from the circuit itself,
There is a switch and OP-AMP. It can be said that more DC offset occurs in the switch and that it occurs in one direction. The amount of DC offset generated by OP-AMP is small, but it can be said that it is not unidirectional. Therefore, the DC offset amount can be reduced by using FIG. 7 or FIG. 8 when the generated DC offset amount is unidirectional like a switch. That is, in the case of a unidirectional DC offset source, the first
The DC offset amount of the circuit for the figure (equation (5)) and the DC offset amount of the circuit for the circuit of FIG.
As can be seen by comparing (3)), it can be said that the circuit of FIG. 7 or 8 of the present invention has a small DC offset amount.

Finally, the effectiveness of the present invention is shown by the results of design and trial production. An equalizer for equalizing the attenuation characteristic of FIG. 9 was designed by the circuit of the present invention and the conventional circuit. This design element value is shown in Table 1.
And shown in Table 2.

Table 3 shows the experimental results.

As can be seen from Table 3, according to the present invention as compared with the conventional circuit, the DC offset voltage generated from the circuit itself can be suppressed to be small.

(Effects of the Invention) As described above, according to the present invention, it is possible to reduce the DC offset amount generated from the circuit itself.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional general switched capacitor biquadratic circuit, FIG. 2 is a circuit diagram of the RC equivalent circuit of FIG. 1, and 3
The figure is a circuit diagram of RC equivalent circuit when focusing on offset,
FIG. 4 is a circuit diagram of a general switched capacitor biquadratic basic circuit for explaining the present invention, FIG. 5 is a circuit diagram of the RC equivalent circuit of FIG. 4, and FIG. 6 is a circuit diagram of the RC equivalent circuit for a DC offset. FIG. 7 is a circuit diagram, FIG. 7 is a circuit diagram of a first embodiment of the present invention, FIG. 8 is a circuit diagram of a second embodiment of the present invention, and FIG. 9 is a diagram showing an attenuation characteristic of a design prototype. 1,2 ...... Operational amplifier 3 ...... Signal input terminal 4 ...... Signal output terminal C ₁ , C ₂ , K _{1 to} K ₁₄ ...... Capacitor R _{1 to} R ₇ ...... Resistor SW _{1 to} SW ₈ ...... Switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuhiko Gunji 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Tadakatsu Kimura 3-9-11 Midoricho, Musashino City Japan (72) Masayuki Ishikawa, Inventor Masayuki Ishikawa, 3-9-11 Midoricho, Musashino City, Tokyo Inside the Musashino Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation

Claims (2)

[Claims] 1. A first operational amplifier having an integrating capacitance (C ₁ ) and having a non-inverting input terminal connected to a common potential point, and an integrating capacitance (C
₂ ) and a second operational amplifier having a non-inverting input terminal connected to a common potential point, and a first capacitance (fixedly connected between the signal input terminal and the inverting input terminal of the second operational amplifier ( K
₁₄ ), a second capacitor (K ₅ ) fixedly connected between the output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier, and a third capacitor (K ₁₀ ). , The fourth capacity (K ₃ ),
A fifth capacitor (K ₁ ) fixedly connected between one end of the third capacitor (K ₁₀ ) and one end of the fourth capacitor (K ₃ ), and a sixth capacitor (K ₁ ).
₇ ), a first switching means (SW ₁ ) for switching the signal input terminal and a common potential point to connect to the other end of the third capacitor (K ₁₀ ), and an inverting input terminal of the first operational amplifier. The second switching means (SW ₂ ) for switching the common potential point to connect to the one end of the third capacitor (K ₁₀ ), and the output terminal of the first operational amplifier and the common potential point for switching the fourth potential.
Third switching means for connecting to one end of the capacitor (K ₃₎ (SW ₃₎
A fourth switching means (SW ₄ ) for switching the inverting input terminal of the second operational amplifier and a common potential point to connect to the other end of the fourth capacitor (K ₃ ); Fifth switching means (SW ₅ ) for switching between the inverting input terminal and the common potential point and connecting to one end of the sixth capacitor (K ₇ ).
And a sixth switching means (SW ₆ ) for switching the output terminal of the second operational amplifier and the common potential point to connect to the other end of the sixth capacitor (K ₇ ), and the signal is the signal input terminal. From the output terminal of the second operational amplifier, all of the switching means are driven by a two-phase clock, and the set of the first and sixth switching means and the second , A switched-capacitor biquadratic circuit characterized in that it is connected to a common potential point in an opposite phase relation to the set of the third, fourth and fifth switching means. 2. A first operational amplifier having an integrating capacitance (C ₁ ) and having a non-inverting input terminal connected to a common potential point, and an integrating capacitance (C
₂ ) and a second operational amplifier having a non-inverting input terminal connected to a common potential point, and a first capacitance (fixedly connected between the signal input terminal and the inverting input terminal of the second operational amplifier ( K
₁₄ ), a second capacitor (K ₅ ) fixedly connected between the output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier, and a third capacitor (K ₁₀ ). , The fourth capacity (K ₃ ),
First switching means (SW ₁ ) for switching the fifth capacitance (K ₁ ), the sixth capacitance (K ₇ ), the signal input terminal and the common potential point and connecting to one end of the third capacitance (K ₁₀ ). ), And second switching means for switching between the inverting input terminal of the first operational amplifier and the common potential point to connect to the other end of the third capacitor (K ₁₀ ).
(SW ₂ ) and the output terminal of the first operational amplifier and a common potential point are switched and connected to one end of the fourth capacitor (K ₃ ).
The switching means (SW ₃ ) and the inverting input terminal of the second operational amplifier and the common potential point are switched to switch the fourth capacitance.
A fourth switching means (SW ₄ ) connected to the other end of (K ₃ ),
A fifth switching means (SW ₅ ) for switching the inverting input terminal of the first operational amplifier and a common potential point to connect to one end of the sixth capacitor (K ₇ ); and an output terminal of the second operational amplifier. The sixth switching means (SW ₆ ) for switching the common potential point to connect to the other end of the sixth capacitor (K ₇ ), and the inverting input terminal of the first operational amplifier and the common potential point for switching the common potential point. The seventh switching means (SW ₇ ) connected to one end of the fifth capacitance (K ₁ ) and the output terminal of the first operational amplifier and a common potential point are switched to one end of the fifth capacitance (K ₁ ). An eighth switching means (SW ₈ ) connected thereto, a signal is input from the signal input terminal and output from the output terminal of the second operational amplifier, and all the switching means are driven by a two-phase clock. And said first and sixth switching The pair of switched capacitors and the pair of the second, third, fourth, fifth, seventh and eighth switching means are connected to a common potential point in an inverse phase relationship. Secondary circuit.