JPH07183738A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH07183738A JPH07183738A JP5327132A JP32713293A JPH07183738A JP H07183738 A JPH07183738 A JP H07183738A JP 5327132 A JP5327132 A JP 5327132A JP 32713293 A JP32713293 A JP 32713293A JP H07183738 A JPH07183738 A JP H07183738A
- Authority
- JP
- Japan
- Prior art keywords
- potential
- amplifier
- base
- transistor
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特にベース接地アンプに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a grounded base amplifier.
【０００２】[0002]
【従来の技術】従来のＯＮ、ＯＦＦ機能を付けたベース
接地形アンプは、図２に示すように、ベース接地アンプ
のベース電位をＯＮ，ＯＦＦするスイッチ２０と定電流
源をＯＦＦするためのスイッチ２１がありこれらのスイ
ッチをＯＮすることでベース接地アンプの機能を停止さ
せていた。そのために入力端子は電位のＯＶ付近まで低
下する。2. Description of the Related Art As shown in FIG. 2, a conventional grounded base amplifier having an ON / OFF function has a switch 20 for turning on / off the base potential of the grounded base amplifier and a switch for turning off a constant current source. There is 21 and the function of the grounded base amplifier is stopped by turning on these switches. Therefore, the input terminal drops to near the potential OV.
【０００３】[0003]
【発明が解決しようとする課題】この従来のＯＮ，ＯＦ
Ｆ機能を付けたベース接地アンプを半導体チップ上に集
積化しようとすると、半導体集積化特有の静電保護ダイ
オード１２〜１５を付ける必要がある。この為ベース接
地アンプがＯＦＦ状態においては図４に示すように入力
端子の電位がＯＶ付近であるので、大振巾の入力信号が
入力されると保護ダイオードがＯＮしてしまい半導体集
積回路において誤動作の原因になるという問題点があっ
た。[Problems to be Solved by the Invention] This conventional ON, OF
In order to integrate a base-grounded amplifier having an F function on a semiconductor chip, it is necessary to add electrostatic protection diodes 12 to 15 peculiar to semiconductor integration. For this reason, when the grounded base amplifier is in the OFF state, the potential of the input terminal is near OV as shown in FIG. 4, so that the protection diode turns ON when a large amplitude input signal is input, causing malfunction in the semiconductor integrated circuit. There was a problem that it caused.
【０００４】半導体集積回路では最低電位よりも低い電
圧の信号や最高電位よりも高い電圧を入力すると誤動作
の原因になる。In a semiconductor integrated circuit, inputting a signal having a voltage lower than the lowest potential or a voltage higher than the highest potential causes malfunction.
【０００５】[0005]
【課題を解決するための手段】本発明のＯＮ，ＯＦＦ機
能付きベース接地アンプは、信号を増幅するためのベー
ス接地アンプのトランジスタと前記ベース接地アンプの
トランジスタのエミッタの電位を変える為のトランジス
タと前記ベース接地アンプのトランジスタと前記エミツ
タの電位を与えるトランジスタに与えるバイアス電圧と
バイアス電圧を切り換える為のスイッチと入力側の抵抗
と負荷抵抗と、ベース接地アンプのトランジスタを動作
させるための定電流源とを備えている。The grounded base amplifier with ON / OFF function of the present invention comprises a transistor of the base grounded amplifier for amplifying a signal and a transistor for changing the potential of the emitter of the transistor of the base grounded amplifier. A bias voltage applied to the transistor of the base-grounded amplifier and the transistor that supplies the potential of the emitter, a switch for switching the bias voltage, a resistor on the input side, a load resistance, and a constant current source for operating the transistor of the base-grounded amplifier. Is equipped with.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は、本発明の一実施例で、ＮＰＮトランジスタ
を使った場合の回路図である。まず、信号は入力端子１
より入力され入力抵抗１を経由してベース接地アンプの
入力である第１のトランジスタ５のエミッタに入力され
信号が増幅され出力側であるコレクタから出力される。
このときは、スイッチ１はＯＮ側になっているので第１
のトランジスタ５と第２のトランジスタ７のベースの電
位関係が次の様になっているため定電流源の電流は ＶB1＞ＶB2 ベース接地アンプの第１のトランジスタ５に流れ増幅器
として動作する。次にスイッチ１をＯＦＦ側にすると前
記トランジスタのベース電位は次の様な関係になるため
ベース接地アンプの第１のトランジスタ５のエミッタの
電位が上昇し、前記ベース接地アンプの第１のトランジ
スタ５はＯＦＦ状態になり定電流源１の電流は、第２の
トランジスタ７側に流れ、増幅器としてはＯＦＦ状態に
なる。The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram when an NPN transistor is used in an embodiment of the present invention. First, the signal is input terminal 1
The input signal is further input to the emitter of the first transistor 5 which is the input of the grounded base amplifier via the input resistor 1, and the signal is amplified and output from the collector which is the output side.
At this time, since the switch 1 is on,
Since the potential relationship between the bases of the transistor 5 and the second transistor 7 is as follows, the current of the constant current source flows into the first transistor 5 of the base ground amplifier V B1 > V B2 and operates as an amplifier. Next, when the switch 1 is turned off, the base potential of the transistor has the following relationship, so that the potential of the emitter of the first transistor 5 of the base-grounded amplifier rises and the base potential of the first transistor 5 of the grounded-base amplifier increases. Becomes an OFF state, the current of the constant current source 1 flows to the second transistor 7 side, and becomes an OFF state as an amplifier.
【０００７】この時、入力端子の電位はＶB3−ＶBE（Ｖ
BEは第２のトランジスタ７のベース・エミッタ間の電位
差で約０．７Ｖ）に固定される。そのため図３に示すよ
うにアンプがＯＦＦ状態でも入力端子の電位がさがらな
いので、大振巾の信号が入力されても保護ダイオードが
ＯＮしない。At this time, the potential of the input terminal is V B3 -V BE (V
BE is fixed at a potential difference between the base and emitter of the second transistor 7 of about 0.7 V). Therefore, as shown in FIG. 3, since the potential of the input terminal does not decrease even when the amplifier is in the OFF state, the protection diode does not turn ON even when a large amplitude signal is input.
【０００８】[0008]
【発明の効果】以上説明したように本発明は、ベース接
地アンプのトランジスタをＯＮ，ＯＦＦさせるためのト
ランジスタを追加したので、ベース接地アンプがＯＦＦ
状態でも入力端子の電位が低下しないのでＯＦＦ状態に
おいても、入力端子につく保護ダイオードがＯＮしない
という効果を有する。As described above, according to the present invention, since the transistor for turning on and off the transistor of the grounded base amplifier is added, the grounded base amplifier is turned off.
Since the potential of the input terminal does not drop even in the state, the protection diode attached to the input terminal does not turn on even in the off state.
【図１】本発明の一実施例の回路図。FIG. 1 is a circuit diagram of an embodiment of the present invention.
【図２】従来の回路図。FIG. 2 is a conventional circuit diagram.
【図３】本発明のＯＦＦ時の入力端子の入力波形図。FIG. 3 is an input waveform diagram of the input terminal when the present invention is OFF.
【図４】従来例のＯＦＦ時の入力端子の入力波形図。FIG. 4 is an input waveform diagram of an input terminal when the conventional example is OFF.
１ 入力端子 ２ 入力抵抗 ３ 定電流源 ４ バイアス電圧ＶB1 ５ ベース接地アンプのトランジスタ ６ 負荷抵抗 ７ トランジスタ ８ スイッチ ９ バイアス電圧ＶB3 １０ バイアス電圧ＶB2 １１ 出力端子 １２，１３，１４，１５ 保護ダイオード1 Input Terminal 2 Input Resistance 3 Constant Current Source 4 Bias Voltage V B1 5 Base Ground Amplifier Transistor 6 Load Resistance 7 Transistor 8 Switch 9 Bias Voltage V B3 10 Bias Voltage V B2 11 Output Terminal 12, 13, 14, 15 Protection Diode
Claims (2)
を構成する第１のトランジスタと前記第１のトランジス
タがオフ状態の時に前記第１のトランジスタ内のエミッ
タ電位を所定電位にする電位供給手段を有することを特
徴とする半導体集積回路装置。1. A first transistor forming a grounded base amplifier for amplifying an input signal, and potential supply means for setting an emitter potential in the first transistor to a predetermined potential when the first transistor is in an off state. A semiconductor integrated circuit device having.
第１のトランジスタのエミッタと接続し、そのベースが
複数の電位が発生するバイアス電圧発生に接続したこと
を特徴とする請求項１記載の半導体集積回路装置。2. The semiconductor according to claim 1, wherein the potential supply means has an emitter connected to the emitter of the first transistor and a base connected to a bias voltage generator for generating a plurality of potentials. Integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5327132A JPH07183738A (en) | 1993-12-24 | 1993-12-24 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5327132A JPH07183738A (en) | 1993-12-24 | 1993-12-24 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07183738A true JPH07183738A (en) | 1995-07-21 |
Family
ID=18195675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5327132A Pending JPH07183738A (en) | 1993-12-24 | 1993-12-24 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07183738A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5482157A (en) * | 1977-12-14 | 1979-06-30 | Hitachi Ltd | Electronic switch circuit |
-
1993
- 1993-12-24 JP JP5327132A patent/JPH07183738A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5482157A (en) * | 1977-12-14 | 1979-06-30 | Hitachi Ltd | Electronic switch circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970212 |