JPH07183351A - Semiconductor device - Google Patents

Abstract

PURPOSE:To accurately confirm the amount of misalignment of the mask of a mask pattern for forming an active region and that for forming an n-type diffusion layer region. CONSTITUTION:P-well region 42 is formed on silicon substrate 41, an element isolation region 43 is formed on P-well region 42, and n-type diffusion layer regions 44a, 44b, and 44c are formed at an element region separated by the element isolation region 43. The pattern pitch differs by 0.1mum or longer between the mask pattern for forming active region and that for forming n-type diffusion region. Therefore, assuming that the n-type diffusion layer region 44b is formed at a position where the amount of misalignment between the mask pattern for forming active region and that for forming n-type diffusion layer region is equal to 0, the n-type diffusion layer regions 44a and 44c are formed at a position which is deviated a pattern pitch difference between the mask pattern for forming active region and that for forming n-type diffusion layer region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an inspection pattern for measuring a mask displacement amount for confirming a mask displacement amount by a resistance characteristic evaluation.

[0002]

2. Description of the Related Art Conventionally, a vernier pattern is used as a mask misalignment detection pattern in order to check the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern. The above-mentioned conventional vernier will be described below with reference to the drawings.

FIG. 7 is a plan view of a vernier pattern.
In FIG. 7, 1 is a mask pattern for forming an active region, 2
Is a mask pattern for forming an n-type diffusion layer region. The active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern 2 are made to have different pattern pitches. After patterning the active region forming mask pattern 1, the n-type diffusion layer region forming pattern 2 is patterned using the active region forming mask pattern 1 as a reference. The position where the misalignment between the active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern 2 becomes zero is confirmed by a microscope, and the active region forming mask patterns 1 and n are checked.
The amount of misalignment of the mask of the mask pattern 2 for forming the mold diffusion layer region is examined. The misalignment of the masks of the active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern 2 will be described in detail below.

FIG. 8 is a sectional view showing the position of the section line AA 'in FIG. P well region 4 on silicon substrate 3
To form an element isolation region 5 on the P well region 4, and the active region isolated by the element isolation region 5 has n-type diffusion layer formation regions 6a, 6b and 6c. Areas other than 6a, 6b and 6c are covered with a resist 7.

As shown in FIG. 8, an n-type diffusion layer forming region 6 is formed.
Since the pattern pitch of the n-type diffusion layer region forming pattern 2 for forming a, 6b and 6c and the active region forming mask pattern 1 for forming the element isolation region 5 are different, n-type diffusion in the active region is performed. Layer forming regions 6a, 6b, 6c
Are made so that the positions of the are different from each other. An area in which the mask misalignment amount between the active area forming mask pattern 1 and the n type diffusion layer area forming mask pattern 2 is zero is referred to as an n type diffusion layer forming area 6b in FIG.
The type diffusion layer forming regions 6a and 6c are formed so that a part of the n type diffusion layer forming region rides on the element isolation region.

When the mask misalignment between the active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern 2 occurs, the active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern A region in which the amount of misalignment with the second mask is zero is examined with a microscope, and the amount of misalignment between the active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern 2 is confirmed. After forming the n-type diffusion layer forming regions 6a, 6b and 6c, ion implantation is performed to form the n-type diffusion layer, and then the resist 7 is removed. For this reason, the n-type diffusion layer forming regions 6a, 6b, 6c are not known here.

In the vernier pattern shown above, the mask misalignment between the active region forming mask pattern 1 and the n-type diffused layer region forming mask pattern 2 is determined by patterning the n-type diffused layer forming region mask pattern 2. You can only check it when you go.

[0008]

However, in the above-described structure, when characteristic deterioration occurs after the semiconductor device is manufactured, the cause is the active region forming mask pattern 1 and the n-type diffusion layer region. Forming mask pattern 2
Even if the mask misalignment is estimated, the mask misalignment amount between the active region forming mask pattern 1 and the n-type diffusion layer region forming mask pattern 2 cannot be confirmed.

In view of the above problems, the present invention provides a mask of an active region forming mask pattern and an n type diffusion layer region forming mask pattern by measuring the resistance of the n type diffusion layer region even after the semiconductor device is manufactured. It is an object of the present invention to provide a semiconductor device having an inspection pattern for measuring a mask shift amount, which can accurately check the alignment shift amount.

[0010]

In order to solve the above-mentioned problems, a semiconductor device of the present invention comprises a plurality of element isolation regions formed at equal pitches and an active region formed between the element isolation regions. An inspection pattern including a plurality of diffusion layers formed at equal intervals in the active region at a pitch different from the pitch of the active region.

Further, the inspection pattern comprises a vertical inspection pattern and a horizontal inspection pattern arranged at both ends on a diagonal of the chip, and an element isolation region and a diffusion layer of the vertical inspection pattern are arranged in the vertical direction of the chip. The element isolation region of the lateral inspection pattern and the diffusion layer extend in the lateral direction of the chip.

[0012]

According to the semiconductor device of the present invention, since the misalignment amount between the active region and the diffusion layer region is zero at the center of the inspection pattern, the resistance value of the diffusion layer is at the center of the inspection pattern. It is the minimum value. Therefore, when the resistance value becomes the minimum value in the diffusion layer other than the center of the inspection pattern, it means that there is a misalignment between the active region and the diffusion layer, and the position of the diffusion layer where the resistance value becomes the minimum value. The misalignment amount of the mask can be confirmed by looking at.

Since both the vertical inspection pattern formed parallel to the vertical direction of the chip and the horizontal inspection pattern formed parallel to the horizontal direction of the chip rotated by 90 ° are used, the active region and the diffusion layer are formed. The misalignment of the mask in the vertical and horizontal directions can be confirmed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device having an inspection pattern for measuring a mask shift amount according to an embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are respectively a layout view and a plan view of a semiconductor device having an inspection pattern for measuring a mask shift amount according to an embodiment of the present invention.

In FIG. 1, 21 is a chip and 22 is an inspection pattern. The inspection pattern 22 is for confirming misalignment of the mask. In order to confirm the misalignment between the vertical direction and the horizontal direction of the mask, the inspection pattern is made parallel to the vertical direction of the chip, and at the same time, the inspection pattern is made to be parallel to the horizontal direction rotated by 90 °. In order to confirm not only the misalignment between the vertical and horizontal directions of the mask but also the rotation of the mask, one set of the vertical direction inspection pattern and the horizontal direction inspection pattern is arranged diagonally at two corners of the chip.

In FIG. 2, 23 is a P-well region forming mask pattern, 24 is an active region forming mask pattern, 25 is an n-type diffusion layer region forming mask pattern, and 26.
Is a contact hole forming mask pattern, and 27 is a first
Aluminum wiring forming pattern 28, 29 are contact hole forming regions, 30 to 32 are active region forming mask patterns 2 in the contact hole forming regions 28, 29.
4, the vertical width and the horizontal width and the mask interval, 33 to 35 are the horizontal width and the vertical width and the pattern pitch of the active region forming mask pattern 24 in the regions other than the contact hole forming regions 28 and 29, and 36 and 37 are the contact hole forming regions. Two
8 and 29, n-type diffusion layer region forming mask pattern 25
And the horizontal and horizontal widths 38 to 40 are the horizontal and vertical widths and pattern pitches of the n-type diffusion layer region forming mask pattern 25 in regions other than the contact hole forming regions 28 and 29.

The mask layout rule of the active region forming mask pattern 24 is as follows.
The vertical width 30 and the horizontal width 31 of the mask pattern at 8 and 29 are 2.9 μm or more, and the mask pattern interval 32 is 1.0 μm.
That is all. The lateral width 33 of the active region forming mask pattern 24 in the regions other than the contact hole forming regions 28 and 29 is 1.6 μm or more, and the pitch 35 is 3.9 μm or more. Regarding the vertical width 34, the vertical width 34 of the active region forming mask pattern 24 is set to 30 μm or more so that the resistance value of the first aluminum wiring is 10% or less of the resistance value of the n-type diffusion layer region.

The number of active region forming mask patterns 24 formed by the above-described mask layout is three in FIG. 2, but the number is not limited. A line that vertically connects the active region forming mask patterns 24 in the contact hole forming regions 28 and 29 is the vertical inspection pattern, and the inspection pattern produced by rotating the vertical inspection pattern by 90 ° is the horizontal inspection pattern. And
In order to confirm the misalignment between the mask in the vertical direction and the mask in the horizontal direction, two active region forming mask patterns 24, a vertical inspection pattern and a horizontal inspection pattern, are prepared.

Mask pattern 25 for forming n-type diffusion layer region
The mask layout rule is that the vertical width 36 and the horizontal width 37 of the mask pattern in the contact hole formation regions 28 and 29.
Is 1.0 μm or more larger than the vertical width 30 and the horizontal width 31 of the mask of the active region forming mask pattern 24, and the n-type diffusion layer region forming mask pattern 25 in the contact hole forming regions 28 and 29 is the contact hole forming region. 28,
This is a layout for covering the active region forming mask pattern 24 in 29. Contact hole formation area 2
The lateral width 38 of the mask of the n-type diffusion layer region forming mask pattern 25 in the regions other than 8 and 29 is 1.0 μm or more. Regarding the vertical width 39 of the mask, the vertical width of the mask of the n-type diffusion layer region forming mask pattern 25 is set so that the resistance value of the first aluminum wiring is 10% or less of the resistance value of the n-type diffusion layer region. 39 is 28 μm or more. The pattern pitch 40 is defined by the contact hole formation region 28,
Mask pattern 2 for forming active regions in regions other than 29
4 and the pattern pitch 35 of 4 must be different by 0.1 μm or more. Details regarding the pattern pitch will be described below with reference to sectional views of inspection patterns.

FIG. 3 is a sectional view showing the position of the section line BB 'in FIG. A P well region 42 is formed on a silicon substrate 41, and an element isolation region 43 is formed on the P well region 42.
And n-type diffusion layer regions 44a, 44b and 44c are formed in the active region separated by the element isolation region 43. The effect of producing the inspection pattern configured as described above will be described below with reference to FIGS.

The n-type diffusion layer region forming mask pattern 25 shown in FIG. 2 is the active region forming mask pattern 24.
Is used as a reference to form regions for forming n-type diffusion layer regions 44a, 44b, 44c as shown in FIG. Active region forming mask pattern 24
And the n-type diffusion layer region forming mask pattern 25 are laid out so that the pattern pitches thereof are different by 0.1 μm or more.

The n-type diffusion layer region 44b is formed at a position where the misalignment amount between the active region forming mask pattern 24 and the n-type diffusion layer region forming mask pattern 25 is zero. The regions 44a and 44c are formed at positions displaced by the pattern pitch difference between the active region forming mask pattern 24 and the n-type diffusion layer region forming mask pattern 25. The mask layout is prepared so that the lateral spread of the n-type diffusion layer region becomes smaller as the mask shift amount between the active region formation mask pattern 24 and the n-type diffusion layer region formation mask pattern 25 becomes larger. There is.

Therefore, each n-type diffusion layer region 44a,
Since the widths of 44b and 44c in the horizontal direction are different, the resistance values (voltage value / current value) of the n-type diffusion layer regions 44a, 44b, and 44c are different from each other. When the mask shift amount between the active region forming mask pattern 24 and the n-type diffusion layer region forming mask pattern 25 becomes large, the n-type diffusion layer region forming mask pattern 25 and the element isolation region 43 gradually overlap with each other and the ion implantation region becomes small. Therefore, the lateral spread of the n-type diffusion layer region becomes smaller and the resistance value becomes higher. Active area forming mask pattern 2
4 and the n-type diffusion layer region forming mask pattern 25 formed at a position where the amount of misalignment is zero, the n-type diffusion layer region 44b has the largest lateral spread, and thus has the minimum resistance value. .

The inspection pattern is manufactured such that the misalignment amount between the active region forming mask pattern 24 and the n-type diffusion layer region forming mask pattern 25 is zero at the center of the inspection pattern. Therefore, at the center of the inspection pattern, n
The resistance value of the type diffusion layer region must be the minimum value. When the resistance value becomes the minimum value in the n-type diffusion layer region other than the center of the inspection pattern, the active region forming mask pattern 24
Therefore, the misalignment between the mask pattern 25 for forming the n-type diffusion layer region and the misalignment occurs, and at the same time, the misalignment amount of the mask can be estimated by checking the minimum resistance value.

Since the inspection pattern uses both the vertical inspection pattern formed parallel to the vertical direction of the chip and the horizontal inspection pattern formed parallel to the horizontal direction of the chip rotated by 90 °, the inspection pattern for forming the active region is used. Mask pattern 24 and n
It is possible to confirm the misalignment of the mask in the vertical direction and the horizontal direction of the mask pattern 25 for forming the type diffusion layer region. The number of n-type diffusion layer region forming mask patterns 25 is not limited as in the active region forming mask pattern 24.
The same number as the active region forming mask pattern 24 is produced. The n-type diffusion layer region forming mask pattern 25 is aligned with the active region forming mask pattern 24 as a reference.

FIG. 4 is a plan view of an inspection pattern in which a part of the contact hole forming regions 28 and 29 of FIG. 2 is enlarged. Reference numeral 45 is a contact hole forming mask pattern, 46 is a contact hole interval of the contact hole forming mask pattern, 47 is a contact hole size, 48 is an active region forming mask pattern, and 49 is a first
Reference numeral 50 denotes an aluminum wiring forming mask pattern, and 50 denotes an overlap between the contact hole forming mask pattern 45 and the first aluminum wiring forming mask pattern 49.

Mask pattern 4 for forming contact holes
The layout rule of No. 5 is that the contact hole size 47 is 0.8 μm, the contact hole forming mask pattern 4 is
The contact spacing 46 of No. 5 is 0.5 μm or more. The number of contact holes should be large in order to reduce the resistance value of the contact holes as much as possible. The overlap 50 between the contact hole forming mask pattern 45 and the first aluminum wiring forming mask pattern 49 is 0.4 μm.
It is m or more. The width of the first aluminum wiring forming mask pattern 49 is the same as that of the active region forming mask pattern 48 in order to reduce the resistance of the first aluminum wiring.

The wiring required for measuring the resistance value of the n-type diffusion layer region of the inspection pattern will be described below. Figure 5
FIG. 4 is a wiring diagram showing wiring of a semiconductor device having an inspection pattern for measuring a mask shift amount in an embodiment of the present invention. In FIG. 5, reference numeral 51 is a vertical inspection pattern for confirming the vertical mask displacement of the chip, 52 is a horizontal inspection pattern for confirming the horizontal mask displacement of the chip, and 53.
Is the first aluminum wiring 5 of the vertical inspection pattern 51.
4 is the first aluminum wiring of the lateral inspection pattern 52,
55 is a bonding pad window for common inspection patterns 51 and 52, 56 is a bonding pad window for the vertical inspection pattern 51, and 57 is a bonding pad window for the horizontal inspection pattern 52.

The length and width of the bonding pad windows 55 to 57 are 60 μm or more. Regarding wiring, in order to make the layout of the inspection pattern as small as possible, a bonding pad window 56 common to the vertical direction inspection pattern 51 and the horizontal direction inspection pattern 52 is prepared and connected to the vertical direction inspection pattern 51 and the horizontal direction inspection pattern 52. . Therefore, the first aluminum wiring 5 of the vertical inspection pattern 51
3 and the first aluminum wiring 5 of the lateral inspection pattern 52
4 is used to connect with each contact. Since each of the vertical inspection pattern 51 and the horizontal inspection pattern 52 has two contact hole forming regions, a separate bonding pad window 56 is formed on each of the other contacts of the vertical inspection pattern 51. 1 Connect with aluminum wiring. Similarly, with respect to the lateral direction inspection pattern 52, separate bonding pad windows 57 are prepared and connected by the first aluminum wiring. By using the inspection pattern wired in this way, the resistance value of the n-type diffusion layer region described above can be measured, and the active region forming mask pattern and the n-type diffusion layer region forming mask pattern can be measured. It is possible to confirm the misalignment of the masks in the vertical and horizontal directions. Below is the inspection pattern n
The method for measuring the resistance value of the mold diffusion layer region will be described.

The inspection patterns in the embodiment of the present invention are the vertical inspection pattern 51 and the horizontal inspection pattern 52.
There are two types. A common bonding pad window 55 is provided for the vertical inspection pattern 51 and the horizontal inspection pattern 52.
And are connected by the first aluminum wirings 53 and 54. The other is a separate bonding pad window 5
6, 57 are connected by the first aluminum wiring.

In order to measure the resistance value of the n-type diffusion layer region, the current flowing between the n-type diffusion layer regions and the voltage between the n-type diffusion layer regions are necessary. In the case of the vertical inspection pattern 51, the bonding pad window 55 and the bonding pad window 56 are used, and in the case of the horizontal inspection pattern 52, the bonding pad window 55 and the bonding pad window 57 are used. The resistance between regions can be investigated. Since the measuring methods of the vertical inspection pattern 51 and the horizontal inspection pattern 52 are the same, only the resistance measurement of the vertical inspection pattern 51 will be described here.

A potential difference is generated between the n-type diffusion layer regions, and n
A voltage is applied using the bonding pad window 55 and the bonding pad window 56 in order to pass a current between the mold diffusion layer regions. When a voltage is applied, a potential difference is generated between the n-type diffusion layer regions, so that a current flows between the n-type diffusion layer regions. The current flowing between the n-type diffusion layer regions is read at a certain voltage value, and the resistance value (= voltage value / current value) is calculated from the calculated current value and voltage value. A graph is created with the horizontal axis representing the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern and the vertical axis representing the obtained resistance value.
The amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern can be known by reading the value on the abscissa where the resistance value shows the minimum value from the graph.

Since the purpose of obtaining the resistance value is to know the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern, the resistance measurement of all n-type diffusion layer regions is performed by the voltage value. Fixed. There is no limit on the voltage value. By using the method for measuring the resistance value of the n-type diffusion layer region, it is possible to know the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern.

Regarding the inspection pattern for confirming the misalignment between the active area forming mask pattern and the p-type diffusion layer area forming mask pattern, the active area forming mask pattern and the n
The mask pattern can be formed in the same manner as the inspection pattern for confirming the misalignment of the mask pattern for forming the mold diffusion layer region, and the mask misalignment amount can be examined by the same measuring method. In Figure 6,
The result of electrically measuring the misalignment amount of the mask pattern for forming the n-type diffusion layer region in the lateral direction is shown by the mask misalignment amount measurement pattern manufactured based on this example and the semiconductor device using the same. The inspection pattern used for measuring the amount of misalignment of the mask pattern for forming the n-type diffusion layer region in the lateral direction has the following structure.

In order to form a P well region on a P type silicon substrate, boron is added at an acceleration energy of 120 keV.
A P well region is formed by implanting 5 × 10 ¹² cm ⁻² and treating for 100 minutes in a nitrogen atmosphere at a temperature of 1150 ° C. to diffuse boron. After forming the P-well region,
An active region is formed by the mask pattern for forming the active region, and boron is injected into the active region at an acceleration energy of 15 keV at 6.5 × 10 ¹³ cm ^-2 . After boron implantation, in order to form an element isolation region, a treatment is performed in an oxygen atmosphere at a temperature of 1000 ° C. for 60 minutes to grow LOCOS to a thickness of 500 nm to form an element isolation region. 1. Boron is added to the active region separated by the element separation region at an acceleration energy of 30 keV.
Inject 2 × 10 ¹² cm ⁻² . A region to be an n-type diffusion layer region is formed by an n-type diffusion layer region forming mask pattern in the active region isolated by the element isolation region, and phosphorus is implanted at 9.0 × 10 ¹² cm ^-2 at an acceleration energy of 40 keV. . After that, a treatment is performed in a nitrogen atmosphere at a temperature of 900 ° C. for 30 minutes. Again, a region to be an n-type diffusion layer region is formed by the n-type diffusion layer region forming mask pattern, and arsenic is implanted at 6.0 × 10 ¹⁵ cm ⁻² at an acceleration energy of 40 keV to form an n-type diffusion layer region. After forming the n-type diffusion layer region, a film thickness of 40
A TEOS film (tetraethylorthosilicate) having a thickness of 40 nm is formed, and a nitride film having a thickness of 40 nm is formed on the TEOS film. 700 nm thick BPSG on nitride film
Form a film. After forming the interlayer film, a contact hole is formed by using a contact hole forming mask pattern. A first aluminum wiring having a film thickness of 700 nm is deposited, and a first aluminum wiring for connecting the bonding pad window and the inspection pattern is formed using the first aluminum wiring forming mask pattern. By using the inspection pattern thus wired, the resistance value of the n-type diffusion layer region can be measured, and the mask in the lateral direction of the active region formation mask pattern and the n-type diffusion layer region formation mask pattern can be measured. The amount of misalignment can be confirmed.

A mask layout of the above-mentioned active region forming mask pattern is shown below. In the mask layout other than the contact hole formation region, the mask pattern has a vertical width of 30 μm, a horizontal width of 1.6 μm, and a pattern pitch of 7.0 μm. The mask layout in the contact hole formation region is such that the vertical and horizontal widths of the mask pattern are 5.0.
μm, and the pattern pitch is 7.0 μm. The number of active region forming mask patterns is 11.

Next, the mask layout of the n-type diffusion layer region forming mask pattern is shown below. In the mask layout other than the contact hole formation region, the mask pattern has a vertical width of 28 μm and a horizontal width of 1.0 μm. The mask pattern pitch is 6.8 μm, and the mask layout is such that the pattern pitch between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern differs by 0.2 μm. The mask layout in the contact hole forming region is 1.0 μm larger than the vertical and horizontal widths of the mask of the active region forming mask pattern, and the n-type diffusion layer region forming mask pattern in the contact hole forming region is the contact hole forming region. The layout is such that all the active region forming mask patterns are covered. The number of n-type region forming mask patterns is 11, which is the same as the above-mentioned active region forming mask pattern.

One of the 11 n-type diffusion layer regions is formed at a position where the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern is zero. The arrangement in which the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern is zero was formed in the central portion of the inspection pattern this time. The n-type diffusion layer regions other than the n-type diffusion layer region where the misalignment amount between the active region formation mask pattern and the n-type diffusion layer region formation mask pattern is zero are the active region formation mask pattern and the n-type diffusion layer region. It is formed at a position displaced by the pattern pitch difference of the forming mask pattern.

To measure the resistance value of the n-type diffusion layer region of the inspection pattern, the active region forming mask pattern and the n-type diffusion layer region forming mask pattern can be obtained by using the above-mentioned resistance value measuring method of the n-type diffusion layer region. The misalignment amount of can be known. In FIG. 6, the horizontal axis represents the misalignment amount (μm) between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern, and the vertical axis represents 1 / resistance value (= current value (mA) /
The voltage value (V) is shown. From the measurement results, 1 / resistance value (1
By reading the maximum value of / kΩ), the misalignment amount between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern can be read. From the produced inspection pattern, it was confirmed that the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern was within ± 0.2 μm.

In the mask layout of the active region forming mask pattern and the n-type diffusion layer region forming mask pattern described above, the misalignment amount between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern is 0.2 μm. You can only check in units. Furthermore, when the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern is to be determined exactly, the above-mentioned mask layout of the active region forming mask pattern and the n-type diffusion layer region forming mask pattern is used. I can not cope. In order to more accurately obtain the amount of misalignment between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern, the pattern pitch difference between the active region forming mask pattern and the n-type diffusion layer region forming mask pattern is set to 0. 2 μm or less. In that case, the difference between the lateral width of the n-type diffusion layer region forming mask pattern other than the contact hole forming region and the lateral width of the active region forming mask pattern other than the contact hole forming region is determined by the difference between the active region forming mask pattern and the n-type It is necessary to make it equal to or less than the pattern pitch difference of the diffusion layer region forming mask pattern.

With respect to the inspection pattern for confirming the misalignment between the active region forming mask pattern and the p-type diffusion layer region forming mask pattern, the mask displacement amount can be more accurately examined by the mask layout described above.

[0042]

According to the semiconductor device of the present invention, since the amount of mask misalignment can be confirmed, even when it is considered that there is a problem with the mask misalignment of the diffusion layer region forming mask pattern due to characteristic deterioration or the like, it is promptly required. Correspondence can be achieved.

[Brief description of drawings]

FIG. 1 is a layout view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a view showing a cross section of a semiconductor device according to an embodiment of the present invention along a section line BB ′.

FIG. 4 is an enlarged plan view of a contact hole formation region of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a wiring diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram showing a result of measuring a mask shift amount of an n-type diffusion layer region forming mask pattern by a semiconductor device using the mask shift amount measurement pattern in the example of the present invention.

FIG. 7 is a plan view of a prior art vernier pattern.

FIG. 8 is a cutting line AA ′ of a prior art vernier pattern.
It is a figure which shows the cut surface of a part.

[Explanation of symbols]

 Reference Signs List 21 chip 22 inspection pattern 23 P well region forming mask pattern 24 active region forming mask pattern 25 n-type diffusion layer region forming mask pattern 40 pattern pitch 41 silicon substrate 42 P well region 43 element isolation region 44a, 44b, 44c n Diffusion layer region 51 Vertical inspection pattern 52 Horizontal inspection pattern

Claims (2)

[Claims] 1. A plurality of element isolation regions formed at equal pitches, active regions formed between the element isolation regions, and formed in the active region at equal intervals with a pitch different from the pitch of the active regions. A semiconductor device having an inspection pattern including a plurality of diffused layers. 2. The inspection pattern comprises a vertical inspection pattern and a horizontal inspection pattern arranged at both ends on a diagonal of the chip, and an element isolation region and a diffusion layer of the vertical inspection pattern extend in the vertical direction of the chip. 2. The semiconductor device according to claim 1, wherein the element isolation region of the lateral inspection pattern and the diffusion layer extend in the lateral direction of the chip.