JPH07182254A - Bus fault testing system - Google Patents

Abstract

PURPOSE:To accurately specify a fault position in the case of testing a fault on a common bus. CONSTITUTION:Each of a CPU 11, a memory 12 and plural I/O parts 13 to 15 connected to the common bus 10 is provided with a test pattern generating circuit part 16, a test pattern receiving circuit part 17, a collated result informing circuit part 18, and a collated result collecting circuit part 19, and when the circuit part 16 in any one of the units 11 to 15 transmits a test pattern to the bus 10, the test pattern is collated by respective circuit parts 17 and collated results are transmitted from respective circuit parts 18 to the circuit parts 19 in the transmitted units and collected. Consequently a fault position on the common bus 10 can be directly detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus failure test system for isolating failure points of a common bus.

[0002]

2. Description of the Related Art In a conventional bus fault test system, as shown in FIG. 3, a test data transmitting / receiving circuit section 36 capable of transmitting / receiving test data and collating transmitted data with received data is provided in a CPU 31, and Memory (hereinafter MM) 32
Also, a test data loopback circuit section 37 that loops back the test data sent from the test data transmission / reception circuit section 36 is provided in each of the I / O sections 33 to 35, and a failure test of the common bus 30 is performed.

That is, when performing a common bus failure test, CP
From the test data transmission / reception circuit unit 36 in U31,
The test data is transmitted to the test data folding circuit unit 37 in the O unit 33. Then, the test data return circuit unit 37 returns the received test data to the test data transmission / reception circuit unit 36 that is the transmission source. In this case, the test data transmission / reception circuit unit 36 collates the transmitted test data with the returned test data, and the common bus 30 between the CPU 31 and the I / O unit 33 is determined from the mismatch of the test data.
To detect the presence or absence of a fault. Following the same procedure, CP
Test data transmitting / receiving unit 36 in U31 and each I / O unit 3
The test data is looped back between the test data looping circuit section 37 in the MM 32 and the test data looping circuit section 37 in the MM 32.
Fault detection of the common bus 30 between the I / O unit 34, the I / O units 34 and 35, and the MM 32 is performed.

[0004]

As described above, in the conventional common bus failure test method, the test data is exchanged between the test data transmitting / receiving circuit section 36 and each test data folding circuit section 37 individually. However, there is a problem that the test takes a long time because it is received. Further, the CPU 31, the MM 32, and the I / O units 33 to 25 connected to the common bus 30.
If a communication error occurs during the period, the test data transmission / reception circuit 3
6, each test data return circuit unit 37 and common bus 30
There was a problem that it was not possible to identify which of the two had a failure.

Therefore, it is an object of the present invention to quickly and accurately identify a fault location when performing a fault test on a common bus.

[0006]

In order to solve such a problem, the present invention provides a test pattern for transmitting a test pattern in a device in which a CPU, a memory and a plurality of I / O units are connected on a common bus. A generation circuit unit, a test pattern reception circuit unit that receives the transmitted test pattern and collates it with an expected value, a collation result reporting circuit unit that transmits the collation result of the test pattern reception circuit unit, and a collation that collects the collation result. The result collecting circuit section is provided in the CPU, the memory, and the plurality of I / O sections. Further, a test line is provided as a part of the common bus, and the test pattern and the matching result are transmitted based on the timing of the control signal on the test line.

[0007]

When a test pattern is transmitted to the common bus from the test pattern generation circuit section of any one of the CPU, the memory, and the I / O sections connected to the common bus, this test pattern is used for each test pattern. The matching result data is transmitted from each matching result reporting circuit unit and collected by the matching result collecting circuit unit that is the transmission source of the test pattern while being matched by the receiving circuit unit. As a result, the failure location at the time of the failure of the common bus can be specified accurately. Further, the test pattern and the collation result are transmitted based on the timing of the control signal on the test line provided as a part of the common bus. As a result, the transmission of the same test pattern is checked by a plurality of test pattern receiving circuit units, so that it is possible to quickly perform a failure test on the common bus.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an apparatus to which a bus failure test system according to the present invention is applied. In the figure, 10 is a common bus, and the common bus 10 has a CPU
11, the MM 12, and the I / O units 13 to 15 are connected. Then, the CPU 11, the MM 12, and the I / O units 13 to 1
Each of the units 5 accommodates units indicated by reference numerals 16 to 19 for testing the failure of the common bus 10.

That is, 16 is a test pattern generating circuit section for transmitting a test pattern, 17 is a test pattern receiving circuit section for receiving the transmitted test pattern and collating it with expected value data, and 18 transmitting the collated result. A collation result reporting circuit unit, and 19 is a collation result collecting circuit unit that collects collation results. Then, the CPU 11, the MM 12, and the I / O unit 1
While transmitting the test pattern data to the common bus 10 from the test pattern generating circuit unit 16 of any of 3 to 15,
The collation result data transmitted from each of the collation result reporting circuit units 18 is collected by the collation result collection circuit unit 19 of the transmission source, whereby the common bus fault detection test is performed.

Next, FIG. 2 shows an example of a time chart of the common bus failure test, and the operation of the failure test of the common bus 10 in this apparatus will be described based on this time chart. Here, the address bus, the data bus, and the control lines CT1 and CTn shown in FIGS. 2 (a), 2 (b), 2 (c), and 2 (d).
Is a component of the common bus 10, and is also shown in FIG.
Similarly, the test lines TST1 and TST2 shown in (f) are also included in the common bus 10, and these test lines TST1 and TST2 are included.
The common bus 10 is tested at the level switching timing of "0" and "1". That is, when the test line TST1 is "1", the normal state is shown, and when the test line TST1 is "0", the common bus test is shown. When the test line TST1 is "0", the test line TST2 is "0" to indicate that the test pattern is being transmitted, and "1" to indicate that the verification result data is being transmitted.

That is, for example, first in the test pattern generation circuit section 16 in the CPU 11, when both the test lines TST1 and TST2 are "0", the address bus, the data bus,
And test pattern data that can be checked by all the control lines are transmitted to the common bus 10. At this time, the MM 12 and each test pattern receiving circuit unit 1 of each I / O unit 13 to 15
At 7, the test pattern on the common bus 10 is fetched and collated with the expected value data stored and held inside.

The result of this collation (normal, abnormal) is M
The M12 and the collation result reporting circuit unit 18 of each of the I / O units 13 to 15 detect the collation result reporting circuit unit 18 of the MM12 when the states of the test lines TST1 and TST2 are “0” and “1”, respectively. From then on, the device number of itself is added to the address bus and the total result is added to the data bus at different timings, and the result is sent to the common bus 10. However, in this case, the collation result reporting circuit unit 18 in the CPU 11 that is the transmission source of the test pattern does not send the collation result to the common bus 10 but directly reports it to its own collation result collecting circuit unit 19.

In the collation result collection circuit section 19 in the CPU 11, data other than the above collation result of itself is "0" and "1" for the respective states of the test lines TST1 and TST2.
Then, the collation result data transmitted to the common bus 10 from the respective collation result reporting circuit units 18 at different timings are collected. And as a result of this collation data report,
Also, the isolation of the faulty part of the common bus 10 is judged depending on the presence or absence of the report result, and the judgment is made as follows.

That is, as the first determination condition, the CPU
When all the test pattern data transmitted from the test pattern generation circuit unit 16 in 11 is normal and is reported to the collation result collection circuit unit 19 in the CPU 11, it is determined that the common bus 10 has no fault location. As the second determination condition, when all the test pattern data transmitted from the test pattern generation circuit unit 16 in the CPU 11 is abnormal and is reported to the verification result collection circuit unit 19 in the CPU 11, the CPU
It is determined to be 11 abnormalities. As the third determination condition, C
When the test pattern data transmitted from the test pattern generation circuit unit 16 in the PU 11 is reported to the collation result collection circuit unit 19 in the CPU 11 as normal only in the CPU 11 and all other abnormalities, it is determined that the common bus 10 is abnormal. To do.

As the fourth determination condition, the test pattern data transmitted from the test pattern generation circuit section 16 in the CPU 11 is the CPU 11, MM 12 and each I / O section 1.
CPUs 3 and 14 are normal and only the I / O unit 15 is abnormal.
If the result is reported to the collation result collection circuit unit 19 in 1,
The / O unit 15 is determined to be abnormal. Similarly, the test pattern data transmitted from the test pattern generation circuit unit 16 in the CPU 11 is abnormal only in the MM 12, respectively, and the I / O unit 1
CPU 3 as abnormal only in 3 and abnormal in I / O unit 14
When the result is reported to the collation result collecting circuit unit 19 in 1, the MM 12, the I / O unit 13, and the I / O unit 14 are determined to be abnormal.

As a fifth judgment condition, the test pattern data transmitted from the test pattern generation circuit section 16 in the CPU 11 is the CPU 11, MM 12 and each I / O section 1.
Nos. 3 and 14 are reported as normal to the collation result collecting circuit unit 19 in the CPU 11, and when no collation result is reported only to the I / O unit 15, it is determined that the common bus after the I / O unit 15 has been disconnected. Similarly, when the test pattern data transmitted from the test pattern generating circuit unit 16 in the CPU 11 reports only the MM 12 as a collation result and the other as normal, the I / O unit 13 reports the collation result. Not reported otherwise, and I / O unit 1
When only the verification result of 4 is not reported and the others are reported as normal, the MM 12, the I / O unit 13, and the I / O unit 14 are respectively reported.
It is determined that the common bus around is abnormal.

In the above description, the test pattern data transmitted from the test pattern generating circuit section 16 in the CPU 11 is received by the test pattern receiving circuit section 17 of the MM 12 and each of the I / O sections 13 to 15, and the verification is performed. The result is CPU11
In this example, the collation result collection circuit unit 19 in FIG. 1 collects the test pattern data by using the test pattern generation circuit unit 16 of each unit other than the CPU 11 so that the collation result is obtained from each unit. By doing so, the abnormal portion can be specified more accurately. In this way, the CPU 11, M
M12 and the test result data sent from each of the check result reporting circuit units 18 by sending the test pattern data from the test pattern generating circuit unit 16 of any of the I / O units 13 to 15 onto the common bus 10. Is collected by the collation result collection circuit unit 19 of the transmission source, it is possible to directly detect the failure point at the time of the common bus failure.

[0018]

As described above, according to the present invention, a CPU, a memory, and a plurality of I / Os connected to a common bus.
The test pattern generating circuit unit, the test pattern receiving circuit unit, the collation result reporting circuit unit, and the collation result collecting circuit unit are provided in each unit, and the test pattern is transmitted from any one of the test pattern generating circuit units onto the common bus. And collate this test pattern in each test pattern receiving circuit section,
Since the data of the collation result is transmitted from each collation result reporting circuit unit to the collation result collection circuit unit of the transmission source of the test pattern and collected, the failure point at the time of the common bus failure can be directly detected, Therefore, the failure location can be specified accurately. In addition, a test line is provided as part of the common bus, and test patterns and matching results are sent based on the timing of control signals on this test line, so multiple tests can be performed for the same test pattern. The pattern receiving circuit section can perform the collation, and therefore the common bus failure test can be performed quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an apparatus to which a bus failure test method according to the present invention is applied.

FIG. 2 is a time chart showing a test operation of the above apparatus.

FIG. 3 is a block diagram of a conventional device.

[Explanation of symbols]

 10 common bus 11 CPU 12 memory (MM) 13 to 15 I / O unit 16 test pattern generation circuit unit 17 test pattern receiving circuit unit 18 collation result reporting circuit unit 19 collation result collection circuit unit TST1, TST2 test line

Claims (2)

[Claims] 1. A device in which a CPU, a memory, and a plurality of I / O units are connected to a common bus, a test pattern generation circuit unit for transmitting a test pattern, and an expected value obtained by receiving the transmitted test pattern. The CPU, the memory, and the plurality of I / Os are provided for the test pattern receiving circuit unit for matching, the matching result reporting circuit unit for transmitting the matching result of the test pattern receiving circuit unit, and the matching result collecting circuit unit for collecting the matching result. A bus failure test method, characterized in that it is provided in an O section and isolates a failure point of the common bus. 2. The bus fault test method according to claim 1, wherein a test line is provided as a part of the common bus, and the test pattern and the verification result are transmitted based on a timing of a control signal on the test line. Bus failure test method characterized by performing.