JPH07177120A - Signal multiplexer - Google Patents

Abstract

PURPOSE:To attain efficient multiplexing of a signaling by utilizing the property that the signaling multiplexed with a main signal is not always added to all main signals. CONSTITUTION:It is controlled that each signaling is allocated to a time slot corresponding to a channel number similarly to the case with a main signal and only a channel allocated with effective signaling is written in a buffer memory 13 under the control of a write control section 20. That is, }channel corresponding to data or the like not requiring the signaling is disregarded and the result is written in the buffer memory 13. A read control section 16 reads data written in a prescribed order as a conventional multiplexer to multiplex the data. When a multiplexed signal is received and decoded, the processing reverse to those above is implemented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal multiplexer for efficiently multiplexing signaling used for communication control, which is multiplexed with a main signal such as voice or data and sent to a transmission line. Regarding

[0002]

2. Description of the Related Art For example, a network for connecting telephone lines and computer lines to each other may be provided in a company. This kind of network is also installed in intelligent buildings. In such a network, signals are multiplexed in order to effectively use a transmission line while connecting many terminals to each other.

FIG. 2 shows a block diagram of a configuration example of a signal multiplexer used for such a purpose. As shown in the figure, for example, an exchange 2 is connected to the transmission line 1, and such a signal is output to the transmission line 4 via the signal multiplexer 3. Further, for example, the exchange 2 is not used for data transmission between computers, and the output signal of the computer is directly input from the transmission line 5 to the signal multiplexer 3.
The multiplexing is performed.

FIG. 3 shows a block diagram of a configuration example of such a signal multiplexing apparatus. As shown in the figure, in the signal multiplexing device, the main signal 6 composed of an input audio signal, data signal, etc.
And a signaling 7 for communication control are received, and a multiplexing frame is generated using a voice data signal multiplexer 8 and a signaling signal multiplexer 9. afterwards,
These are multiplexed by the synthesizing / multiplexing unit 10 and sent to the transmission path 4.

The above-mentioned signaling is a general term for signals such as an on-hook signal, an off-hook signal and a dial pulse which are transmitted and received between a telephone and an exchange together with a voice signal when connecting a telephone line. Therefore, such signaling is involved in data transmission and voice transfer between computers connected via an exchange, but it is an unnecessary signal for data transmission between computers directly connected to each other without an exchange. The voice data signal multiplexer 8 and the signaling signal multiplexer 9 multiplex an input signal in a predetermined format to synthesize and multiplex the signal.
Send to 0. The synthesizing / multiplexing unit 10 synthesizes these and sends them to the transmission line 4.

FIG. 4 is a diagram showing the structure of an original signal input to the signal multiplexer. As shown in the figure, for example, the main signal is in the order of channels CH1, CH2, CH3, ... As shown in (a), and time slots TS1 and TS shown in (b).
2, TS3, ... Assigned to the audio data signal multiplexer 8 shown in FIG. In addition, the signaling also includes channels CH1, CH2, CH3, ... Shown in (c) of the figure.
As shown in (d), those corresponding to are assigned to the time slots TS1, TS2, and TS3 and input to the signal multiplexing apparatus for signaling 9 (FIG. 3).

FIG. 5 shows a block diagram of a conventional signal multiplexer for signaling. This device uses signaling 7
Is composed of a buffer memory 13 for receiving the data, a write counter 14 and a read counter 15. The write counter 14 is composed of a counter circuit for supplying a write address to the buffer memory 13.
The read counter 15 reads the data from the buffer memory 13 in the set order and multiplexes the frame 12
It is composed of a counter circuit for obtaining. The write counter 14 stores the signaling 7 in the buffer memory 13 in the order of input, and the read counter 15 outputs a read address for reading in order to multiplex the signaling of each channel to generate a frame of a predetermined format.

FIG. 6 shows an explanatory view of a conventional signal multiplexing example. As shown in this figure, for example, time slot TS1
Is assigned to the channel CH1 and the time slot TS4 is assigned to the channel CH4.
When the channel CH5 signaling is assigned to TS5 and the channel CH6 signaling is assigned to TS6, data is stored in this order in the buffer memory 13 shown in FIG.

As shown in the figure, the input signal is input in this order from time slots TS1 to TS7. Then, as described above, the shaded time slot, for example, TS2, is a time slot assigned to the main signal that does not require signaling. Even in this case,
Signals are written in the buffer memory 13 shown in FIG. 5 in the order of input, and dummy data are written in the time slots TS2, TS3, and TS7. Such signals are multiplexed by the read counter 15, and the data in the format as shown in the figure are collectively read in the first time slot on the output side and sent out to the transmission path.
The shaded area corresponds to the area from which invalid signaling was read.

[0010]

By the way, the above-mentioned conventional signal multiplexer has the following problems to be solved. The voice signal and data transmitted through the network as described above generally have a certain redundancy, and the data compression method adopted in facsimile and various other fields can be adopted. As a result, for example, it is possible to transmit an audio signal transmitted by 64 kilobits per channel and transmitted by 32 kilobits per channel. Therefore, when the number of lines is greatly increased, the transmission capacity can be doubled on the same transmission line.

Further, when the number of lines to be transmitted does not change, the transmission line can be replaced with one having a small transmission capacity to reduce the maintenance cost of the equipment. Therefore, FIG.
In the case of the device shown in (1), the input signal is compressed on the output side of the audio data signal multiplexing device 8, and these signals can be transmitted using the transmission path 4 having a lower transmission capacity.

However, the signaling 7 is, by its nature,
Redundancy is extremely low and is not suitable for compression processing. Therefore,
If the main signal 6 and the signaling 7 are present in the same channel, the transmission capacity of the transmission line cannot be reduced for signaling transmission, and there is no point in compressing the main signal 6.

The present invention has been made by paying attention to the above points, and utilizes the property that signaling does not necessarily accompany all main signals, and achieves efficient multiplexing of signaling to achieve transmission capacity. It is an object of the present invention to provide a signal multiplexing device that compresses the.

[0014]

A signal multiplexer according to the present invention accepts signaling used for communication control, which is multiplexed with a main signal and sent to a transmission line, separately from the main signal, In the case of generating a multiplexed frame, the signaling is assigned to the time slot corresponding to the channel number to receive the signaling like the main signal, and the write address for writing the input signal to the buffer memory. And a read control unit for supplying a read address for multiplexing the signaling of each channel to the buffer memory and reading it so as to generate the frame. Is
According to a preset standard, a write address for changing the combination of the channel number and the corresponding time slot is supplied so that only the channel for which signaling is valid is written in the buffer memory.

[0015]

This device allocates each signaling to the time slot corresponding to the channel number similarly to the main signal and accepts it, and controls to write only the channel to which valid signaling is allocated to the buffer memory under the control of the write controller. . That is, the channel corresponding to the data that does not require signaling is ignored and written in the buffer memory. The read control unit reads the written data in a fixed order as in the past and multiplexes the data. When receiving and decoding the multiplexed signal, the procedure opposite to the above is performed. Since the nature of the input signal is known in advance, the operator sets such conditions for the decoder of the write control unit.

[0016]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a signal multiplexer of the present invention. This device has a buffer memory 13
And a write control unit 20 and a read control unit 16. As described above, the buffer memory 13 receives the signaling 7 multiplexed with the main signal and transmitted to the transmission path. The write controller 20 is a part that supplies a write address for writing a signal to be input to the buffer memory 13. Further, the read control unit 16 is a unit that supplies a read address for reading to the buffer memory 13 so as to multiplex the signaling of each channel to generate a fixed multiplexed frame 12. The configurations of the buffer memory 13 and the read control unit 16 in the present invention are the same as those of the conventional device. That is, the read control unit 16 and the read counter 15 shown in FIG. 5 may have the same configuration.

On the other hand, the write controller 20 is provided with a counter 21 and a decoder 22. Counter 21
Is composed of a counter circuit used in a conventional device for sequentially designating the writing order of input signals. In addition, the decoder 22 receives the write address signal from the counter 21 and outputs the write address so as to write only the channel for which the signaling is valid in the buffer memory 13 according to a preset procedure. Composed.

This allows the signaling 7 to be input.
Is assigned so that the time slot corresponding to the channel number becomes one-to-one, but in the case of writing, signal writing is not performed in the time slot to which invalid signaling is assigned. In this way, the combination of the channel number and the corresponding time slot is changed.

The specific operation of the above apparatus will be described in more detail. FIG. 7 is an operation explanatory diagram of the device of the present invention. First, as shown in this figure, it is assumed that the signaling channels CH1 to CH6 are assigned to the time slots TS1 to TS7 of the input signal, respectively. In this case, as explained above, the time slots TS2, T
Signaling corresponding to the main signal assigned to S3 and TS7 is unnecessary and therefore invalid.

That is, the signals of these time slots are
For example, it is a slot for data transmission in which computers are directly connected. The nature of such data has been clarified in advance during system design. Therefore, in the device of the present invention, the decoder 2 shown in FIG.
For No. 2, the address translation table is stored so that the time slots of valid signaling and invalid signaling are processed separately. The structure of the address conversion table will be specifically described with reference to FIGS. 7 (d) and 7 (e).

The apparatus of the present invention, when there is such an input signal, as shown in FIG.
Only valid signaling for 1, TS2, TS3, TS4 is picked up and written. That is, channel CH1 for time slot TS1, channel CH4 for time slot TS2, and channel C for time slot TS3.
Signaling of channel CH6 is assigned to H5 and time slot TS4, and is continuously written in the buffer memory 13.

The counter 21 shown in FIG. 1 corresponds to the time slot number of the input signal shown in FIG.
As shown in (d), the address signals from "1" to "7" are output. On the other hand, the decoder 22 is shown in FIG.
As shown in (e), when the output of the counter is "1", it is "1", when it is "4", it is "2", when it is "5", it is "3", and when it is "6", it is "4". Is output. In other cases, the address signal is not output. The address conversion table may be configured with such simple contents. As a result, the writing of signaling as shown in FIG. 7B is performed.

The read control section 16 shown in FIG. 1 calls up a signal in the same procedure as the conventional device. Therefore, FIG.
As shown in (c), in the first read slot, data of the channels CH1, CH4, CH5, and CH6 are multiplexed and output following the data "F" indicating the time slot delimiter. It should be noted that such a signal must be restored by a completely corresponding process at the decoding stage. Therefore, the read control unit of the decoding unit (not shown) is required to have a unit for performing the address conversion reverse to that of the write control unit 20 shown in FIG. 1 and outputting the data.

FIG. 8 is a diagram (No. 2) for explaining the operation of the apparatus of the present invention. In the device of the present invention, as shown in this figure,
For example, if all the time slots TS1 to TS7 are assigned to valid signaling, the same operation as that of the conventional apparatus is performed. That is, in this case, the decoder 22 shown in FIG.
As shown in (d) and (e), the address signal output from the counter 21 is directly supplied to the buffer memory 13.

The present invention is not limited to the above embodiments. In the above embodiment, the write controller 20 is replaced by the counter 2.
1 and the decoder 22 have been described, but a circuit that supplies an address that changes the combination of the channel number and the corresponding time slot so that only the channel for which the signaling is valid is written in the buffer memory by the above procedure. As long as it has any configuration.

[0026]

According to the signal multiplexing apparatus of the present invention described above, when there is valid signaling and invalid signaling due to the nature of the main signal, these are assigned to constant time slots and stored in the buffer memory 13. When an input is made, the combination of the channel number and the corresponding time slot is changed so that only the channel for which the signaling is valid is written in the buffer memory, so that useless multiplexing of the signaling can be avoided.

Thus, when trying to reduce the transmission capacity of the transmission line by compressing the main signal, if the main signal does not require signaling, the signaling is also multiplexed. The band can be efficiently and apparently compressed, and the transmission capacity of the transmission line on the output side can be reduced as a whole.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal multiplexer of the present invention.

FIG. 2 is a block diagram of a usage example of a signal multiplexing device.

FIG. 3 is a block diagram of a configuration example of a signal multiplexing device.

FIG. 4 is an explanatory diagram of a configuration of an original signal.

FIG. 5 is a block diagram of a conventional signal multiplexer for signaling.

FIG. 6 is an explanatory diagram of a conventional signal multiplexing example.

FIG. 7 is an operation explanatory view (1) of the device of the present invention.

FIG. 8 is an operation explanatory view (No. 2) of the device of the present invention.

[Explanation of symbols]

 7 Signaling 12 Multiplexed Frame 13 Buffer Memory 16 Read Control Section 20 Write Control Section

Claims (1)

[Claims] 1. A signal for receiving a signal multiplexed with a main signal and sent to a transmission line and used for communication control in advance separately from the main signal to generate a multiplexed frame. Similarly to the main signal, a buffer memory assigned to a time slot corresponding to a channel number and received, a write controller for supplying a write address for writing an input signal to the buffer memory, and a buffer memory for the buffer memory , A read control unit that multiplexes the signaling of each channel and supplies a read address for reading so as to generate the frame, and the write control unit is a channel for which signaling is effective according to a preset standard. Write only to the buffer memory. Signal multiplexing apparatus characterized by supplying a write address to change the combination of Le numbers and corresponding time slot.