CN1067195C - High-speed multiplexer and its implementation - Google Patents
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- CN1067195C CN1067195C CN96109329A CN96109329A CN1067195C CN 1067195 C CN1067195 C CN 1067195C CN 96109329 A CN96109329 A CN 96109329A CN 96109329 A CN96109329 A CN 96109329A CN 1067195 C CN1067195 C CN 1067195C
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Abstract
The present invention provides a high-speed multiplexer used in a spacecraft, which comprises seven part of three buffer circuits of input data, a guiding-head data buffer circuit, a generation circuit of filling data, a processing circuit of output data and a control circuit of a multiplexing process. The present invention can carry out asynchronous multiplexing to make high-speed, medium-speed and lower-speed data flow generated by different signal sources on the spacecraft become serial data flow according to a CCSDS standard by the concepts of packet-division remote-measurement and a virtual channel. Thus, the requirement of transmitting various data flow on the same physical channel by time division multiplexing is realized.
Description
High-speed multiplexer of the present invention is to belong to space technology, be meant a kind of spacecraft that is used for especially, as the data that on space station, space platform, the satellite various various information sources produced, become the serial datum same physical channel of flowing through as still image, voice, scientific experiment data, engineering parameter etc. according to the form multiple connection of the Aerospace Data Systems standard recommendation book of the international space data system consultancy committee (CCSDS) issue and finish the equipment and the method for transfer of data.
Artificial satellite, spacecrafts such as space station need transmit science data and engineering parameter earthward, normally realize this transfer of data by remote measurement.Traditional remote mode is that the individual data with measured parameter manages, and each measured parameter is arranged on the ad-hoc location in the form of the similar matrix form that is made of " road " and " frame ".The start bit of frame is equipped with special identification code and is called synchronous code, and all parameters are to rely on the relative position of synchronous code to be distinguished.
Along with the development of space technology, this traditional remote mode can not adapt to the requirement of modern spacecraft to transfer of data.Modern spacecraft often need transmit the multiple information such as engineering parameter that comprise image, voice, scientific experiment data, instrument and equipment on a physical channel.These information often do not produce with fixing speed, sometimes also need transmitting burst information, simultaneously because space operation is permobile, for each countries and regions provide mutual support, the demand that has caused extensive international cooperation so just needs a cover and not only adapts to modern spacecraft requirement but also be convenient to the standard of the transfer of data of support mutually.Comply with this demand international space data system Advisory Board and begin to have issued successively a series of standard recommendation books mid-term, be called for short the CCSDS standard about spatial data transmission from the eighties.
Having introduced two important notions in the CCSDS standard is packet telemetry and pseudo channel.Be different from traditional remote measurement, packet telemetry is that unit manages with the data acquisition system, and this set is contained in the data field that is called " bag ".To seldom restriction of this set, the code bit number of only recommending its data is the integral multiple of byte.The data field of bag adds that packet header constitutes complete bag, and bag is the practical object of data management.Pseudo channel is that a tangible physical channel logically is divided into maximum 64 pseudo channels.The transmission frame that can transmit on each pseudo channel separately is called virtual channel data unit unit (VCDU).All there is a top guide part in each virtual channel data unit unit, and 6 pseudo channel identification codes in the dependence top guide are distinguished the data of different pseudo channels.
The CCSDS standard has improved the flexibility of transfer of data and the utilance of channel greatly for the transfer of data of modern spacecraft provides a unified standard.Various images, the data of various information sources such as science data can be put into different pseudo channels, or in the bag of the different application process of same pseudo channel, transmit in same physical channel with time division way.But, still there be not the off-the-shelf equipment and the method for this process of realization owing to this processing procedure more complicated.
The objective of the invention is to design a kind of novel structure, advanced in performance, reliable, economical and practical, can finish according to the CCSDS standard the various data on the spacecraft are carried out equipment and the method that multiple connection is handled.
The equipment that the present invention has realized, the output speed after its multiple connection is 8.448Mbps, is provided with A, B, three data input ports of C, A wherein, the B mouth is two independently serial data input ports, each mouthful provides two road signals by the user, and one the tunnel is data, and another road is the drive clock of these data.The C mouth is the 1553B bus interface, provides two tunnel redundant each other bus interface according to American army mark MIL-STD-1553B standard.Wherein the flank speed of the data of A, B mouth input is designed to 7.2Mbps, and the C mouth is 200kbps.The data input rate does not have the lower limit constraint, and allows to suspend or change in input process the speed of input.Arbitrary moment will can not produce loss of data as long as the input data rate sum of three mouths is no more than 8Mbps.Data input rate of each mouthful and multiplexer internal clocking are independently uncorrelated and allow input rate to change under the prerequisite that is no more than the highest permission speed.Multiple connection is to adopt asynchronous system, and the very strong adaptivity and the flexibility of use are arranged.Dateout is divided into 4 pseudo channels, its A, B by the CCSDS standard, the data of three mouths of C respectively account for a pseudo channel, and another pseudo channel is used to send padding data, works as A, B during three mouthfuls of inputs of C data deficiencies, need send padding data in order to make output stream be unlikely interruption.
The present invention is according to CCSDS Aerospace Data Systems standard recommendation book, and " senior to the rail system, " (CCSDS701.0-B-2 blue book, in November, 1992) has selected bit stream service processing mode wherein for use for network and the explanation of data link structure.Transmission frame length is elected 512 bytes as, and virtual channel data unit unit (VCDU) length is 508 bytes, and form is as follows:
| VCDU main stem head | |||||||||
| Synchronous 32 | Version number 2 | | VCID 6 | VCDU counter 24 | Signal domain | VCDU top guide error control 16 | B-PDU top guide 16 | B-PDU bit stream data district 498 bytes | |
| Playback sign 1 | Standby 7 | ||||||||
Synchronous code: be defined as 32 by CCSDS, be expressed as 1ACFFC1D by 16 systems.
VCDU dominates head part:
" 01 " sign virtual channel data unit unit is got by version number (position 0～1).
Spacecraft identifier (SCID) (position 2～9).
Virtual channel identifier (VCID) (position 0～15): arranged 4 pseudo channels: channel A wherein, B is used for transmitting the high-speed data of serial input, and channel C is used for transmitting the data of the low rate of sending into through 1553B bus mouth, and channel D is for filling channel.
Virtual channel data unit unit counter (position 16～39): the data cell to each pseudo channel counts separately, binary system, mould 224.
Signal domain (position 40～47):
Playback sign (position 40): " 0 "=in real time VCDU, " 1 "=playback VCDU.
Keep backup domain (41～47): this 7bits is kept by CCSDS, at present full reset.
VCDU top guide error control (position 48～63): the version number territory of 2 bits, the VCDU identifier domain of 14 bits and the signal domain of 8 bits are protected by error control and error correcting code.
The mechanism that produces VCDU top guide error control territory is used RS (10, the 6) sign indicating number that shortens, and the parameter of institute's code selection is as follows:
(1). " J=4 ", the sign indicating number position of each R-S symbol.
(2). " E=2 ", the symbol error-correcting ability that the R-S code word is interior.
(3). the territory generator polynomial is: on GF (2), F (x)=X
4+ X+1.
(4). sign indicating number is generated as multinomial:
At GF (2
4) on:
g(x)=(x+α
6)(x+α
7)(xα
8)(x+α
9)
F(α)=0
α
6=1100，α
7=1011，α
8=0101，α
9=1010
GF(2
4)
9(x)=x
4+α
3x
3+αx
2+α
3x+1
α
0=0001, α
3=1000
α
1=0010
(5). transmission is from leftmost position in the R-S symbol; For example
α
3=1000
Transmission will be to pass one " 1 " earlier, follow then 3 " 0 ".VCDU data cell part:
B-PDU bit stream stipulations data cell:
Top guide part: position (0～1): standby, now be changed to " 00 ".
Position (2～15): the bit stream data pointer, be changed to " 1 " entirely, being illustrated in the bit stream data district does not have padding data.
The bit stream data district: place the defeated bit stream data of tendency to develop, length is 498 bytes.
In order to guarantee suitable transition density, avoid long-time appearance " 0 " or " 1 ", need to get up with a pseudo random sequence and every XOR except that synchronous mark.According to the regulation of CCSDS, the pseudo random sequence generator polynomial is:
h(x)=X
8+x
7+X
5+X
3+1
This sequence repeats after 255, and sequencer repeats to be initially full one state during each synchronous mark.Initial 40 of this sequence is: 1,111 1,111 0,100 1,000 0,000 1,110 1,100 0,000 1,001 1010
High-speed data will be cut to the section of 498 bytes in high-speed multiplexer, put into top B-PDU bit stream data district, will be after ground receives according to virtual channel identifier and VCDU counter, and the number stream that is stitched together and recovers original.
Data for the middle low rate that transmits through the 1553B bus are handled its packing, are distinguished with different application process identifiers.Correctly unpack in order to simplify the operation and to be convenient to ground, the packet length unification of all application processes is defined as 498 bytes, so that each bag embeds in the B-PDU bit stream data district exactly.In each virtual channel data unit unit, adorn a bag so just, make the starting point of synchronous code and each packet that fixing position relation be arranged, guarantee the reliability that unpacks.The form of packet adopts following form by the regulation of CCSDS:
Leading head
| Leading head | ||||||||
| The bag sign | Packet sequence control | Packet length | Secondary top guide | Source data | ||||
| Version number | Type | Secondary top guide sign | The application process identifier | Segmentation marker | The source sequence counting | |||
| 3 | 1 | 1 | 11 | 2 | 14 | 16 | Variable | |
| 2 bytes | 2 bytes | 2 | 492 bytes | |||||
The bag sign:
(1) version number (position 0～2), version number are that " 000 " is complete source packet format.
(2) type (position 3) is got " 0 " expression remote measurement bag.
(3) secondary top guide sign (position 4), this is masked as " 1 ", in the bag of expression source secondary top guide data is arranged, for " 0 " expression does not have secondary top guide.
(4) application process identifier (position 5～15), this 11 bit is used for identifying the specific application process of generation source bag.
Packet sequence control:
(1) segmentation marker (position 0,1) is got " 11 " and is represented not fragmented packets.
(2) source sequence counting (position 2～15), this 14bit territory comprises the direct sequential counting (mould 16384) of each bag, is produced by each special application process on the spacecraft.
Packet length (16bit), this 16 bit comprise the binary counting " C " of an order, and it represents the length (is unit with the byte) of the remainder of this back, territory.The value of " C " equals the spare word joint number and subtracts 1.
The invention is characterized in: produce seven parts such as circuit, dateout treatment circuit, multiple connection control circuit and constitute by A, B, C three input data buffers, top guide data buffer, padding data, wherein, A, B, C three input data buffers, top guide data buffer link to each other through inner 8 bit data bus with the data outlet that padding data produces circuit, and be connected to the data output processing circuit through this 8 bit data bus, the multiplexer control circuit links to each other with other six partial circuit respectively, produces control signal control multiple connection process; Control by hardware logic and microcomputer is passed through the standard of the middle low rate data streams of 1553B bus interface input according to international space data system Advisory Board (CCSDS) with two tunnel serial high speed and a tunnel, the notion asynchronous multiplexing of utilization packet telemetry and pseudo channel becomes serial datum stream, its output data rate can reach 8.448Mbps, every road serial input data flank speed can reach 7.2Mbps, 1553 mouthfuls of input rates can reach 200Kbps, under the condition that is no more than the highest permission speed, the variation of input data rate there is adaptivity; The serial data input interface is to adopt external clock to drive, through serial/parallel conversion by external clock behind 8 frequency divisions pulse automatically data are deposited in cache way in first in first out (FIFO) memory; Multiplexer is established a MIL-STD-1553B bus data interface, receive the data of importing through the 1553B bus by the special purpose interface chip, and the data of buffer memory input in interface chip, when the data of input constituted a packet just, just controlling by CPU again, a packet moved on in the buffer that is made of the FIFO memory; The data that its output processing circuit is finished synchronous code generation, pseudo noise code generation, pseudo noise code and virtual channel data unit unit (VCDU) by hardware logic electric circuit fully are XOR and the switching of yardage stream and VCDU data synchronously by turn; The generation of its pseudo noise code is to adopt one 8 shift register to constitute through suitable feedback circuit, the initialization of its state is to utilize to switch its serial input terminal realization, between the synchronous code period of output, the serial input terminal of shift register is put high level, shift register is all put " 1 " through clock pulse, thereby realized initialization; The control of its multiple connection process is the control impuls and the mode that combines with the microcomputer software program that adopts hardware to produce, to cooperate be to produce pulse and cause that CPU interrupts by being carved in due course by hardware to strict sequential between hardware pulse and the software control, thereby the startup interrupt service routine is realized; Eight kinds of sequential require complicated very accurately control signals, are to utilize PROM in advance its wave mode to be stored, and drive coincidence counter with internal clocking then, thereby the address that produces PROM is with the output and realizing continuously automatically of the signal of the control wave mode of being deposited; The capacity of data memory input is selected 4 times of VCDU length for use, its cleverly control strategy be to utilize CPU by checking the half-full signal of each buffer, thereby decision should discharge the data of which buffer next time, and the top guide data of making this channel deposit the top guide data buffer in and realize, each data of reading from buffer are not more than 1/4 of capacity register, cause that the dateout interruption can not cause overflowing of buffer yet thereby guaranteed neither buffer to be read sky.
The present invention is simple in structure; The control principle design is ingenious, and reliable operation is used flexibly, and the present model machine of realizing has data output rate and other performance recited above of 3 input ports and 8.448Mbps.Can improve output data rate as required according to same principle, increase the quantity of data input port.
The invention will be further described below in conjunction with accompanying drawing, and wherein: Fig. 1 is the simple principle block diagram.Fig. 2 is detailed theory diagram.Fig. 3 produces circuit for synchronous code.Fig. 4 produces circuit for pseudo noise code.Fig. 5 produces circuit for control impuls.Fig. 6 is the control strategy schematic diagram.Fig. 7 is software workflow figure.Fig. 8 is that software workflow figure (interrupt service routine 1) Fig. 9 is software workflow figure (interrupt service routine 0)
Circuit theory of the present invention and control strategy are as follows:
Fig. 1 has provided basic structure block diagram of the present invention, the present invention includes seven parts as seen from the figure:
1.A mouthful input-buffer circuit is used for the high-speed data of buffer memory by A mouth serial input.
2.B mouthful input-buffer circuit is used for the high-speed data of buffer memory by B mouth serial input.
3.C mouthful input-buffer circuit, be used for buffer memory by the C mouth in the input of 1553B bus, low-rate data.
4.VCDU the top guide buffer circuit is used for the top guide of buffer memory virtual channel data unit unit and the top guide of bit stream stipulations data cell.
5. padding data produces circuit, is used to produce the data of filling channel.
6. the dateout treatment circuit is used to produce synchronous code, and pseudo noise code also carries out the data of virtual channel data unit unit to export behind the XOR with sequence with puppet before output.
7. control circuit is used for the control of above 6 partial multiple courses of work.
Accompanying drawing 2 has provided detailed diagram of the present invention.
Among the figure 1., 2. two parts have shown A, B dual serial input buffer principle.The data (data) of user's input are under the effect of its drive clock (clock), at first become parallel data through string and conversion (s/p) device, clock pulse deposits the parallel input data that is converted to a byte wide in this data buffer (Buffer) through 8 frequency division rear drive first in first out (FIFO) data buffers.Among the figure: MR is the reset signal of buffer, and HF is the half-full index signal of buffer, and the data in FIFO surpass a half, and HF will become low level by high level.R, RA are the control signal of reading of FIFO, and the data when R and RA are " 1 " among the FIFO are read out a byte.
3. shown C mouth input buffer principle among the figure.The 1553B interface is the 1553B communication protocol process chip of a special use among the figure, can finish the data communication on the 1553B bus automatically.Interface chip produces the CPU in the interrupt signal notice control circuit when the data by 1553 bus interface output are a complete packet just, under the control of CPU, deposit whole packet in buffer Buffer C through inner microcomputer bus, with Buffer A, B same buffer also be to constitute by FIFO.
4. the principle that has shown virtual channel data unit unit (VCDU) top guide buffer among the figure.Deposit the top guide data in this buffer by the CPU in the control section by inner microcomputer bus, the control impuls RV that is produced by the control section hardware circuit controls reading of top guide data.
5. for padding data produces principle, it is made of a simple tri-state gate circuit among the figure, and the input of triple gate is connected into a fixing pattern (as complete 0), under the control of R and RD this fixed data is read.
6. show the principle that dateout is handled among the figure.It is by (P/S) parallel-to-serial converter, pseudorandom scrambler generator, and the synchronous code generator, diverter switch and output driving circuit constitute.Between the synchronous code period of output, switch is controlled tangential 1 by the hardware logic electric circuit of control section, and the synchronous code in the synchronous code generator drives output by the CP internal clocking.Between VCDU data period of output, switch controls tangential 2 by the hardware logic electric circuit of control section, the data of reading by data buffer through and the string conversion after, carry out XOR after driver output with the pseudo noise code of scrambler generator output, CP is the internal clocking of multiplexer, the output speed of its determination data.
7. shown the operation principle of control section among the figure, control section is made of two parts circuit as can be seen from Figure.A part is to be the microsystem formation of core with 80C186 CPU, the total reset signal MR of this part generation, and A mouth, B mouth gating signal STRA, STRB, reading of BufferA～C allows signal RA～RC and padding data to allow signal RE.Half-full signal HFA～HFC that computer part detects Buffer A～C should read to determine the data among which Buffer.Another part circuit in the control circuit is for driving the control impuls generator that is made of hardware with internal clocking.This partial circuit produces synchronous selection pass signal SYC, VCDU gating signal VCDU, synchronous code load signal SYC_SET, BufferA～C switching signal BUF_EXCHG, the parallel data load signal PRL_SET of parallel/serial transducer, buffer read signal R, top guide data reading signal RD, and synchronous necessary these control signals of CPU interrupt signal Int. switching that control data flows in high speed multiple connection process for hardware circuit and microcomputer software are partly controlled, requirement speed is fast, sequential accurately and logical relation is simple relatively and fixing produces with hardware circuit to make circuit working reliable and stable.
The annexation of this seven part is: 1., 2., 3., 4. the partial data buffer readout window and 5. in padding data outlet link together through inner 8 bit data bus, and the serial/parallel transducer in 6. enters the mouth and joins through this bus and dateout processing section.1.-5. only allowing a part dateout in the part at synchronization between the VCDU period of output, handling 6. output through dateout.The CPU of control section in 7. through internal microprocessor bus (16 bit data bus, 20 bit address buses and control bus) and top guide buffer 4., 3. the 1553B special interface circuit link to each other with Buffer C, finishes the transmission of C mouth input data and top guide data through this bus.8 tunnel control signals that the control impuls generator of control circuit in 7. produces link to each other with 1.-6. part respectively, control the each several part co-ordination, finish the multiple connection function.
Accompanying drawing 3 is made of 4 shift registers of incorporating into to go here and there out for synchronous code produces circuit.The parallel input of shift register be connected in advance required synchronous code pattern 1ACFFC1D between the VCDU period of output by signal SYC_SET control loaded, between synchronous period of output, drive 32 bit synchronization sign indicating numbers shifted out by internal clocking.
Accompanying drawing 4 is made of 8 bit shift register for pseudo noise code produces circuit, exports 8 rank pseudorandom M sequences by signal VCDU control according to the CCSDS standard code between the VCDU period of output.
Accompanying drawing 5 produces circuit for control impuls, it is stored among the PROM by the waveform that the PROM of one 12 digit counter and a slice 4K*8 constitutes required control arteries and veins in advance, 12 bit synchronization counters will produce 12 bit address during work, under it drives, 8 position datawires of PROM will be exported the wave mode of required control impuls (SYC, VCDU, SYC SET, BUF_EXCHG, PRL_SET, R, RD, INT) continuously.
Accompanying drawing 6 is a control strategy schematic diagram of the present invention.A among the figure, B, C, 3 buckets are represented A, B, C, three input data buffers respectively, and the D bucket is represented VCDU top guide data buffer, and the E pipe is represented padding data.A, B, three buckets of C a half-full signal HFA～HFC all arranged.Three water pipes of these three bucket tops are represented A, B, the data flow of three mouth inputs of C.Output speed is constant and adds top guide data sum greater than input traffic when supposing KA～KE valve open, has realized being in the example 8.448Mbps as the present invention.
The multiplexing process is the recreation as doing so especially, A, B, three water pipes of C add water with its inherent speed in three buckets, the rule of recreation is to control five valves of KA～KE rightly, allow the D bucket emit certain mark current (top guide that is equivalent to virtual channel data unit unit) earlier at every turn, open KA then, KB or KC emit 1/4 barrel water continuously from corresponding bucket, repeat said process again.Any one bucket can not overflow in the requirement operating process, does not also allow to export current and interrupts.Water allows to open KE more after a little while and puts filling water in three barrels of A, B, C, also must put 1/4 barrel at every turn.In order to accomplish that its basic controlling strategy of this point is: check the half-full sign of A bucket when a certain bucket is discharging water, if the half-full sign that then is ready to A in D of A, put the sign of A next time earlier, opens KA again, and the A bucket is bled off 1/4.If the A bucket does not reach the half-full half-full signal of then checking B as yet, and the like.If A, B, C are all not half-full, then are ready to the sign of E in D, open KE next time and put 1/4 barrel of filling water.If known A water inlet tube speed is managed greater than B, the B pipe is managed greater than C, and the water inlet speed that A, B, C three pipes add sign bucket is less than total then Theoretical Calculation and experimental results show that and adopt above tactful A, B, C neither can overflow for three barrels that the output current can not interrupt yet of speed that discharges water.
Accompanying drawing 7,8,9 is software workflow figure of the present invention.Software of the present invention is write as with the 80C186 assembler language, and program is divided into main ordering and two interrupt service routines.Main program (accompanying drawing 7) is finished system initialization, and self check and mode of operation inspection are carried out in circulation.First interrupt routine (accompanying drawing 8) is the zero hour in the VCDU dateout by control impuls Int signal triggering.CPU checks the half-full signal of three data buffers in the service routine, should read which buffer data or add padding data next time according to control logic above-mentioned decision, and in Buffer D, put into the top guide and the bit stream stipulations data cell top guide data of corresponding virtual channel data unit unit.Second interrupt service routine (accompanying drawing 9) triggered by the 1553B interface chip, and (complete packet (498 bytes) is sent to Buffer C will to be stored in of 1553B interface chip in the disconnected hereinto program of CPU.
Claims (9)
1, a kind of high-speed multiplexer, it is characterized in that, constitute by A, B, C three input data buffers, top guide data buffer, padding data generation circuit, dateout treatment circuit, multiple connection control circuit seven parts, wherein, A, B, C three input data buffers, top guide data buffer link to each other through inner 8 bit data bus with the data outlet that padding data produces circuit, and be connected to the data output processing circuit through this 8 bit data bus, the multiple connection control circuit links to each other with other six partial circuit respectively, produces control signal control multiple connection process.
2, a kind of implementation method of high-speed multiplexer, it is characterized in that, control by hardware logic and microcomputer is passed through the standard of the middle low rate data streams of 1553B bus interface input according to international space data system Advisory Board (CCSDS) with two tunnel serial high speed and a tunnel, the notion asynchronous multiplexing of utilization packet telemetry and pseudo channel becomes serial datum stream, its output data rate can reach 8.448Mbps, every road serial input data flank speed can reach 7.2Mbps, 1553 mouthfuls of input rates can reach 200Kbps, under the condition that is no more than the highest permission speed, the variation of input data rate there is adaptivity.
3, high-speed multiplexer implementation method according to claim 2, it is characterized in that, the serial data input interface is to adopt external clock to drive, and automatically data is deposited in cache way in first in first out (FIFO) memory through the pulse that serial/parallel conversion is obtained behind 8 frequency divisions by external clock.
4, high-speed multiplexer implementation method according to claim 2, it is characterized in that, multiplexer is established a MIL-STD-1553B bus data interface, receive the data of importing through the 1553B bus by the special purpose interface chip, and the data of buffer memory input in interface chip, when the data of input constitute a packet just, by CPU control whole packet is moved on in the buffer that is made of the FIFO memory again.
5, high-speed multiplexer according to claim 1, it is characterized in that the data that its output processing circuit is finished synchronous code generation, pseudo noise code generation, pseudo noise code and virtual channel data unit unit (VCDU) by hardware logic electric circuit fully are XOR and the switching of yardage stream and VCDU data synchronously by turn.
6, high-speed multiplexer according to claim 5, it is characterized in that, the generation of its pseudo noise code is to adopt one 8 shift register to constitute through suitable feedback circuit, the initialization of its state is to utilize to switch its serial input terminal realization, between the synchronous code period of output, the serial input terminal of shift register is put high level, shift register is all put " 1 " through clock pulse, thereby realized initialization.
7, high-speed multiplexer implementation method according to claim 2, it is characterized in that, the control of its multiple connection process is the control impuls and the mode that combines with the microcomputer software program that adopts hardware to produce, to cooperate be to produce pulse and cause that CPU interrupts by being carved in due course by hardware to strict sequential between hardware pulse and the software control, thereby the startup interrupt service routine is realized.
8, high-speed multiplexer according to claim 1, it is characterized in that, eight kinds of sequential multiple connection control circuits require complicated very accurately control signal, be to utilize PROM in advance its wave mode to be stored, drive coincidence counter with internal clocking then, thereby the address that produces PROM is with the output and realizing continuously automatically of the signal of the control wave mode of being deposited.
9, high-speed multiplexer according to claim 1, it is characterized in that, the capacity of data memory input is selected 4 times of VCDU length for use, its control strategy is to utilize CPU by checking the half-full signal of each buffer, thereby decision should discharge the data of which buffer next time, and the top guide data of making this channel deposit the top guide data buffer in and realize, each data of reading from buffer are not more than 1/4 of capacity register, cause that the dateout interruption can not cause overflowing of buffer yet thereby guaranteed neither buffer to be read sky.
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| CN109412939B (en) * | 2018-12-11 | 2021-05-25 | 中冶京诚工程技术有限公司 | Communication gateway for recording industrial network communication period process data and working method |
| CN111865396B (en) * | 2020-06-18 | 2022-08-12 | 上海卫星工程研究所 | Satellite load data receiving monitoring and autonomous resetting device and method |
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| JPH07177120A (en) * | 1993-12-21 | 1995-07-14 | Oki Electric Ind Co Ltd | Signal multiplexer |
| US5499238A (en) * | 1993-11-06 | 1996-03-12 | Electronics And Telecommunications Research Institute | Asynchronous transfer mode (ATM) multiplexing process device and method of the broadband integrated service digital network subscriber access apparatus |
| JPH08102725A (en) * | 1994-10-03 | 1996-04-16 | Natl Space Dev Agency Japan<Nasda> | Data multiplexing device |
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| US5499238A (en) * | 1993-11-06 | 1996-03-12 | Electronics And Telecommunications Research Institute | Asynchronous transfer mode (ATM) multiplexing process device and method of the broadband integrated service digital network subscriber access apparatus |
| JPH07177120A (en) * | 1993-12-21 | 1995-07-14 | Oki Electric Ind Co Ltd | Signal multiplexer |
| JPH08102725A (en) * | 1994-10-03 | 1996-04-16 | Natl Space Dev Agency Japan<Nasda> | Data multiplexing device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603146A (en) * | 2016-12-30 | 2017-04-26 | 中国电子科技集团公司第五十四研究所 | Synchronous control method for satellite virtual channel data packet transmission delay |
| CN106603146B (en) * | 2016-12-30 | 2019-03-15 | 中国电子科技集团公司第五十四研究所 | A kind of synchronisation control means for the delay of satellite virtual channel data divided stator frame |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1176549A (en) | 1998-03-18 |
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