JPH07177115A - Multiplexer and method for detecting fault in the multiplexer - Google Patents

Abstract

PURPOSE:To surety detect a fault and to improve the reliability by multiplexing plural signals to which prescribed identification information as a fault detection pattern is respectively inserted and collating the extracted pattern with the inserted pattern. CONSTITUTION:Fault detection pattern insertion circuits 12-1-12-N insert prescribed identification information as a fault detection pattern to each signal from transmission lines 20-1-20-N so as to be located at a prescribed area after multiplexing prior to multiplexing plural signals. A multiplex timing generating circuit 3 generates multiplex logic number information of information logically indicating a multiplexed position and output it to bus multiplexer circuits 11-1-11-N and fault detection pattern insertion circuits 12-1-12-N of each 1.5M interface section and to a fault detection pattern collation circuit 2. Then the fault detection pattern collation circuit 2 extracts each fault detection pattern inserted after multiplexing of the signals by the bus multiplexer circuits 11-1-11-N and collates the extracted pattern with the inserted pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a device failure due to a hardware failure in a communication device for processing multiplexed signals.

[0002]

2. Description of the Related Art In a communication device for processing a multiplexed signal, a method for detecting a hardware failure in an online state is to use a surplus area (FTS: Filling T) in the multiplexed signal.
A method is known in which a specific pattern (hereinafter, referred to as a failure detection pattern) for the purpose of detecting a failure is inserted in an ime slot and the expected value matching of the failure detection pattern is performed in each part of the device.

This conventional technique will be described with reference to FIG.
FIG. 10 shows a multiplexing device to which the prior art device failure detection method is applied. The multiplexer includes a serial-parallel conversion circuit 101 that inputs a plurality of serial signals and converts the serial signals into 8-bit parallel signals, and a multiplex processing circuit 102 that multiplexes the parallel signals. Further, the fault detection pattern insertion circuit 100 is provided in the preceding stage of the serial-parallel conversion circuit 101 of the multiplexer, and the fault detection pattern matching circuit 103 is provided in the latter stage via the multiplex processing circuit 102. Here, the failure detection pattern insertion circuit 100 and the failure detection pattern matching circuit 103 are intended to detect a failure due to a hardware failure of the serial-parallel conversion circuit 101 and the multiple processing circuit 102.

Before explaining the operation, the structure of the fault detection pattern in the prior art will be described. FIG. 11 shows
6 is a diagram showing a configuration example of a fault detection pattern used in the conventional technique. The fault detection pattern shown in FIG. 11 is for detecting the operation abnormality of the serial-parallel conversion circuit 101.
The pattern is composed of an 8 × 8 square matrix, and is configured so that the same pattern does not occur between rows and columns. In the example shown in FIG. 11, the inside of an 8 × 8 square matrix is composed of a unit matrix pattern and its inverted pattern. The reason why the unit matrix pattern and its inversion pattern are used in combination as the fault detection pattern is to detect the gate stuck-at fault of the logic circuit to be monitored for the fault. A gate degeneracy fault is a signal whose logic value is "
This is a fault fixed at 0 "or" 1 ". That is, the gate stuck-at fault can take both logical values 0 and 1, so that the monitored gate is controlled to have both polarities of 0 and 1 by the fault detection pattern. It needs to be activated by sex information.

Next, the operation of detecting a device failure of the multiplexer shown in FIG. 10 will be described. The fault detection pattern insertion circuit 100 generates the fault detection pattern composed of the square matrix shown in FIG. 11 and inserts it into the FTS portion in the multiplexed signal. The serial / parallel conversion circuit 101 located at the subsequent stage performs serial / parallel conversion of the multiplex signal including the failure detection pattern.
The serial-parallel conversion operation is nothing but the process of transposing the multiplexed signal on the time axis and the space axis. Therefore, if the serial-parallel conversion circuit 101 is functioning normally, the unit matrix of the fault detection pattern even after the serial-parallel conversion. Is saved. The same applies to the inversion pattern of the unit matrix. Furthermore, the serial-parallel conversion circuit
The output of 101 is input to the failure detection pattern matching circuit 103 via the multiplex processing circuit 102, and the expected value matching of the failure detection pattern is performed. The failure detection pattern matching circuit 103 detects a failure of the serial-parallel conversion circuit 101 and the multiplex processing circuit 102 based on the mismatch of the matching results of the failure detection patterns.

As described above, in the prior art, the fault detection pattern is configured individually corresponding to the physical signal multiplexing / demultiplexing processing.

[0007]

In the above-mentioned prior art, the fault detection pattern is constructed individually corresponding to the multiplexing / demultiplexing processing of the physical signal, but there are the following problems.

First, as the first problem, when the multiplexing rule is complicated and when the degree of multiplexing is high, the failure detection pattern becomes complicated, and the failure detection pattern of the prior art cannot actually cope with it.

As a second problem, the prior art does not consider the case where signals of a plurality of types of multiplexing units are mixed or accommodated, and the fault detection pattern of the prior art cannot deal with the problem. For example, there are signals of 1.544 Mb / s, 44.736 Mb / s, etc. as a plurality of types of multiplexing units, and a configuration in which these signals are mixed and multiplexed has not been considered in the related art. The conventional detection pattern cannot be used.

In order to solve the above problems, it is an object of the present invention to provide a fault detection method and a highly reliable multiplexing device that can reliably perform fault detection.

Another object of the present invention is to provide a multiplexer capable of verifying the signal multiplexing rule even when the multiplexing becomes complicated.

Still another object is to provide a multiplexer capable of detecting a fault even when handling various multiplexing units.

[0013]

In order to solve the above-mentioned problems, the present invention provides a multiplexing unit for multiplexing a plurality of signals and a plurality of signals multiplexed by the multiplexing unit. An inserting section for inserting a failure detection pattern for detecting a failure in a signal before multiplexing so as to be located in a predetermined area after multiplexing, and an inserting section from the area after multiplexing by the multiplexing section Each of the fault detection patterns inserted by is extracted, and has a collating unit for collating the extracted fault detection pattern and the inserted fault detection pattern, the insertion unit, As the pattern, predetermined identification information is inserted for each of the plurality of signals.

Further, the multiplexing section performs multiplexing according to a predetermined multiplexing rule, and the inserting section uses an identification number as the identification information for each multiplexing unit of the multiplexing rule in the multiplexing section. After the insertion, the collation unit can perform collation for each of the multiplexing units and detect the failure.

It further comprises a control unit for outputting identification information for each multiplexing unit to the inserting unit and the collating unit according to a predetermined multiplexing rule.

The inserting section may further insert an inverted signal of the identification information as the failure detection pattern.

Further, the collation unit is configured to, as a result of the collation,
A notification unit may be provided for notifying that a failure has occurred when it does not match the failure detection pattern.

The collation unit includes a detection unit for detecting the multiplexing unit, and the collation can be performed according to the multiplexing unit detected by the detection unit. Alternatively, the multiplexing unit outputs information indicating the multiplexing unit, and the collating unit includes a detection unit that detects the multiplexing unit output from the multiplexing unit, and the detection unit detects the multiplexing unit. The collation is performed according to the conversion unit.

As another configuration, a multiplexing bus for performing multiplexing, a plurality of interface circuits connected to low-speed signals, and a plurality of interface circuits provided corresponding to each of the plurality of interface circuits are provided. An insertion circuit for inserting a failure detection pattern for failure detection into the low-speed signal so as to be located in a predetermined area after conversion, and the insertion circuit provided corresponding to each of the insertion circuits. Of the low-speed signal is output to the multiplex bus in accordance with a predetermined timing, and each fault detection pattern connected to the multiplex bus and inserted by the insertion circuit from the area is extracted. , The extracted fault detection pattern, and a collating unit for collating the inserted fault detection pattern, the insertion circuit, as the fault detection pattern It can be inserted identification information predetermined respectively for the low-speed signal.

Further, as another configuration, a demultiplexing unit that demultiplexes a plurality of multiplexed signals, and a plurality of signals that are demultiplexed by the demultiplexing unit are determined in advance. An insertion section for inserting a failure detection pattern for failure detection into an area, and after separation by the separation section, each failure detection pattern inserted by the insertion section from the area is extracted, and the extracted failure detection Pattern, and a collating unit that collates the inserted fault detection pattern. The inserting unit inserts predetermined identification information for each of the plurality of signals as the fault detection pattern.

Further, as a method of detecting a failure in a multiplexer for multiplexing a plurality of signals, for each of the plurality of signals to be multiplexed, before multiplexing so as to be located in a predetermined area after multiplexing. For each signal, the identification information is inserted for each multiplexing unit in a predetermined multiplexing rule, after the multiplexing, the inserted identification information is extracted, the extracted identification information, and the inserted identification information. May be compared with each other, and if the result of the comparison does not match, it may be detected as a failure.

Further, the inverted signal of the identification information is further inserted, and the inserted inverted signal is further extracted after the multiplexing, and the extracted inverted signal is compared with the inserted inverted signal. If the results of the comparison do not match, it can be detected as a failure.

[0023]

In a device for multiplexing a plurality of low speed signals into a high speed signal, a failure caused by a hardware failure can be classified as shown below.

(1) Abnormality of multiplexing rule This is a failure to execute multiplexing in a state different from a predetermined multiplexing rule due to a failure of a circuit that controls multiplexing of low-speed signals. In the latter stage, since the signal arrangement is different from the predetermined multiplexing rule, the signal is not transmitted to the correct opponent.

(2) Signal crossing fault This is a fault in which a signal is not normally transmitted to the subsequent stage due to the crossing of the signal line of the gate through which the signal passes. This fault also includes an event in which multiple signals are output at the same timing due to an abnormality in the multiplexing control in the bus multiplexing circuit.

(3) Fault of fixed logic value of signal This is a fault in which the logic value of the signal is fixed to "0" or "1" in the subsequent stage of the fault gate due to the stuck logic fault of the gate through which the signal passes.

The operation of the means for solving the problems will be described with reference to the above failure modes.

The inserting section is for detecting a failure for detecting a failure with respect to a signal before multiplexing so that it is located in a predetermined area after multiplexing for each of a plurality of signals multiplexed by the multiplexing section. Insert a pattern. The matching unit extracts each failure detection pattern inserted by the insertion unit from the area after multiplexing by the multiplexing unit, and matches the extracted failure detection pattern with the inserted failure detection pattern. I do.

The fault of the multiplexing rule (1) is detected by the collating unit when the fault detection pattern in the multiplexed signal and its expected value do not match. That is, in the fault detection pattern to which the present invention is applied, the pattern is different for each signal of the multiplexing unit, that is, the predetermined identification information of each multiplexed signal. The identification information is an identification number for each multiplexing unit of the multiplexing rule in the multiplexing unit. Therefore, it is possible to verify the signal multiplexing rule by collating the expected value of the failure detection pattern generated according to the temporal positional relationship after multiplexing with the failure detection pattern.

Further, the signal crosstalk trouble (2) is detected as a mismatch of expected values in the collating unit, as in the case (1). In general, the phenomenon in signal line mixing is not uniform, but in most cases, the logical function of the output signal is a wired OR (logical sum) or a wired AND (logical product). Therefore, when passing through the wired logic due to the mixing of the signal lines, the logical product or the logical sum of the two signals is output to the subsequent stage, and like the fault detection pattern to which the present invention is applied, a different pattern for each individual signal of the multiplexing unit. , The output value of the failure detection pattern portion changes, and it is detected that the expected values do not match.

As described above, in a communication device that handles a multiplexed signal composed of a single type of multiplexing unit, it is possible to detect a failure caused by various failure modes.

When the multiplexing unit is different, it is general that the vacant area in which the failure detection pattern can be mounted is different. In this case, by further providing detection means for detecting the type of the multiplexing unit, it is possible to specify a free area corresponding to the detected type and select and insert an optimum failure detection pattern. Therefore, even when various multiplexing units are handled in the same communication device, the device failure can be detected.

In the logic value fixed fault (3), the inversion signal of the identification information is further inserted as the fault detection pattern in the inserting section, so that the logic values are complementary to each other. It can be detected by the failure detection pattern.

Further, the notification means can notify that a failure has occurred when the result of the collation does not match the failure detection pattern.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the structure of a multiplexer according to the first embodiment of the present invention. First shown in FIG.
In the circuit of the embodiment, N 1.5M interface units 10-1 to 10-N respectively accommodating 1.5M transmission lines 20-1 to 20-N are provided.
A multiplex bus 1 for multiplexing the output signals from them, a fault detection pattern matching circuit 2 connected to the multiplex bus 1, and a multiplex timing generation circuit 3 for generating multiplex timings. Further, the 1.5M interface unit 10-1 includes a 1.5M interface circuit 13-1 for terminating the 1.5M transmission line, a failure detection pattern insertion circuit 12-1 for generating and inserting a failure detection pattern, and , A bus multiplexing circuit 11-1 for multiplexing signals on multiple buses.
The other 1.5M interface units 10-2 to 10-N have the same configuration. The multiplex timing generation circuit 3 generates multiplex logical number information of information logically indicating the multiplex position,
It outputs to each of the 1.5M interface units 10-1 to 10-N and the failure detection pattern insertion circuit 12-1. The 1.5M interface units 10-1 to 10-N are instructed by the multiplex logic number information from the multiplex timing generation circuit 3, and the bus multiplex circuit 11-1.
To 11-N and the fault detection pattern insertion circuits 12-1 to 12-N. In this embodiment, in order to perform bus multiplexing,
In each of the bus multiplex circuits 11-1 to 11-N, output is performed at a predetermined multiplex timing according to the multiplex logical number information. Also, the fault detection pattern insertion circuits 12-1 to 12
In -N, a failure detection pattern of predetermined identification information is inserted into a signal from each transmission line before being multiplexed. This failure detection pattern will be described later. Also,
Instead of instructing the multiplex logical number information from the multiplex timing generating circuit 3, a control section for performing multiplex control is provided,
The control unit may instruct the multiple logical number information.

Next, the operations of multiplexing and fault detection in the first embodiment will be described with reference to FIGS. In explaining the operation, the frame structure of the multiplexed signal applied to the multiplexer of the first embodiment will be described.

FIG. 2 shows a multiplexing system applied to the multiplexing device of the first embodiment. In this example, S proposed by Bell core of the United States
An example is the case of using ONET (Synchronous Optical NETwork). In the first embodiment, in the 1.5M interface circuits 13-1 to 13-N and the bus multiplexing circuits 11-1 to 11-N, the low speed 1 received from the 1.5M transmission lines 20-1 to 20-N is used. Virtual container 11 (VC) with 5M signal (1.544Mb / s)
-11: Virtual Container 11) and mapped to the tributary unit 11 (TU-11: Tributary Unit 11) and the tributary unit group 2 (TUG-2: Tributary Grou
via virtual container 3 (VC-3: Virtual C
ontainer 3). In this case, TU-11
4 signals make up a TUG-2 signal, and
A VC-3 signal is composed of seven G-2 signals. That is, 28 TU-11 signals are multiplexed in the VC-3 signal.

FIG. 3 shows a frame structure in the multiplex bus 1 of the first embodiment. The frame on the multiplex bus 1 shown in FIG. 3 is composed of a total of 810 bytes consisting of 90 columns × 9 rows per frame of 125 μs cycle. This frame structure is STM-0 (Syn) defined by the Telegraph and Telephone Technical Committee (TTC).
It is the same as chronous Transport Module 0).

The frame shown in FIG. 3 contains one VC-3 signal, and 28 TU-11 signals are contained therein. The TU-11 signal is composed of 27 bytes per frame, and includes a TU pointer 1 byte and a 26-byte VC-11.
Signals and are included. The multiple timing generation circuit 3 generates timing based on this frame. Further, the TU-11 signal has a multi-frame structure in which 4 frames are set as one unit, and the area of the TU pointer is
Information that is different for each frame is loaded with 4 frames as a cycle, and is called V1 to V4 bytes corresponding to the frame number in the multiframe. Pointer information is mounted in the TU pointer areas of the first frame and the second frame, that is, the V1 byte and the V2 byte, of the four frames forming one multi-frame. Also,
The TU pointer area of the third frame, that is, the V3 byte is used for frequency matching (justification).

On the other hand, since the V4 byte of the fourth frame has no fixed purpose, this V4 byte is used in this embodiment.
The failure detection patterns 30-1 and 30-2 are installed in the byte area. In this case, each of the failure detection pattern insertion circuits 12-1 to 12-N in FIG. 1 inserts the failure detection pattern into the V4 byte area.

Next, the structure of the failure detection pattern in the first embodiment will be described with reference to FIG. The fault detection pattern shown in FIG. 4 is composed of a positive polarity pattern and a negative polarity pattern that are in an inverse relationship to each other. Explaining in association with FIG. 3, the positive polarity pattern (a) shown in FIG. 4 corresponds to the failure detection pattern 30-1, and the negative polarity pattern (b) shown in FIG. 4 corresponds to the failure detection pattern 30-2.

Next, the detailed structure of the fault detection pattern shown in FIG. 4 will be described. In FIG. 4, the failure detection pattern is composed of a combination of three basic patterns as described below. First, when the LSB is the 0th bit, the TUG is changed from the 5th bit to the 3rd bit.
An identification pattern is mounted. What is a TUG identification pattern?
It is a pattern of the identification number of the TUG-2 to which the multiplexed signal belongs, and TUG- for the VC-3 signal.
There are 7 possible values corresponding to a multiplexing number of 2. Next, the TU identification pattern is mounted in the 2nd bit to the 0th bit. The TU identification pattern is a pattern of the identification number of the TU-11 signal to which the multiplexed signal belongs, and can take four values corresponding to the number of multiplexed TU-11 signals for TUG-2. . Finally, a fixed pattern is mounted on the 7th bit to the 6th bit regardless of the belonging of the multiplexed signal. These three types of basic patterns have an inversion relationship between the positive polarity pattern and the negative polarity pattern. Thus, the failure detection pattern is TU
A pattern different for each −11 signal, that is, identification information indicating a multiplexing rule (multiplexing order) is inserted for each multiplexing unit.

FIG. 5 shows a concrete configuration example of the TUG identification pattern and the TU identification pattern. Figure 5
2 uses a binary coded multiplex logical number information indicating the multiplexing order of TUG-2 for the VC-3 signal. The multiplex logical number information is information that is specified by the multiplex timing generation circuit 3 when multiplexing and logically indicates the multiplex position of the TU-11 signal accommodated in the interface. Also, as the TU identification pattern, multiplex logical number information indicating the multiplexing order of the TU-11 signal for the TUG-2 is binary coded and used. By combining these TUG identification patterns and TU identification patterns, a unique failure detection pattern is assigned to each of the 28 TU-11 signals included in the VC-3 signal. Therefore, by monitoring the failure detection patterns shown in FIGS. 4 and 5, it is possible to identify the multiple logical number information of the TU-11 signal with respect to the VC-3 signal. That is, the failure detection pattern matching circuit 2 compares the failure detection pattern for matching based on the multiplex logical number information instructed from the multiplex timing generation circuit 3 with the failure detection pattern inserted in the multiplexed signal. By doing so, when they do not match, it can be detected as a failure.

Next, the bus multiplexing operation in the multiplexing bus 1 of the multiplexer of the first embodiment will be described with reference to FIG. FIG. 6 shows a case in which 28 circuits are mounted in the 1.5M interface section in FIG. 1, that is, N = 28. The 1.5M interface unit 10-1 sends data to the multiplex bus 1 in bursts at each multiplexing cycle at a position corresponding to the first TU-11 signal belonging to the first TUG-2. To do. The operation explanatory view shown in FIG. 6 shows a signal waveform in the vicinity of the V4 byte on which the failure detection pattern is mounted, and the failure detection pattern 31-1 is transmitted to the multiplex bus 1. Also, similarly,
From the 1.5M interface unit 10-2, the second TUG-
The fault detection pattern 31-2 is transmitted to the multiplex bus 1 at the position corresponding to the first TU-11 signal belonging to the second bus. Similarly, up to the interface unit 10-28, the data including the failure detection pattern is transmitted at the multiplexing position corresponding to each interface. That is, each of the 1.5M interface units 10-1 to 10-28 has a multi-bus frame structure as shown in FIG.
, The multiplex timing is controlled and the TU-
11 signals are transmitted, and fault detection patterns 30-1 and 30-2 are inserted in the V4 byte area.

These 1.5M interface units 10-1 to 10
-N is the fault detection pattern sent by each fault detection pattern insertion circuit 12-1 ~
Generated at 12-N and inserted at V4 byte position. This failure detection pattern is generated based on the above-mentioned multiplex logical number information provided from the multiplex timing generation circuit 3. This multiplexed logical number information is used in the bus multiplexing circuit 11-1.
Also applied to ~ 11-N and used to control data output timing to multiplex bus 1. As the method of giving the multiplex logical number information to the fault detection pattern insertion circuits 12-1 to 12-N, a method of applying it as a level signal to the signal connector terminals of the 1.5M interface units 10-1 to 10-N, and There is a method of writing as logic information in a control register inside the 1.5M interface units 10-1 to 10-N. In the case of the method of writing as logic information in the control register, the control register is also provided in the failure detection pattern matching circuit 2, and the 1.5M interface unit 10 is preliminarily set at the initial setting stage.
Multiple logical number information may be set in the internal control registers of -1 to 10-N and the control register of the fault detection pattern matching circuit 2, respectively. 1.5M interface section 10-1
Multiple logical number information indicating each multiplexing position is set in the internal control registers of ~ 10-N, and all the multiple logical numbers as shown in FIG. 5 are set in the control register of the fault detection pattern matching circuit 2. Information is set, and a failure detection pattern corresponding to the information is set.

The data portion after multiplexing in FIG. 6 shows a signal waveform after bus multiplexing at the termination point of the multiplex bus 1 in FIG. 1, that is, at the input portion of the fault detection pattern matching circuit 2. As the failure detection pattern,
The TUG identification pattern described in FIGS. 4 and 5,
A failure detection pattern consisting of three basic patterns of TU-11 identification pattern and fixed pattern is used. Fault detection pattern 30-1 after multiplexing shown in FIG.
The numeral shown in 30-2 is the failure detection pattern based on FIGS. 4 and 5 expressed in hexadecimal.

The multiplexed data shown in FIG. 6 shows the data when the bus multiplexing is normally performed. In the fourth frame, the positive fault detection pattern is multiplexed, and in the eighth frame. Then, the negative polarity fault detection patterns are multiplexed and input to the fault detection pattern matching circuit 2. The failure detection pattern matching circuit 2 generates an expected value of the matching failure detection pattern at the V4 byte position according to the multiplexing position information received from the multiplex timing generation circuit 3 and compares it with the failure detection pattern received from the multiplex bus 1. Compare and collate.

The result of collation can be held in the fault detection register as shown in FIG. The fault detection register can be provided in the fault detection pattern matching circuit 2,
As shown in FIG. 12, "1" is set when a mismatch is detected. When a mismatch is detected, the fact that a failure has occurred is notified. In this case, the multiplexing device can be provided with a notification means. As a notification means, a display means such as an LED may be provided in the package of each circuit and the LED may be turned on when a failure occurs. Or
Equipped with a liquid crystal display and predetermined error messages (messages indicating failure status and location)
May be displayed. Also, as a notification means,
A sound generator that outputs a warning sound or a message may be provided. The failure notification may be a predetermined notification corresponding to the type of failure. Alternatively, when notifying a failure to another external device, a failure notification packet may be generated and output. Furthermore, when a maintenance terminal or the like is provided, the maintenance terminal can be notified of the occurrence of a failure. The above fault detection register is
Clear the contents held after notification, or
Receiving means for receiving the reset may be provided, and when the user resets the receiving means, the contents held in the register can be cleared.

Further, in FIG. 12, 4 frames are 1
The failure detection for one multi-frame as a unit is held, but the failure detection for a plurality of multi-frames is held and the failure is notified when a predetermined number of failures continue. May be.

As a result of the collation, for example, when a fixed failure of data occurs due to a logic value degeneracy failure of a gate through which a signal passes, at least one of the positive and negative failure detection patterns has an expected value and a received value. And a logic value stuck-at fault of the gate is detected. As shown in FIG. 12, in the interface unit 10-2, when the positive TUG number and the TU number do not match and an error is detected, and when the negative polarity is not detected, the logic value is fixed in the interface unit 10-2. It can be presumed to be a disorder.

Further, the bus multiplexing circuits 10-1 to 10-N shown in FIG.
If a fault occurs, a multiplexing rule abnormality fault or a signal crosstalk fault in the multiplex bus 1 occurs. Of these, in the case of a fault in the multiplexing rule, T received from the multiplex bus 1
The TUG identification pattern and the TU-11 identification pattern included in the failure detection pattern in the U-11 signal and the TUG identification pattern and TU-11 for collation generated based on the multiplexed position information from the multiplex timing generation circuit 3. The pattern does not match. Therefore, it can be detected that a predetermined multiplexed signal is not arranged at a predetermined multiplexing position, and an abnormality in the multiplexing rule can be detected. Further, in the case of a signal line cross-link failure which is a phenomenon in which TU-11 signals from a plurality of interfaces collide on the multiplex bus 1, a wired OR (logical sum) or momentary OR is performed at the portion where the signals collide. This is equivalent to the formation of a wired AND (logical product) logic, and the value of the failure detection pattern changes. Therefore, the failure detection pattern matching circuit 2 detects a mismatch between the failure detection pattern and the expected value, and the signal line crossing failure is also detected. For example, as shown in FIG. 12, when a failure occurs in the interface unit 10-1, it can be notified that the interface unit 10-1 has a failure. Furthermore, if a spare interface unit is provided, the faulty interface unit may be switched to the spare interface unit.

As described above, by using the multiplexer for bus-multiplexing the TU-11 signal to the VC-3 signal as an example, different failure detection patterns are used for individual multiplexed signals in the same multiplexing unit. With this, it is possible to detect a device failure due to a failure in various modes. further,
The interface part of the multiplexed signal in which the failure has occurred can be specified.

Next, a second embodiment of the present invention will be described, targeting a multiplexer which handles a plurality of multiplexing units.

FIG. 7 and FIG. 8 show an example of the configuration of the multiplexing device showing the second embodiment of the present invention. The multiplexer according to the second embodiment has 1.5M transmission lines 20-1 to 20-20.
-N and 45M transmission lines 50 can be accommodated.

FIG. 7 shows a configuration in which the 1.5M transmission lines 20-1 to 20-N are accommodated. In this case,
The 1.5M interface units 10-1 to 10-N are mounted on the multiplexer. The multiplexer shown in FIG. 7 has a configuration in which a monitoring / multiplexing unit monitoring circuit 4 for monitoring a multiplexing unit is added to the multiplexer of the first embodiment shown in FIG. The multiplexing unit monitoring circuit 4 receives information indicating the interface type from the interface units 10-1 to 10-N connected to the multiplexing bus 1 via the control lines 21-1 to 21-N, respectively, and The content is output to the fault detection pattern matching circuit 2. As the information indicating the interface type, predetermined identification information such as 1.5M interface and 45M interface is output. Alternatively, instead of sending out via the control line, information indicating the interface type may be added to the packet and sent out.

In the configuration example shown in FIG. 7, since the 1.5M interface is mounted as the interface type, the VC-conforms according to the same multiple rule as in the case of the first embodiment.
After being mapped to 11 signals, they are multiplexed into VC-3 signals via TU-11. In the case of accommodating the 1.5M interface shown in FIG. 7, the frame structure on the multiplex bus is shown in FIG. 3 as in the case of the first embodiment. The failure detection pattern for detecting a hardware failure is V
It is mounted in a 4-byte area. It is the same as the operation of the first embodiment that the device failure corresponding to various failure modes of hardware can be detected by using this failure detection pattern.

Next, FIG. 8 shows a structure in which the 45M transmission line 50 is accommodated. In this case, 45M transmission line 50 is accommodated.
The M interface 40 is mounted on the multiplexer. Figure 8
The multiplexer shown in FIG. 6 has exactly the same configuration as the multiplexer shown in FIG. 7 except for the type of the mounted interface.
In the configuration example shown in FIG. 8, the interface type is 45
The M interface is mounted, and the signal of the 45M transmission line is directly mapped to the VC-3 signal. This is
In the multiplexing system diagram shown in FIG. 2, the C-3 signal is converted to VC-
Equivalent to mapping to 3 signals. FIG. 9 shows a frame structure on the multiplex bus 1 when the 45M interface 40 is installed. The signal on the 45M transmission line is directly converted to VC-3.
When mapped to a signal, the TU pointer area does not exist, and data is mounted in all parts of the frame except the first column, the third column, the 33rd column, and the 52nd column. . Therefore, the failure detection pattern cannot be mounted at the same position as in FIG. 7 that accommodates the 1.5M interface. Instead, in the frame configuration shown in FIG. 9 corresponding to the interface implementation in FIG. 8, fault detection patterns 60-1 to 60-8 are added to the first to third columns corresponding to the section over head area. In the case of the configuration shown in FIG. 8, since there is only one interface that multiplexes data on the multiplex bus 1, it is not necessary to configure a fault detection pattern that distinguishes the multiplexing position, and a fault with a complementary fault detection pattern is not necessary. It can be detected. For example, all 1s are set in the failure detection pattern 60-1, and all 0s are set in the failure detection pattern 60-2. In the multiplexing unit monitoring circuit 4, the interface unit 10-1
According to the information indicating the interface type from ~ 10-N,
Fault detection pattern 60 for 45M interface
-1 to 60-8 is detected.

In the configuration shown in FIG. 7 for accommodating the 1.5M interface and the configuration shown in FIG. 8 for accommodating the 45M interface, the fault detection pattern is mounted according to the interface type, that is, the multiplexing unit type. By switching the position, it is possible to reliably detect a device failure due to a hardware failure in each implementation.

In the above embodiment, only the fault detection in the upstream direction in which a plurality of low speed signals are multiplexed into a high speed signal has been described, but the high speed signal is separated into a plurality of low speed signals in the downstream direction. In the case of, similarly, the failure detection pattern may be inserted. In this case, a high-speed side fault detection pattern insertion circuit for inserting a fault detection pattern in the high-speed signal before separation and a fault detection pattern collation circuit for collating the fault detection pattern in each interface section are provided. In the high-speed side fault detection pattern insertion circuit, the identification number in each multiplexing unit is inserted as a fault detection pattern in the high-speed signal, and after separation, in the fault detection pattern matching circuit of each interface unit, the fault detection pattern By comparing with the expected value, it is possible to detect the failure in the case of disagreement. As a result, it is possible to detect a failure in the downlink direction.

Further, even when a plurality of multiplex buses are provided and the multiplex buses are used to multiplex to a higher speed signal, the fault detection pattern may be similarly inserted. In this case, a failure detection pattern inserting circuit for inserting a failure detection pattern into a signal multiplexed by the multiplexing bus, and a high speed multiplexing circuit after the failure detection pattern matching circuit 2 in the multiplexing bus shown in FIG. It is possible to provide a high speed side failure detection pattern matching circuit for matching failure detection patterns. This makes it possible to detect a failure even when multiplexing is performed.

[0062]

According to the present invention, it is possible to reliably detect a hardware failure of a communication device that handles multiplexed signals, and to realize high reliability of the communication device.

Further, even when the multiplexing becomes complicated, the signal multiplexing rule can be verified.

Furthermore, even when handling various multiplexing units, it is possible to detect a fault.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiplexer according to a first embodiment.

FIG. 2 is an explanatory diagram showing a multiplexing system in the first and second embodiments.

FIG. 3 is an explanatory diagram showing a frame structure of a multiplex bus according to the first embodiment.

FIG. 4 is an explanatory diagram showing a configuration of a fault detection pattern in the first embodiment.

FIG. 5 is an explanatory diagram showing code allocation of individual parts of a multiplexed signal in a failure detection pattern.

FIG. 6 is an operation explanatory diagram of the multiplex bus according to the first embodiment.

FIG. 7 is a first configuration diagram showing a configuration example of a multiplexing device showing a second embodiment.

FIG. 8 is a second configuration diagram showing a configuration example of a multiplexing device showing a second embodiment.

FIG. 9 is an explanatory diagram showing a frame structure of a multiplex bus according to a second embodiment.

FIG. 10 is a configuration diagram of a multiplexing device to which a device failure detection method of the related art is applied.

FIG. 11 is a configuration diagram of a fault detection pattern in the related art.

FIG. 12 is an explanatory diagram of a fault detection register according to the first embodiment.

[Explanation of symbols]

1 ... Multiplexing bus, 2 ... Fault detection pattern matching circuit, 3 ...
Multiplex timing generating circuit, 4 ... Multiplexing unit monitoring circuit, 10
-1, ..., 10-N ... 1.5M interface, 11-1, ・
.., 11-N ... Bus multiplexing circuit, 12-1, ..., 12-N ... Fault detection pattern insertion circuit 1, 13-1, ..., 13-N ... 1.5M interface circuit, 20- 1, ..., 20-N ... 1.5M transmission line, 30-1,30-2 ... Fault detection pattern, 31-1, ..., 31-28
... fault detection pattern, 40 ... 45M interface circuit, 41 ... bus multiplexing circuit, 42 ... fault detection pattern insertion circuit 2, 43 ... 45M interface circuit, 50 ... 45
M transmission line, 60-1, ..., 60-8 ... Fault detection pattern, 10
0 ... Fault detection pattern insertion circuit, 101 ... Serial / parallel conversion circuit, 102 ... Multiple processing circuit, 103 ... Fault detection pattern matching circuit.

Claims (11)

[Claims] 1. A multiplexing unit for multiplexing a plurality of signals, and each of a plurality of signals multiplexed by the multiplexing unit,
An insertion unit for inserting a failure detection pattern for detecting a failure in a signal before multiplexing so as to be located in a predetermined area after multiplexing, and the insertion from the area after multiplexing by the multiplexing unit. Each fault detection pattern inserted by the unit, and has a collating unit that collates the extracted fault detection pattern and the inserted fault detection pattern, the insertion unit, the fault detection A multiplexing device, wherein predetermined identification information is inserted into each of the plurality of signals as a usage pattern. 2. The multiplexing unit according to claim 1, wherein the multiplexing unit performs multiplexing according to a predetermined multiplexing rule, and the inserting unit uses the multiplexing unit of the multiplexing rule in the multiplexing unit as the identification information. An identification number is inserted for each of the multiplex units, and the matching unit performs the matching for each of the multiplex units to detect the failure. 3. The multiplexing device according to claim 2, further comprising a control unit that outputs identification information for each multiplexing unit to the inserting unit and the collating unit according to a predetermined multiplexing rule. 4. The multiplexer according to claim 1, wherein the inserting section further inserts an inverted signal of the identification information as the fault detection pattern. 5. The multiplexing according to claim 1, wherein the collating unit includes notifying means for notifying that a fault has occurred when the collation result does not match the fault detection pattern. apparatus. 6. The multiplexing according to claim 2, wherein the matching unit includes a detection unit for detecting the multiplexing unit, and the matching is performed according to the multiplexing unit detected by the detection unit. apparatus. 7. The multiplexing unit according to claim 2, wherein the multiplexing unit outputs information indicating the multiplexing unit, and the collating unit includes a detection unit that detects the multiplexing unit output from the multiplexing unit. A multiplexing device, wherein the collation is performed according to a multiplexing unit detected by the detecting means. 8. A multiplexing bus for performing multiplexing, a plurality of interface circuits connected to low-speed signals, a plurality of interface circuits provided corresponding to each of the plurality of interface circuits, and predetermined after multiplexing. An insertion circuit for inserting a fault detection pattern for fault detection into the low-speed signal so as to be located in a region, and a low-speed signal from the insertion circuit provided in advance corresponding to each of the insertion circuits. Multiplexing means for outputting to the multiplex bus according to a predetermined timing, and each fault detection pattern connected to the multiplex bus and inserted by the insertion circuit from the area,
The extracted fault detection pattern and a collating unit that collates the inserted fault detection pattern are included, and the insertion circuit, as the fault detection pattern, identification information predetermined for each of the low-speed signals. A multiplexing device, characterized in that 9. A demultiplexing unit for demultiplexing a plurality of multiplexed signals, and for each of the plurality of signals demultiplexed by the demultiplexing unit, for detecting a failure in a predetermined region of the multiplexed signals. After inserting the fault detecting pattern, the fault detecting pattern is separated by the separating unit, each fault detecting pattern inserted by the inserting unit is extracted from the region, and the extracted fault detecting pattern is inserted. A separation device comprising: a collation unit that collates with a failure detection pattern, wherein the insertion unit inserts predetermined identification information for each of the plurality of signals as the failure detection pattern. 10. A method of detecting a failure in a multiplexer for multiplexing a plurality of signals, wherein each of the plurality of signals to be multiplexed is multiplexed so as to be located in a predetermined area after the multiplexing. For the previous signal, the identification information for each multiplexing unit in the predetermined multiplexing rule is inserted respectively, after the multiplexing, the inserted identification information is extracted, and the extracted identification information and the inserted identification Compare with the information,
A method of detecting a fault, which is characterized in that a fault is detected when the results of the comparison do not match. 11. The inversion signal of the identification information is further inserted, the inserted inversion signal is further extracted after the multiplexing, and the extracted inversion signal and the inserted inversion signal are added. And detecting the failure when the results of the comparison are inconsistent.