JPH07176694A - Fabrication of capacitor - Google Patents
Fabrication of capacitorInfo
- Publication number
- JPH07176694A JPH07176694A JP32064993A JP32064993A JPH07176694A JP H07176694 A JPH07176694 A JP H07176694A JP 32064993 A JP32064993 A JP 32064993A JP 32064993 A JP32064993 A JP 32064993A JP H07176694 A JPH07176694 A JP H07176694A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- entire surface
- electrode
- layer
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】化合物半導体集積回路の製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】化合物半導体集積回路中のキャパシタの
製造に関して、従来では、ＳｉＯｘやＳｉＮｘなどの絶
縁材料をスパッタ法や蒸着法で堆積させた薄膜をキャパ
シタ誘電体層として適用してきた。2. Description of the Related Art Conventionally, for manufacturing a capacitor in a compound semiconductor integrated circuit, a thin film formed by depositing an insulating material such as SiOx or SiNx by a sputtering method or a vapor deposition method has been applied as a capacitor dielectric layer.
【０００３】[0003]
【発明が解決しようとする課題】しかし、これら堆積に
よって形成した誘電体膜を利用するキャパシタ製造方法
は、誘電体膜のピン・ホールやエッジ部の欠陥によるキ
ャパシタ耐圧の劣化をまねきやすく、また、ウエハ内や
ロット間でのキャパシタの電気特性のばらつきを頻繁に
まねく、という問題点があった。However, the capacitor manufacturing method using the dielectric film formed by these depositions is apt to cause deterioration of the withstand voltage of the capacitor due to the defect of the pin hole or the edge portion of the dielectric film, and There has been a problem that variations in the electrical characteristics of the capacitors within a wafer or between lots frequently occur.
【０００４】[0004]
【課題を解決するための手段】本発明の方法では、キャ
パシタ誘電体膜を、陽極酸化液のよく確立された電気化
学方法であるウェット陽極酸化法によって形成する。SUMMARY OF THE INVENTION In the method of the present invention, a capacitor dielectric film is formed by the wet anodic oxidation method, which is a well established electrochemical method of anodizing solutions.
【０００５】また、キャパシタ上部電極をＡｕで、キャ
パシタ上部電極とキャパシタ間のコンタクト薄膜層をＡ
ｌ／Ｔｉ／Ｐｔ／Ａｕで形成する。The capacitor upper electrode is made of Au, and the contact thin film layer between the capacitor upper electrode and the capacitor is made of Au.
It is formed of 1 / Ti / Pt / Au.
【０００６】[0006]
【作用】本発明の方法では、キャパシタ誘電体膜は、陽
極酸化液のよく確立された電気化学的方法であるウェッ
ト陽極酸化法によって形成されるため、ピン・ホールや
エッジ部での欠陥のない緻密な構造をもち、より高い耐
圧を有するようになる。また、陽極酸化膜の膜厚は、酸
化の際の印加電圧により精密に制御されるため、ウエハ
内やロット間での電気特性のばらつきのきわめて少ない
キャパシタが形成される。In the method of the present invention, since the capacitor dielectric film is formed by the wet anodic oxidation method, which is a well-established electrochemical method of anodic oxidation solution, there is no defect in pin holes or edges. It has a dense structure and has a higher breakdown voltage. Further, since the film thickness of the anodic oxide film is precisely controlled by the applied voltage at the time of oxidation, a capacitor having extremely few variations in electrical characteristics within the wafer or between lots is formed.
【０００７】キャパシタ誘電体とキャパシタ上部電極と
の間のコンタクト薄膜層には、Ａｌ／Ｔｉ／Ｐｔ／Ａｕ
を用いる。このうち、キャパシタ誘電体の電気的接続を
とるＡｌは、キャパシタ誘電体として用いている金属酸
化膜からキャパシタ上部電極へ向かって酸素が拡散する
のを防ぐ働き（Ａｌは一旦酸化されると酸素の拡散に対
して障壁となる。）があり、キャパシタの電気的特性を
安定化させる（特に経時変化をなくする。）。また、Ａ
ｌ上部のＴｉ／Ｐｔ／Ａｕは、Ａｌとの接着性がよいだ
けでなく、化合物半導体デバイスのオーミック電極によ
く用いられているＡｕＧｅ／ＡｕあるいはＡｕＧｅ／Ｎ
ｉ／Ａｕとの電気的接続を低抵抗に、すなわち良好にす
る。The contact thin film layer between the capacitor dielectric and the capacitor upper electrode contains Al / Ti / Pt / Au.
To use. Of these, Al that electrically connects the capacitor dielectric serves to prevent oxygen from diffusing from the metal oxide film used as the capacitor dielectric toward the upper electrode of the capacitor (Al once oxidized, oxygen It acts as a barrier against diffusion, and stabilizes the electrical characteristics of the capacitor (especially eliminates changes over time). Also, A
Ti / Pt / Au on the upper part of 1 has not only good adhesiveness with Al, but also AuGe / Au or AuGe / N which is often used for ohmic electrodes of compound semiconductor devices.
Makes electrical connection with i / Au low resistance, that is, good.
【０００８】キャパシタ上部電極としてはＡｕを用い
る。Ａｕは、その下のＡｌ／Ｔｉ／Ｐｔ／Ａｕコンタク
ト薄膜層に対して接着性がよく、コンタクト抵抗が低い
ので、電気的特性のよいキャパシタ上部電極を形成す
る。Au is used as the upper electrode of the capacitor. Since Au has good adhesiveness to the Al / Ti / Pt / Au contact thin film layer thereunder and has low contact resistance, it forms a capacitor upper electrode having good electrical characteristics.
【０００９】請求項１の発明の方法は、化合物半導体デ
バイスの電極材料として実績のあるＡｌをキャパシタ下
部電極として利用するので、化合部半導体集積回路のプ
ロセス全体に対して支障をもらたす心配がないうえ、キ
ャパシタ誘電体Ａｌ2 Ｏ3 の誘電損失も小さいというメ
リットをもつ。In the method of the first aspect of the present invention, since Al, which has a proven track record as an electrode material for compound semiconductor devices, is used as the lower electrode of the capacitor, there is a concern that it may hinder the entire process of the compound semiconductor integrated circuit. In addition, there is an advantage that the dielectric loss of the capacitor dielectric Al 2 O 3 is small.
【００１０】請求項２の発明の方法は、キャパシタ誘電
体層として実用されている材料であるＴａ2 Ｏ5 を利用
するが、これは、比誘電率εｒの比較的高い（εｒ＝２
５）材料であるため、相対的にチップ上でレイアウト面
積の小さいキャパシタを実現でき、マイクロ波集積回路
への適用に向いている。The method according to the second aspect of the present invention utilizes Ta 2 O 5 which is a material practically used as a capacitor dielectric layer, which has a relatively high relative permittivity εr (εr = 2).
5) Since it is a material, it is possible to realize a capacitor having a relatively small layout area on a chip, which is suitable for application to a microwave integrated circuit.
【００１１】[0011]
【実施例】請求項１の発明の一実施例を図１と図３を用
いて説明する。図１は本発明の方法によって作製される
キャパシタの構造を示すための図であり、図３は本発明
の方法を説明するための図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the invention of claim 1 will be described with reference to FIGS. FIG. 1 is a diagram for showing a structure of a capacitor manufactured by the method of the present invention, and FIG. 3 is a diagram for explaining the method of the present invention.
【００１２】（１）下地１の上に、絶縁層２としてＳｉ
Ｏ2 をスパッタあるいは蒸着法などで全面に堆積する。(1) Si as an insulating layer 2 on the base 1
O 2 is deposited on the entire surface by sputtering or vapor deposition.
【００１３】（２）次に、キャパシタ下部電極及び下部
配線３としてＡｌをスパッタあるいは蒸着法などで全面
に堆積する。(2) Next, Al is deposited on the entire surface by sputtering or vapor deposition as the capacitor lower electrode and the lower wiring 3.
【００１４】（３）次に、レジストをウエハ全面に塗布
し、キャパシタ誘電体パターンと陰極パターン（図１の
４の部分に対応）の窓が開くよう、現像パターンニング
する。(3) Next, a resist is applied to the entire surface of the wafer, and development patterning is performed so that the windows of the capacitor dielectric pattern and the cathode pattern (corresponding to part 4 in FIG. 1) are opened.
【００１５】（４）次に、図３に示す陽極酸化の装置に
より、キャパシタ誘電体となる部分を陽極として、ウェ
ット陽極酸化を行い、Ａｌ2 Ｏ3 層４を形成する。電解
溶液には、例えば、五ホウ酸アンモニウム、エチレング
リコールと水の混合液（グライナー、Ｊ．Ｈ．ら：”フ
ァブリケイション・プロセス・フォア・ジョセフソン・
インテグレーテッド・サーキッツ”アイビーエム（ＩＢ
Ｍ）ジャーナル．Ｒ＆Ｄ．，２４，２，ｐｐ．１９５−
２０５（１９８０年３月））を用いる。通常、電流密度
は１０-4Ａ／ｃｍ2 程度が用いられ、膜厚は印加電圧に
より制御する。印加電圧と酸化膜厚は線形の関係にあ
る。(4) Next, wet anodic oxidation is performed by using the apparatus for anodic oxidation shown in FIG. 3 with the portion to be the capacitor dielectric as an anode to form an Al 2 O 3 layer 4. Examples of the electrolytic solution include ammonium pentaborate, a mixed solution of ethylene glycol and water (Greiner, JH, et al .: "Fabrication Process For Josephson.
Integrated Circuits "IBM (IB
M) Journal. R & D. , 24, 2, pp. 195-
205 (March 1980)). Usually, a current density of about 10 −4 A / cm 2 is used, and the film thickness is controlled by the applied voltage. The applied voltage and the oxide film thickness have a linear relationship.
【００１６】（５）レジスト除去した後、再びレジスト
をウエハ全面に塗布し、キャパシタ下部電極及び下部配
線３のパターンをパターンニングする。(5) After removing the resist, the resist is applied to the entire surface of the wafer again to pattern the pattern of the capacitor lower electrode and the lower wiring 3.
【００１７】（６）次に、イオンミリングやウェット・
エッチングなどの方法でエッチングし、キャパシタ下部
電極及び下部配線３だけ残す。(6) Next, ion milling or wet
Etching is performed by a method such as etching to leave only the capacitor lower electrode and the lower wiring 3.
【００１８】（７）レジスト除去した後、再びレジスト
をウェア全面に塗布し、キャパシタ上部電極及び電極コ
ンタクト層５のパターンの窓が開くよう、パターンニン
グする。(7) After removing the resist, the resist is applied to the entire surface of the garment again, and patterning is performed so that the window of the pattern of the capacitor upper electrode and the electrode contact layer 5 is opened.
【００１９】（８）ウェハ表面クリーンニング後、ウエ
ハ全面にＡｌ／Ｔｉ／Ｐｔ／Ａｕを蒸着し、リフトオフ
法によりキャパシタ上部電極及び電極コンタクト層５を
形成する。(8) After cleaning the wafer surface, Al / Ti / Pt / Au is deposited on the entire surface of the wafer, and the capacitor upper electrode and the electrode contact layer 5 are formed by the lift-off method.
【００２０】（９）同様に、リフトオフ法でＡｕ上部配
線６を形成する。(9) Similarly, the Au upper wiring 6 is formed by the lift-off method.
【００２１】以上の工程による本発明の方法により、耐
圧劣化がなく、また特性の均一性、再現性の良いキャパ
シタが得られる。According to the method of the present invention, which is based on the above steps, a capacitor having no deterioration in withstand voltage and having good characteristic uniformity and reproducibility can be obtained.
【００２２】請求項２の発明の一実施例を図２を用いて
説明する。図２は本発明の方法によって作製されるキャ
パシタの構造を示すための図である。An embodiment of the invention of claim 2 will be described with reference to FIG. FIG. 2 is a diagram showing a structure of a capacitor manufactured by the method of the present invention.
【００２３】（１）下地１の上に、絶縁層２としてＳｉ
Ｏ2 をスパッタあるいは蒸着法などで全面に堆積する。(1) Si as an insulating layer 2 on the base 1
O 2 is deposited on the entire surface by sputtering or vapor deposition.
【００２４】（２）次に、キャパシタ下部電極及び下部
配線７としてＴａをスパッタあるいは蒸着法などで全面
に堆積する。(2) Next, Ta is deposited on the entire surface as a capacitor lower electrode and lower wiring 7 by sputtering or vapor deposition.
【００２５】（３）次に、レジストをウエハ全面に塗布
し、キャパシタ誘電体パターンと陰極パターン（図２の
８の部分に対応）の窓が開くよう、現像パターンニング
する。(3) Next, a resist is applied to the entire surface of the wafer, and development patterning is performed so that the windows of the capacitor dielectric pattern and the cathode pattern (corresponding to the portion 8 in FIG. 2) are opened.
【００２６】（４）次に、キャパシタ誘電体となる部分
を陽極として、ウェット陽極酸化を行い、Ｔａ2 Ｏ5 層
８を形成する。電解溶液には、例えば、五ホウ酸アンモ
ニウム、エチレングリコールと水の混合液を用いる。(4) Next, wet anodic oxidation is carried out using the portion which will be the capacitor dielectric as an anode to form a Ta 2 O 5 layer 8. As the electrolytic solution, for example, a mixed solution of ammonium pentaborate, ethylene glycol and water is used.
【００２７】（５）レジスト除去した後、再びレジスト
をウエハ全面に塗布し、キャパシタ下部電極及び配線パ
ターンをパターンニングする。(5) After removing the resist, the resist is applied to the entire surface of the wafer again to pattern the capacitor lower electrode and the wiring pattern.
【００２８】（６）次に、イオンミリングやウェット・
エッチングなどの方法でエッチングし、キャパシタ下部
電極及び下部配線６だけ残す。(6) Next, ion milling or wet
Etching is performed by a method such as etching to leave only the capacitor lower electrode and the lower wiring 6.
【００２９】（７）レジスト除去した後、再びレジスト
をウエハ全面に塗布し、キャパシタ上部電極及び電極コ
ンタクト層５のパターンの窓が開くよう、パターンニン
グする。(7) After removing the resist, the resist is applied again on the entire surface of the wafer and patterned so that the window of the pattern of the capacitor upper electrode and the electrode contact layer 5 is opened.
【００３０】（８）ウエハ表面クリーンニング後、ウエ
ハ全面にＡｌ／Ｔｉ／Ｐｔ／Ａｕを蒸着し、リフトオフ
法によりキャパシタ上部電極及び電極コンタクト層５を
形成する。(8) After cleaning the wafer surface, Al / Ti / Pt / Au is vapor-deposited on the entire surface of the wafer, and the capacitor upper electrode and the electrode contact layer 5 are formed by the lift-off method.
【００３１】（９）同様に、リフトオフ法でＡｕ上部配
線６を形成する。(9) Similarly, the Au upper wiring 6 is formed by the lift-off method.
【００３２】以上の工程による本発明の方法により、キ
ャパシタの耐圧劣化のない、かつ均一性、再現性の良い
キャパシタが得られる。By the method of the present invention through the above steps, it is possible to obtain a capacitor which is free from deterioration of the withstand voltage of the capacitor and has good uniformity and reproducibility.
【００３３】[0033]
【発明の効果】本発明の方法により、耐圧劣化のない、
かつ均一性及び再現性の良い、ばらつきのないキャパシ
タが得られる。従って、本発明は、半導体集積回路の特
性向上に多大の貢献をなすものである。According to the method of the present invention, there is no deterioration in withstand voltage,
Further, it is possible to obtain a capacitor having good uniformity and reproducibility and no variation. Therefore, the present invention makes a great contribution to improving the characteristics of the semiconductor integrated circuit.
【図１】本発明を説明するための図。FIG. 1 is a diagram for explaining the present invention.
【図２】本発明を説明するための図。FIG. 2 is a diagram for explaining the present invention.
【図３】陽極酸化膜形成装置を示す図で、（ａ）は全体
図、（ｂ）は電極部を示す図である。3A and 3B are views showing an anodized film forming apparatus, wherein FIG. 3A is an overall view and FIG. 3B is a view showing an electrode portion.
１ 下地（Ｓｕｂｓｔｒａｔｅ） ２ ＳｉＯ2 絶縁層 ３ キャパシタ下部電極及び下部配線（Ａｌ） ４ Ａｌ2 Ｏ3 キャパシタ誘電体層 ５ キャパシタ上部電極及び電極コンタクト層（Ａｌ
／Ｔｉ／Ｐｔ／Ａｕ） ６ Ａｕ上部配線層 ７ キャパシタ下部電極及び下部配線（Ｔａ） ８ Ｔａ2 Ｏ5 キャパシタ誘電体層1 Substrate 2 SiO 2 Insulating Layer 3 Capacitor Lower Electrode and Lower Wiring (Al) 4 Al 2 O 3 Capacitor Dielectric Layer 5 Capacitor Upper Electrode and Electrode Contact Layer (Al
/ Ti / Pt / Au) 6 Au upper wiring layer 7 capacitor lower electrode and lower wiring (Ta) 8 Ta 2 O 5 capacitor dielectric layer
Claims (2)
程と、その表面層を陽極酸化することによりキャパシタ
誘電体Ａｌ2 Ｏ3 を形成する工程と、Ａｌ／Ｔｉ／Ｐｔ
／Ａｕコンタクト薄膜層を形成する工程と、キャパシタ
上部電極をＡｕで形成する工程を備えることを特徴とす
るキャパシタの製造方法。1. A step of forming a capacitor lower electrode with Al, a step of forming a capacitor dielectric Al 2 O 3 by anodizing a surface layer thereof, Al / Ti / Pt
/ Au contact thin film layer forming step, and a step of forming a capacitor upper electrode of Au, a method of manufacturing a capacitor.
程と、その表面層を陽極酸化することによりキャパシタ
誘電体Ｔａ2 Ｏ5 を形成する工程と、Ａｌ／Ｔｉ／Ｐｔ
／Ａｕコンタクト薄膜層を形成する工程と、キャパシタ
上部電極をＡｕで形成する工程を備えることを特徴とす
るキャパシタの製造方法。2. A step of forming a capacitor lower electrode with Ta, a step of forming a capacitor dielectric Ta 2 O 5 by anodizing the surface layer thereof, Al / Ti / Pt
/ Au contact thin film layer forming step, and a step of forming a capacitor upper electrode of Au, a method of manufacturing a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5320649A JP2570607B2 (en) | 1993-12-20 | 1993-12-20 | Method for manufacturing capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5320649A JP2570607B2 (en) | 1993-12-20 | 1993-12-20 | Method for manufacturing capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07176694A true JPH07176694A (en) | 1995-07-14 |
| JP2570607B2 JP2570607B2 (en) | 1997-01-08 |
Family
ID=18123775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5320649A Expired - Lifetime JP2570607B2 (en) | 1993-12-20 | 1993-12-20 | Method for manufacturing capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570607B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1005073A1 (en) * | 1998-11-27 | 2000-05-31 | Murata Manufacturing Co., Ltd. | Method of forming dielectric thin film pattern and method of forming laminate pattern comprising dielectric thin film and conductive thin film |
| KR100343049B1 (en) * | 1998-06-15 | 2002-07-02 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and manufacturing method thereof |
| WO2014102881A1 (en) * | 2012-12-28 | 2014-07-03 | 国立大学法人東北大学 | Semiconductor device, mis transistor, and multilayer wiring substrate |
| KR101432138B1 (en) * | 2012-09-26 | 2014-08-20 | 성균관대학교산학협력단 | Capacitor and method for manufacturing the same |
-
1993
- 1993-12-20 JP JP5320649A patent/JP2570607B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100343049B1 (en) * | 1998-06-15 | 2002-07-02 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and manufacturing method thereof |
| EP1005073A1 (en) * | 1998-11-27 | 2000-05-31 | Murata Manufacturing Co., Ltd. | Method of forming dielectric thin film pattern and method of forming laminate pattern comprising dielectric thin film and conductive thin film |
| KR101432138B1 (en) * | 2012-09-26 | 2014-08-20 | 성균관대학교산학협력단 | Capacitor and method for manufacturing the same |
| WO2014102881A1 (en) * | 2012-12-28 | 2014-07-03 | 国立大学法人東北大学 | Semiconductor device, mis transistor, and multilayer wiring substrate |
| JPWO2014102881A1 (en) * | 2012-12-28 | 2017-01-12 | 国立大学法人東北大学 | Multilayer wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2570607B2 (en) | 1997-01-08 |
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