JPH0717027Y2 - Timing generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial application field" This invention is used, for example, in a semiconductor test apparatus, and a timing switching data memory (a part of a test pattern memory) is read by an output address of an address counter, and the reading is performed. The present invention relates to a timing generator that reads a cycle setting memory according to the issued timing switching data and outputs a timing pulse having a cycle according to the read cycle setting data.

"Prior Art" FIG. 2 shows a conventional timing generator. When the start pulse (FIG. 3A) is input to the address counter 11, the address counter 11 is cleared and the address counter 11 is cleared.
The timing switching data memory 12 is read by the output address (FIG. 3B) from 11, and the cycle setting memory 13 is read by using the read timing switching data (FIG. 3C) as an address, and the reading is performed. The issued cycle setting data (FIG. 3D) is supplied to the cycle generator 14, and after a time corresponding to the cycle setting data, the timing pulse (FIG. 3E) is output from the cycle generator 14. The address pulse 11 is incremented by 1 by the timing pulse. The timing switching memory 12 is read again by the output address of the address counter 11, and the same operation is performed thereafter to generate timing pulses one after another.

When this timing generator is used in a semiconductor test device, the timing switching data memory 12 is configured as a part of the test pattern memory.

That is, each address of the test pattern memory stores the timing switching data indicating the cycle of the timing pulse to be generated, and the test pattern to be applied to each pin of the semiconductor device under test, that is, "1" or "0". There is.

[Problems to be solved by the invention] In the conventional timing generator, the timing switching data (number) is, for example, 1 to 16, and each time the test is changed to test A, test B, test C, ... The contents stored in the cycle setting memory 13 are rewritten in order to change the relationship between the timing switching data 1 to 16 and the cycle setting data so that the timing of the matched cycle can be obtained. This rewriting has a drawback that the test time as a whole becomes long.

According to the present invention, the timing switching data memory is read by the output address of the address counter, the data is externally set in the register, and the data of the register and the timing switching data memory are read. The added timing switching data is added by an adder, the cycle setting memory is read by the added data, and the read cycle setting data is supplied to the cycle generator to correspond to the cycle setting data. Timing pulses are generated in cycles.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. In this invention, there is provided a register 21 capable of setting data externally, for example, by a program, and the data of the register 21 and the timing switching data read from the timing switching data memory 12 are added by an adder 22. The cycle setting memory 13 is read by using the addition output as an address. Unlike the conventional case, the cycle setting memory 13 has a larger number of addresses than the data of the timing switching data memory 12. For example, the data of the timing switching data memory 12 is 1
16 and the addresses of the cycle setting memory 13 are 1 to 1024.

For example, test A, test B, test C, ... 16 each
If each of the 16 cycle setting data is assigned one of the timing switching data 1 to 16, each cycle setting data for the timing switching data 1 to 16 of the test A is required. Are stored in the addresses 1 to 16 of the cycle setting memory 13, the respective cycle setting data for the timing switching data 1 to 16 of the test B are stored in the addresses 17 to 32 of the cycle setting memory 13, and the timing switching data 1 to 1 of the test C are stored. Each cycle setting data for 16 is stored in addresses 33 to 48 of the cycle setting memory 13, and the same is performed thereafter.

Therefore, in any of the test A, the test B, the test C, ..., The timing switching data read from the timing switching data memory 12 is any one of 1 to 16. However, at the time of the test of the test A, the data 0 is stored in the register 21. 0 is added to the timing switching data 1 to 16 set and read from the timing switching data memory 12, and the addition outputs 1 to 16 are added.
The cycle setting memory 13 is read by, the data 16 is set in the register 21 at the time of the test B, and the data 16 is added to the timing switching data 1 to 16 read from the timing switching data memory 12. The cycle setting memory 13 is read by the addition outputs 17 to 32, the data 32 is set in the register 21 in the test of the test C, and the data 32 is set in the timing switching data 1 to 16 read from the timing switching data memory 12. Are added and the cycle setting memory 13 is read by the addition outputs 33 to 48. The same operation is performed thereafter.

In this way, it is not necessary to rewrite the contents of the cycle setting memory 13 for each test by using the test patterns described in the timing switching data 1 to 16 created for the conventional timing generator as they are. The test time can be shortened. Note that it is possible to rewrite the test patterns described in the timing switching data 1 to 16 for each of the tests A, B, C, ... To the timing switching data 1 to 1024, but in this case, the translation of the program, that is, The drawback is that it only takes time to translate a program to run hardware.

In the above description, the number of timing switching data in the timing switching data memory 12 is 16 and the number of addresses in the cycle setting memory 13 is 1024, but these numbers can be arbitrarily selected. Although the data in the register 21 is rewritten for each test, the data in the register 21 may be rewritten during one test if necessary. The data set in the register 21 may be arbitrary, and the adder 22 may perform the subtraction process.

"Effect of Device" As described above, according to this device, the timing switching data from the timing switching data memory 12 and the data of the externally settable register 21 are added, and the cycle setting memory 13 is read by the added data. Therefore, it is possible to access different addresses of the cycle setting memory 13 without rewriting the timing switching data memory 12, and for example, it is applied to a semiconductor test device and the conventional test pattern is used as it is, for each test. Cycle setting memory
A series of tests can be performed in a short time without rewriting 13.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional timing generator, and FIG. 3 is a time showing an operation example of the device shown in FIG. It is a chart.

Claims (1)

[Scope of utility model registration request] 1. An address counter for generating an address, a timing switching data memory read by an output address from the address counter, a register to which data is externally set, data of the register and the timing switching data memory. An adder for adding the read timing switching data, a cycle setting memory read by the added data from the adder, and a timing corresponding to the cycle setting data read from the cycle setting memory A timing generator comprising: a period generator that generates a pulse.