JPH07169837A - Manufacture of wiring in close proximity - Google Patents

Abstract

PURPOSE:To form a fine wiring pattern without damages on a conductor layer with regard to the manufacturing method of a semiconductor element, wherein wirings are formed between the conductor layers in close proximity. CONSTITUTION:On an element region including diffused layer regions 7, 8 and 12 or gate electrodes 5 and 10, the laminated structure of a first conductor film 15 and a second conductor film 16 is formed. The second conductor film 16 is selectively etched by a dry etching method, and the surface of the first conductor film 15 is exposed. The first conductor film 15 is etched by a wet etching method. Thus, the wirings among the diffused layers 7, 8 and 12 and the gate electrodes 5 and 10 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method between conductive regions in a semiconductor integrated circuit. With the high integration of semiconductor devices, it is necessary to reduce the element region and the wiring region. However, in the multi-layer wiring process using a plurality of polycrystalline silicon films, metal films, metal silicides, etc., it is necessary to form an insulating film and to open an element region, and it is necessary to secure a positioning margin. Has become a big issue for the reduction of.

In recent years, proximity wiring (Local Interconnection) has been used in which an adjacent diffusion region or polycrystalline silicon region is connected by a conductive film without using an insulating film or an opening for contact.
Law is drawing attention.

[0003]

2. Description of the Related Art Conventionally, many reports have been made on the proximity wiring method. IEDM (International Elec
As an example of this method, a method of using a refractory metal silicide film such as a tungsten silicide film (WSix) for the wiring layer is disclosed on page 118 of a 1984 bulletin of the tron device meeting) society.

The method will be described with reference to FIGS. FIG. 8 is a circuit diagram of a cell portion of the CMOS ring oscillator. Vcc is a power supply line, Vss is a ground line, Q7 and Q9 are P-channel MOSFETs, Q8 and Q1.
0 is an N-channel MOSFET. A region B (region surrounded by a dotted line in the drawing) in the drawing is wired by proximity wiring.

FIG. 9 is a plan view of a cell portion of the ring oscillator shown in FIG. 8, both showing two cells.
FIG. 9A shows the case where the proximity wiring is not used, and FIG. 9B shows the case where the proximity wiring is used. V of aluminum (Al) wiring
There is a cc line 91 and a Vss line 92, and the gate electrode 94 of polycrystalline silicon is a P channel MOSFET and an N
It is a common gate that doubles as the gate of the channel MOSFET.

The wiring in the area B in FIG. 8 is A in FIG. 9 (A).
1 wiring 93, and in FIG.
It is done in. The source / drain diffusion layers and the gate electrode are in contact with the Al wiring through a contact hole 96. In FIG. 9A which does not use the proximity wiring, the number of contact holes required for each cell is five.
In FIG. 9B in which the adjacent wiring is used, the number can be reduced to two per cell and the size of the cell can be reduced.

Next, a manufacturing method thereof will be described based on the process cross-sectional views of FIGS. FIG. 10 is a sectional view taken along line XX ′ of FIG. In the figure, 101 is a P-type semiconductor substrate, 102 is an N-type well, and 1
Reference numeral 03 is a field oxide film, 104 and 109 are gate oxide films, 105 and 110 are gate electrodes, 106 and 111 are sidewall oxide films formed on the side walls of the gate electrode, 107 is a low concentration N type diffusion layer region, and 108 is a high concentration. N-type diffusion layer region, 112 is a high-concentration P-type diffusion layer region, 11
5 is a tungsten film, 116 is an amorphous silicon film, and 118 is a tungsten silicide film.

First, as shown in FIG. 10A, a P channel and an N surrounded by a field oxide film are formed by an ordinary method for manufacturing a self-aligned CMOS integrated circuit.
Form a channel MOSFET. On the P-type substrate 101,
There is an N-type well region 102, and LOCOS (LOCal Oxida
The element regions are separated by the field oxide film 103 formed by the method of silicon of the like.

The N-channel MOSFET is an LDD (Ligh
tly Doped Drain) structure, on the P-type substrate 101, a polycrystalline silicon gate electrode 105, a gate oxide film 104, a low-concentration N-type diffusion layer region 107, and a high-concentration N-type diffusion layer region 10.
It is composed of 8. The P-channel MOSFET has a polycrystalline silicon gate electrode 11 on the N-type well region 102.
0, the gate oxide film 109, the high concentration P-type diffusion layer region 112
It is composed of.

First, the tungsten film 11 is formed on the entire surface of the substrate.
5 and the amorphous silicon film 116 are sequentially formed. Next, as shown in FIG. 10B, a resist 117 is formed, and the amorphous silicon film 116 is etched into a desired wiring shape by using a normal dry etching means.

Since amorphous silicon and tungsten have a large etching selection ratio, the gate electrodes 105, 110, which are under the tungsten film 115,
The amorphous silicon film 116 can be etched without affecting the 113 and the diffusion layers 108 and 112. Next, as shown in FIG. 10C, after removing the resist 117, heat treatment is performed in an inert gas to form silicon regions of the diffusion layers 108 and 112 and the gate electrode 10.
The polycrystalline silicon film of 5, 110, 113 is reacted with tungsten to form tungsten silicide.

At the same time, the tungsten film 115 and the amorphous silicon film 116 on which the wiring pattern is formed react with each other to form a tungsten silicide wiring layer. At this time, the region where the amorphous silicon has been removed remains tungsten because it does not undergo a silicidation reaction. Next, the unreacted tungsten is etched by a wet etching method using acid or the like. Since the etching selectivity between tungsten and tungsten silicide or the oxide film layer is large, etching can be performed without damaging the tungsten silicide or the oxide film layer.

By the above method, the adjacent wiring layer can be formed without damaging the diffusion layers of the source and drain portions and the polycrystalline silicon film of the gate electrode. Further, as another example of forming the proximity wiring layer, US Pat.
There are methods disclosed in 4,793,896, 4,821,085 and 5,010,032. In these patents, titanium nitride (TiN) obtained by nitriding titanium (Ti) as an adjacent wiring layer is used.
Alternatively, a metal compound such as oxidized titanium oxide (TiO) is used.

Self-aligned silicide (Salicide for short) is used for the diffusion layer silicon regions of the source and drain parts and the polycrystalline silicon film of the gate part.
The method is characterized in that it is silicided to titanium silicide (TiSi) by the method and at the same time, metal nitriding and oxidation are performed, and this metal compound is used as an adjacent wiring. Figure 11
The method will be described based on the process cross-sectional views. In the figure, the same numbers as those in FIG. 10 indicate the same or corresponding portions as those in FIG.

First, as shown in FIG. 11A, a CMOSFET is formed by using the same process as in the first conventional example, and then a metal film 115 is formed on the entire surface. next,
As shown in FIG. 11B, high temperature heat treatment is performed along with a normal salicide process to form the diffusion layer 1 of the source and drain portions.
Silicon regions 08 and 112, and gate electrode 10
The metal silicide film 120 is formed by reacting the polycrystalline silicon regions 5, 110 and 113 with the metal film.

As described above, this heat treatment forms the silicide 120 and the metal compound 121. For example, if the heat treatment is performed in a nitrogen atmosphere, the metal film is nitrided to form metal nitride. Further, if the treatment is performed in an oxygen atmosphere, the metal film is oxidized to form metal oxide. Next, as shown in FIG. 11C, a resist 117 is used to form a metal compound 121 on a desired wiring pattern.
The adjacent wiring is formed by etching.

The etching of the metal compound 121 must be performed by a method that does not damage the underlying silicon region or the oxide film layer. In the above three patents, the following methods have been proposed as etching methods.
In US Pat. No. 4,821,085, titanium nitride (TiN) is used as a metal compound in a wiring pattern. The titanium nitride is etched by a wet etching method using a mixed solution of hydrogen peroxide solution and sulfuric acid so that the underlying layer is not affected.

However, since the mixed solution also etches the resist used for pattern formation, it is not possible to form a desired wiring pattern with the resist alone. Therefore, an oxide film is formed on the titanium nitride film by chemical vapor deposition (CVD), etc., the oxide film is etched by plasma etching, and the oxide film is used as a mask for patterning. Is taking a way.

In US Pat. No. 4,793,896, the wiring pattern contains titanium nitride (TiN) as a metal compound,
Alternatively, titanium oxide (TiO) is used, and etching is performed by a dry etching method using carbon tetrachloride (CCl4). Carbon tetrachloride has a low etching rate with respect to an oxide film and not only has a high etching selection ratio, but also has a low etching rate with respect to a titanium silicide layer.

This is because the carbon in carbon tetrachloride reacts with titanium or silicon to form titanium carbide (TiC) or silicon carbide (SiC), and the surface of the carbon is covered with chlorine (Cl) to etch silicon or titanium. This is because the reaction can be suppressed. Therefore, the metal nitride or metal oxide layer can be etched without affecting the base.

In US Pat. No. 5,010,032, titanium nitride is used as a metal compound in a wiring pattern. As a method for etching titanium nitride, a wet etching method is used with a mixed solution of hydrogen peroxide water and ammonia water. Alternatively, a method has been proposed in which dry etching is performed to about 80% of the film thickness using a mixed gas of carbon tetrafluoride (CF4) and helium, and then wet etching is performed using a mixed solution of hydrogen peroxide solution and ammonia water. There is.

Since the mixed solution also etches the resist, it is etched using the oxide film as a mask, as in US Pat. No. 4,821,085. Further, instead of using an oxide film mask, a method of hardening the resist by an ion implantation method to increase the etching resistance is also shown.
Further, there is also disclosed a method of selectively implanting oxygen ions or the like into the titanium nitride film to be left as a wiring by an ion implantation method to change the quality of the film, thereby lowering the wet etching rate.

[0023]

First of all, the problems in the case where a metal silicide film such as titanium silicide is used as the adjacent wiring material shown as the first conventional example will be described. Regarding the method of forming wiring by forming amorphous silicon on a refractory metal, a sufficient dry etching method can be used to obtain a sufficient selection ratio. Therefore, the diffusion layer silicon and the polycrystalline silicon of the gate are etched. There is no problem and there is no problem.

However, a metal silicide film such as titanium silicide has a low diffusion barrier property against impurities such as phosphorus and boron, and impurity atoms can easily pass through the metal silicide. Therefore, for example, in a CMOS device, when connecting the N-type diffusion layer and the P-type diffusion layer, or when connecting the P-type diffusion layer and the N-type doped polycrystalline silicon film, conductivity types opposite to each other are used. Therefore, there is a problem that the carrier concentration is lowered, the contact resistance is increased, and an unnecessary PN junction is formed.

Next, the problem of the system using a metal compound such as metal nitride or metal oxide for the wiring layer, which is shown as the second conventional example, will be described. By using a metal compound having a large diffusion barrier property against impurities such as phosphorus and boron, the impurities described in the first conventional example interdiffuse, and the impurity concentration of the diffusion layer and polycrystalline silicon decreases. Therefore, there is no problem that the contact resistance is increased and an unnecessary PN junction is formed.

However, this method has a problem of etching the wiring layer. When the metal compound is etched by wet etching in consideration of the influence on the underlying metal silicide, it is difficult to control the width of the wiring and it is difficult to form a fine wiring pattern. Therefore, a dry etching method having a high etching selection ratio between the underlying silicide and the metal compound must be used.

US Pat. No. 4,821,085 describes carbon tetrachloride.
Although a method of etching a metal compound by using (CCl4) without damaging the underlying silicide has been shown, unfortunately carbon tetrachloride cannot be actually used due to CFC regulations. Therefore, in the method shown in the second conventional example, there is no dry etching method that does not damage the base.

As described above, if there is no problem in forming a wiring pattern, there is a problem that contact resistance increases due to diffusion of impurities. If a material that does not diffuse impurities is used, the base is damaged. There is a problem that it is difficult to form a wiring pattern without giving

[0029]

The present invention provides a manufacturing method which solves the above problems. FIG. 1 is a principle diagram of proximity wiring according to the present invention. In the figure, 1 is a P-type semiconductor substrate, 2 is an N-type well, 3 is a field oxide film, 4 and 9 are gate oxide films, and 5 and 10 are gate electrodes. , 6 and 11 are sidewall oxide films formed on the sidewalls of the gate electrode, 7 is a low concentration N type diffusion layer region, 8 is a high concentration N type diffusion layer region, 12 is a high concentration P type diffusion layer region, and 15 is a first , And 16 is a second conductive film.

The above problem is that the insulating film 3 is formed on the semiconductor substrate 1.
And a step of forming an element region surrounded by and the above-mentioned element region and the insulating film 3 including the diffusion layer regions 7, 8, 12 or the gate electrodes 5, 10 have a dry etching rate of the first conductivity type. The second conductive film is larger than the second conductive film, and the wet etching rate is higher in the first conductive film than in the second conductive film;
The step of forming a laminated structure of the conductive film 16; and the step of selectively etching the second conductive film 16 by a dry etching method to expose the surface of the first conductive film 15. By etching the conductive film 15 of No. 1 by a wet etching method, the diffusion layer 7,
8 and 12, and a step of forming a wiring between the gate electrodes 5 and 10, which is solved by a method for manufacturing a semiconductor device.

Alternatively, a step of forming an element region surrounded by the insulating film 3 on the semiconductor substrate 1 and the diffusion layer regions 7, 8, 12 and the gate electrodes 5, 1 in the element region are formed.
The step of forming a metal silicide on the surface of 0 and the dry etching rate on the device region including the diffusion layer regions 7, 8, 12 or the plurality of gate electrodes 5, 10 and the insulating film 3 are A first conductive film 15 in which the second conductive film is larger than the first conductive film and the wet etching rate is higher in the first conductive film than in the second conductive film; A step of forming a laminated structure of the second conductive film 16; a step of selectively etching the second conductive film 16 by a dry etching method to expose the surface of the first conductive film 15; First conductive film 15
Is formed by wet etching to form wiring between the diffusion layers 7, 8, 12 and the gate electrodes 5, 10 by a method of manufacturing a semiconductor device. It

Alternatively, a metal or a metal compound and a first conductive film 15 are formed on the element region and the insulating film 3 including the diffusion layer regions 7, 8, 12 or the gate electrodes 5, 10. A step of sequentially forming the second conductive film 16; a step of selectively etching the second conductive film 16 by a dry etching method to expose the surface of the first conductive film 15; The step of etching the conductive film 15 of No. 1 by a wet etching method to selectively expose the surface of the metal or the metal compound; and the selective removal of the metal or the metal compound by etching, thereby forming the diffusion layer 7. 8 and 12, and a step of forming a wiring between the gate electrodes 5 and 10, which is solved by the method for manufacturing a semiconductor device.

Alternatively, a step of forming a wiring between the diffusion layers 7, 8, 12 or the gate electrodes 5, 10; and a step of forming the wiring and the diffusion layers 7, 8, 12 and the gate electrodes 5, 10 And a step of selectively forming a tungsten film on the surface of the semiconductor device. Alternatively, the first conductive film 15 is made of copper, and the second conductive film 16 is made of a metal other than copper.

[0034]

The effect of the present invention will be described with reference to the principle diagram of FIG. An N-type well 2 is formed in a P-type substrate 1 and element regions are separated by a field oxide film 3.
The P-type substrate 1 includes a gate oxide film 4, a gate electrode 5, a low-concentration N-type diffusion layer region 7, and a high-concentration N-type diffusion layer region 8.
An LDD type N-channel MOSFET is formed.

In the N-type well 2, the gate oxide film 9, the gate electrode 10 and the high-concentration P-type diffusion layer region 12 form a P-channel MOSFET. N channel MOSFE
The diffusion layer 8 of T and the diffusion layer 12 of P-channel MOSFET are connected to each other by an adjacent wiring. As the adjacent wiring, a multilayer wiring of copper 15 as the first conductive film and second conductive film 16 is used.

First, the effect of the present invention on the diffusion of impurities will be described. Since the copper 15 alone has a diffusion barrier property against impurities such as phosphorus and boron, it is possible to use, as the second conductive film 16, one having no diffusion barrier property such as silicide. Of course, there is no problem even if a metal compound having a diffusion barrier property is used as the conductive film 16. Next, the effect of the present invention regarding the etching process at the time of forming the adjacent wiring will be described.

In the dry etching process, generally, a fluorine-based or chlorine-based halogen compound is used for etching. Since copper has a low boiling point as a compound with a halide and a low vapor pressure at room temperature, copper cannot be etched by a normal dry etching method. Therefore, by forming the copper 15 in the lower layer of the wiring layer metal or the metal compound 16, it can be used as a stopper for dry etching. This can prevent the diffusion layers 8 and 12, the polycrystalline silicon films 5 and 10, or the silicide layer from being damaged by etching.

On the contrary, copper has a higher etching rate for a wet etching solution such as nitric acid than other metals or metal compounds such as tungsten and titanium. Therefore, it is possible to etch the copper 15 without affecting the wiring metal or the metal compound 16. Of course, in this wet etching, the underlying diffusion layers 8 and 1
2. It does not damage the polycrystalline silicon films 5, 10 or the silicide layer.

Since the wet etching of copper is an isotropic etching, the side etching progresses so that an overhang occurs in the adjacent wiring layer, but the influence is reduced by reducing the thickness of copper. be able to.

[0040]

FIG. 2 is a circuit diagram for explaining an embodiment of the present invention, showing a circuit of a cell portion of a 6-transistor type complete CMOS static RAM. Transistors Q1 and Q3 are P-channel MOSFETs, and the remaining transistors Q2, Q4, Q5 and Q6 are N-channel MO.
It is an SFET.

In the figure, BL and BL bar indicate bit lines, and W indicates word lines. Vcc is a power supply line and Vss is a ground line. The method of closely wiring the area A (the area surrounded by the dotted line in the drawing) will be described below.
A description will be given based on each example. In the region A, the diffusion layers of the transistors Q1, Q2, Q5 and the transistors Q3, Q4
The common gate portion of is wired.

3 and 4 are process sectional views showing the first embodiment of the present invention. In FIGS. 3 and 4, the same numbers as those in FIG. 1 indicate the same or corresponding parts. First, Fig. 3 (A)
As shown in FIG. 5, the P-channel and N-channel MOSFETs surrounded by the field oxide film are formed by a normal method of manufacturing a self-aligned CMOS integrated circuit.

As a forming method, for example, the following method may be used. The P-type substrate 1 is formed into an N
The mold well region 2 is formed. Subsequently, a field oxide film 3 is formed by a LOCOS process, and element regions are formed separately. Next, a gate oxide film is formed on the element region by a thermal oxidation method. At this time, depending on the characteristics of the transistor, the gate oxide film 4 of the N-channel MOSFET may be formed by a method of selectively removing the oxide film and then re-oxidizing it.
The thickness of the gate oxide film 9 of the P-channel MOSFET may be changed.

After growing polycrystalline silicon to be a gate electrode and introducing impurities such as phosphorus by a thermal diffusion method or the like,
By patterning, the gate electrode 5 of the N-channel MOSFET and the gate electrode 10 of the P-channel MOSFET are formed. At this time, another M is formed on the field oxide film 3.
The contact wiring 13 of the OSFET is also formed. Next, a region for forming the P-channel MOSFET is protected by a resist or the like, and an N-type material such as phosphorus (P) is formed by an ion implantation method.
A type impurity is introduced to form a diffusion layer region 7 having a low concentration.

Subsequently, an oxide film is grown by the CVD method, and reactive ion etching (Reactive Ion Etching,
Hereinafter, the oxide film is anisotropically etched using a method called RIE) to form oxide film sidewalls 6 and 11 on the side surfaces of the gate electrodes 5 and 10. The sidewall 14 is also formed on the sidewall of the polycrystalline silicon 13 on the field oxide film 3.
Is formed.

Next, the P-channel MOSFET region is protected by a resist or the like, and an N-type impurity such as arsenic (As) is introduced by an ion implantation method to form a high-concentration N-type diffusion layer region 8. In addition, the N-channel MOSFET region is protected by a resist or the like, and a P-type impurity such as boron (B) is introduced by an ion implantation method to obtain a high-concentration P-type diffusion layer region 12.
To form.

Subsequently, heat treatment is performed to activate the impurities in the diffusion layer regions 7, 8 and 12. Through the above steps,
LDD structure N-channel MOSFET and P-channel M
A CMOSFET with OSFET is formed. next,
As shown in FIG. 3 (B), copper 15 is deposited by a sputtering method.
After forming 100 Å, the tungsten film 16 is formed thereon by 1000 Å.

Next, as shown in FIG. 3C, a resist 17 for forming a proximity wiring is applied, and after patterning, the tungsten film 16 is etched. The etching was carried out using a parallel plate type dry etching device under the conditions of Cl2 100 cc, reaction pressure 20 mTorr and high frequency power 300 W. Next, FIG.
As shown in (A), using the resist 17 and the tungsten film 16 as masks, 62% nitric acid was used to remove copper 15 at room temperature.
To etch. At this time, since the etching rate of copper is about 10 times the etching rate of tungsten, the copper 1
5 can be etched.

Next, as shown in FIG. 4B, the resist 17 is removed using oxygen plasma. At this time, the resist 17 may be removed using a mixed solution of ammonia and hydrogen peroxide solution or a mixed solution of sulfuric acid and hydrogen peroxide solution. By the above method, the N-channel MOSFET and the P-channel M
Proximity wiring having a two-layer structure of copper and tungsten that connects the diffusion layer of the OSFET and the polycrystalline silicon of the gate electrode of another FET can be formed.

FIG. 5 is a process sectional view of the second embodiment of the present invention. In the figure, the same numbers as those in FIGS. 3 and 4 indicate the same or corresponding portions. As shown in FIG. 5A, the P-channel and N-channel MOSFs surrounded by the field oxide film 3 are formed by the same method as that described in the first embodiment.
Form ET.

Next, as shown in FIG. 5 (B), titanium is grown on the entire surface by 500 Å by sputtering. Continuing,
Heat treatment is performed at 1000 ° C. for 15 seconds by a rapid thermal anneal (hereinafter referred to as RTA) method so that titanium, the N-type diffusion layer 8, the P-type diffusion layer 12, and the polycrystalline silicon layers 5, 10, 13 are formed. And reacts with the silicon on the top surface to form a titanium silicide film 18.

Subsequently, the unreacted titanium film is removed by etching with a mixed solution of hydrogen peroxide solution and ammonia. next,
As shown in FIG. 5C, copper 15 is sputtered by
After forming 100 Å, the tungsten film 16 is formed thereon by 1000 Å. Thereafter, etching is performed using the same process as that of the first embodiment to form a proximity wiring having a two-layer structure of copper and tungsten. Note that titanium silicide is not etched with 62% nitric acid, so copper 1
The etching of 5 has no effect on the titanium silicide film 18.

According to the method of this embodiment, since the silicide layer 18 is provided below the copper layer 15, the effect of preventing copper from penetrating into the silicon layer by the heat treatment in the subsequent step as compared with the first embodiment is achieved. There is. FIG. 6 is a sectional view showing a third embodiment of the present invention. Since the manufacturing process is similar to that of the first embodiment, the process sectional view is omitted. In the figure, the same numbers as those in FIGS. 3 and 4 indicate the same or corresponding portions.

P-channel and N-channel MOSFETs surrounded by the field oxide film 3 are formed by the same method as in the first and second embodiments. Next, a titanium tungsten film 19 is formed as a barrier metal layer by a sputtering method at 100 Å
Form. Next, copper 15 is sputtered to 100
Å is formed, and the tungsten film 16 is formed thereon by sputtering to 1000Å.

Next, a resist pattern for forming adjacent wiring is formed, and the tungsten film 1 is formed by the same method as in the first embodiment.
6 and copper 15 are sequentially etched. Since the etching rate of titanium-tungsten with respect to 62% nitric acid is about one-tenth that of copper, the titanium-tungsten film 19 is hardly etched when the copper 15 is etched.

Next, the titanium tungsten film 19 is etched. The etching was performed by using a parallel plate type dry etching apparatus with Cl2 100 CC, reaction pressure 20 mTorr and high frequency power 300 W. The thickness of the titanium tungsten film 19 is 10
Since it is as thin as 0Å, it can be etched with almost no damage to the silicon layer. Subsequently, the resist 17 is removed by using oxygen plasma, and a proximity wiring having a three-layer structure of titanium-tungsten, copper, and tungsten can be formed.

In the method of this embodiment, since titanium tungsten 19 is provided as a barrier metal layer between the copper 15 and the underlying silicon layers 8, 12, 5, 10, 13, copper is removed by heat treatment in a subsequent step. It has the effect of preventing it from penetrating into the silicon layer. Although the source and drain diffusion layers have been described as being silicon layers in this embodiment, it goes without saying that they can be manufactured in the same manner by using the silicide structure shown in the second embodiment.

FIG. 7 is a sectional view showing a fourth embodiment of the present invention. Since the manufacturing process is similar to that of the first embodiment, the process sectional view is omitted. Numbers in the figure that are the same as those in FIGS. 3 and 4 indicate the same or corresponding portions. A proximity wiring layer having a two-layer structure of copper and tungsten is formed by using the same method as that described in the first embodiment.

Next, as shown in FIG. 7, silane (SiH4) and tungsten hexafluoride (WF6) were used by the CVD method,
A tungsten film 20 is selectively grown at a growth temperature of 300 ° C. The tungsten film 20 includes silicon layers 8, 12, 5,
It grows on the side wall portions of 10, 13 and copper 15 and on the upper tungsten film 16 of the adjacent wiring and on the side wall. In the present embodiment, the tungsten film 20 is grown on the side wall of the copper 15 to make it difficult for the oxygen atmosphere to reach the copper 15, which has an effect of preventing the copper 15 from being oxidized in the subsequent process.

Although the source / drain diffusion layers have been described as silicon layers in this embodiment, the silicide structure shown in the second embodiment may be used. Needless to say, as shown in the third embodiment, even if the barrier metal layer 19 is used under the copper 15, the same production can be performed. First to
In the fourth embodiment, tungsten is used as an example of the second conductive film 16 formed on the copper 15, but metals such as molybdenum, titanium, cobalt, and chromium, and metal compounds such as titanium tungsten and titanium nitride are used. Even if you use
It goes without saying that the same effect can be obtained. If there is a margin in resistance, a silicide film such as tungsten silicide, molybdenum silicide, or chromium silicide can be used.

Although copper is used as the first conductive film 15 in the first to fourth embodiments, it may have a lower dry etching rate and a lower wet etching rate than the second conductive film. For example, another conductive film such as a copper alloy can also be used. Although the structure using titanium as the salicide structure has been described in the second embodiment, it goes without saying that the same effect can be obtained by using palladium, cobalt, chromium, nickel, platinum or the like.

In the third embodiment, titanium-tungsten is used as the barrier metal for preventing the invasion of copper into the silicon layer. However, the same applies when titanium nitride, tantalum, cobalt, carbon or titanium bromide is used as the barrier metal. Can be obtained. In the first, second, and fourth examples, the resist 17 was removed after the etching of the copper 15, but the resist 17 was peeled off before the etching of the copper 15, and the upper conductive film 16 was removed.
The copper 15 may be wet-etched using the as a mask.

In the first to fourth embodiments, nitric acid is used as the wet etching solution for the copper 15, but the upper conductive film 16 is used.
In the case of silicide or the like, other acids capable of etching copper, a mixed solution of ammonia water and hydrogen peroxide water, or the like can also be used. As the first to fourth examples, the CMO
The S structure was explained, but the bipolar structure and BiCM
Needless to say, the same effect can be obtained with the OS structure.

[0064]

According to the present invention, the adjacent wiring layer has a two-layer structure in which the lower layer is a thin film of copper and the upper layer is a conductive film of metal, metal compound, metal silicide or the like. Since the underlying copper is difficult to dry-etch, it can be used as an etching stopper. Therefore, the upper conductive film can be dry-etched without damaging the underlying diffusion layer or the polycrystalline silicon layer.

Since the lower layer copper is also wet-etched, the underlying diffusion layer and the polycrystalline silicon layer are not damaged. Therefore, it is possible to form a fine pattern using the dry etching method without damaging the underlying diffusion layer or the polycrystalline silicon layer. Further, by forming metal silicide on the surfaces of the diffusion layer and the polycrystalline silicon film, it is possible to alleviate the invasion of copper into the diffusion layer and the polycrystalline silicon layer.

Further, by providing a thin barrier metal layer below the lower copper layer, it is possible to prevent copper from entering the diffusion layer and the polycrystalline silicon layer. Furthermore, after wiring formation,
By selectively forming the tungsten film and covering the area around the copper, it is possible to prevent the copper from being oxidized.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of proximity wiring according to the present invention.

FIG. 2 is a circuit diagram of a cell portion of a 6-transistor type complete CMOS static RAM used as an example according to the present invention.

FIG. 3 is a process sectional view of a first embodiment according to the present invention.

FIG. 4 is a process sectional view of the first embodiment according to the present invention.

FIG. 5 is a process sectional view of a second embodiment according to the present invention.

FIG. 6 shows a third embodiment according to the present invention.

FIG. 7 shows a fourth embodiment according to the present invention.

FIG. 8 is a circuit diagram of a cell portion of a ring oscillator for explaining a proximity wiring method according to a conventional method.

FIG. 9 is a plan view of a cell portion of a ring oscillator for explaining a proximity wiring method according to a conventional method.

FIG. 10 is a process sectional view for explaining a problem in the manufacturing method according to the first conventional example.

FIG. 11 is a process sectional view for explaining a problem of the manufacturing method according to the second conventional example.

[Explanation of symbols]

 1,101 P-type semiconductor substrate 2,102 N-type well 3,103 Field oxide film 4,104 Gate oxide film 5,105 Gate electrode 6,106 Oxide film sidewall 7,107 Low-concentration N-type diffusion layer region 8,108 High concentration N type diffusion layer region 9,109 Gate oxide film 10,110 Gate electrode 11,111 Oxide film side wall 12,112 High concentration P type diffusion layer region 13,113 Polycrystalline silicon 14,114 Oxide film side wall 15th Conductive film 16 1 Second conductive film 17, 117 Resist 18 Metal silicide film 19 Barrier metal layer 20 Tungsten film 91 Aluminum power supply line 92 Aluminum ground line 93 Aluminum wiring 94 Common gate electrode 95 Proximity wiring layer 96 Contact portion 115 Tungsten film 116 Amol Fas silicon film 118 Tungsten silicide film 119 Titanium film 120 Titanium silicide film 121 Titanium nitride film

Claims (5)

[Claims] 1. A step of forming an element region surrounded by an insulating film (3) on a semiconductor substrate (1), and a diffusion layer region (7,8,12) or a gate electrode (5,10). Including,
A dry etching rate of the second conductive film is higher than that of the first conductive film and a wet etching rate is higher than that of the second conductive film on the element region and the insulating film (3).
Forming a laminated structure of the first conductive film (15) and the second conductive film (16) so that the second conductive film (16) is larger than the second conductive film (16). By selectively etching the first conductive film (15) to expose the surface of the first conductive film (15), and by etching the first conductive film (15) by a wet etching method, the diffusion layer (7, 8, 12) and a step of forming wiring between the gate electrodes (5, 10). 2. A step of forming an element region surrounded by an insulating film (3) on a semiconductor substrate (1), a diffusion layer region (7, 8, 12) in the element region, or a gate electrode ( 5,10) forming a metal silicide on the surface of the diffusion layer region (7,8,12) or the plurality of gate electrodes
The dry etching rate of the second conductive film is higher than that of the first conductive film on the element region and the insulating film (3) including (5, 10), and the wet etching rate is higher than that of the second conductive film. A step of forming a laminated structure of the first conductive film (15) and the second conductive film (16) such that the first conductive film is larger than the film, and the second conductive film (16) ) Is selectively etched by a dry etching method to expose the surface of the first conductive film (15), and the first conductive film (15) is etched by a wet etching method. A method of manufacturing a semiconductor device, comprising the steps of forming a diffusion layer (7, 8, 12) and a wiring between the gate electrodes (5, 10). 3. The device region and the insulating film including the diffusion layer region (7, 8, 12) or the gate electrode (5, 10)
(3) The metal or metal compound and the dry etching rate of the second conductive film are higher than those of the first conductive film.
A step of sequentially forming a first conductive film (15) and a second conductive film (16) so that the wet etching rate of the first conductive film is higher than that of the second conductive film; A step of selectively etching the second conductive film (16) by a dry etching method to expose the surface of the first conductive film (15); and a wet etching method for the first conductive film (15). Etching, selectively exposing the surface of the metal or metal compound, by selectively etching away the metal or metal compound, the diffusion layer (7,8,12), and the gate 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a wiring between the electrodes (5, 10). 4. A step of forming wiring between the diffusion layers (7,8,12) and the gate electrodes (5,10), the wiring and the diffusion layers (7,8,12), and 4. A method of manufacturing a semiconductor device according to claim 1, further comprising the step of selectively forming a tungsten film on the surface of the gate electrode (5, 10). 5. Copper is used as the first conductive film (15),
The method for manufacturing a semiconductor device according to claim 1, wherein a metal other than copper is used as the second conductive film (16).