JPH07168425A - Bias generating device - Google Patents

Abstract

PURPOSE:To prevent overshoot from occurring at an output end during the generation of intermediate voltage by providing a clipping means clipping the voltage of the output end at a ground level during the generation of intermediate voltage. CONSTITUTION:Positive high voltage, negative high voltage and the intermediate voltage between both of high voltage are periodically generated, and the voltage of the output end is clipped at the ground level during the generation of intermediate voltage. In such a case, a clipping circuit 14 enables its action according to a zero timing signal from a timing signal generation circuit 10, and clipping action is performed so that the voltage of a switching point may not exceed the ground level. By providing a clipping detecting means detecting that the voltage is clipped by the clipping means and making a high voltage switching circuit (A) 6 in an off-state by output from the clipping detecting means, the voltage of the output end is clipped at the intermediate voltage level during the generation of intermediate voltage. Thus, the overshoot is prevented from occurring at the output end.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias generator suitable for a developing bias generator used in electrophotographic copying machines and printers.

[0002]

2. Description of the Related Art In recent electrophotographic copying machines and printers, a developing bias device for applying a high voltage between a developing sleeve and a photosensitive member to float toner on the surface of the photosensitive member is used to improve image quality. As a purpose, a ternary bias circuit that superimposes a DC bias on an AC waveform having three types of voltage values is used.

Therefore, in the conventional circuit, + V, -V
The desired three-valued bias waveform is obtained by periodically switching between the two types of voltage and the control of the intermediate value voltage between them.

A conventional circuit will be described below.

(Conventional Example 1) FIG. 7 shows a block diagram of a conventional circuit for outputting a ternary bias.

In the figure, 1 is a PWM circuit which compares a predetermined reference voltage with an input voltage and generates a pulse signal having a pulse width corresponding to the result, and 2 is the PW.
The drive circuit 3 which receives the pulse signal from the M circuit 1 and switches the transistor to drive the transformer generates a high voltage in response to the signal from the drive circuit 2, and smoothes the high voltage to obtain the first level. High voltage DC voltage (+
V) a step-up smoothing circuit (A) including a transformer, 4
Is the same as 3, and the high voltage DC voltage (-
V) generating step-up smoothing circuit (B), 5 is a voltage detection circuit which divides the output voltage of step-up smoothing circuit (A) 3 and is used as an input signal to PWM circuit 1, and 6 is step-up smoothing circuit (A) 3 A high voltage switch circuit (A) for switching the high voltage output voltage from the output coupling capacitor C to the output coupling capacitor C, and a high voltage switch circuit (B) for switching the high voltage output voltage from the step-up smoothing circuit (B) 4 to the output coupling capacitor C (B). ), 8
Is a voltage detection circuit (B) that divides the switched high-voltage output and outputs a low-voltage signal proportional to the high-voltage output signal, and 9 receives the signal from the voltage detection circuit (B) 8 and sets the voltage at the switch point to the first voltage. An intermediate voltage control circuit 10 for generating a signal for controlling to an intermediate level of the second high voltage level, 10 is an operation of each of the high voltage switch circuit (A) 6, the high voltage switch circuit (B) 7, and the intermediate voltage control circuit 9. A timing signal generating circuit for generating a timing signal for controlling timing, 11 receives an ON / OFF signal applied from the outside and transmits a switch ON signal of the high voltage switch circuit (A) 6 from the timing signal generating circuit 10. Similarly to the signal switch circuits (A) and 12 for ON / OFF control, the switch ON signal of the high voltage switch circuit (B) is turned ON / OF.
The signal switch circuits (B) and 13 for F control receive the signal from the intermediate voltage control circuit 9 and control the signal level from the signal switch circuit 11, or the signal switch circuit 1
1 is a signal control circuit for ON / OFF controlling the signal from 1.

With the circuit configuration described above, conventionally, the step-up smoothing circuit (A) 3 generates a positive high-voltage output and the step-up smoothing circuit (B) 4 generates a negative high-voltage output. First, in order to switch the positive high voltage output, a high voltage switch circuit (A) 6
Is turned on, then the high voltage switch circuit (A) 6 is turned off, and the high voltage switch circuit (B) 7 is turned on to switch the negative high voltage output, and then the high voltage switch circuit (B) 7 is turned off and the high voltage The switch circuit (A) is turned on again. At this time, the output voltage rises from a negative high voltage, but the voltage detection circuit (B) 8, the intermediate voltage control circuit 9,
By the action of the signal control circuit 13, the high voltage switch circuit (A) 6 is turned off when the output voltage becomes 0 [V]. By repeating the above, the ternary bias as shown in FIG. 7 is obtained at the switch point.

(Prior art example 2) Also, as shown in FIG.
Step-up smoothing circuit 3α for generating the voltage of this voltage (+2
V) is switched to the output coupling capacitor C, a high voltage switch circuit 6α and a 0 [V] switch circuit 7α that switches 0 [V] (ground level) are provided, and + 2V,
It is also possible to periodically repeat 0 [V] and the intermediate voltage + V to obtain the same ternary bias output as described above.

[0009]

In the developing bias device as described above, an overshoot occurs in the control of the intermediate value voltage, and the overshoot periodically occurs, so that streaks appear on the copied image. There is a problem that unevenness occurs.

The main causes of the overshoot are as follows.

In the error amplifier or comparator used for controlling the intermediate value voltage, the reference voltage which is the basis of its operation is influenced by the peripheral circuit and periodically fluctuates.

Delay in response of the error amplifier or comparator.

The present invention has been made in such a situation, and it is an object of the present invention to provide a bias generator in which overshoot does not occur at the output end during the generation period of the intermediate voltage. .

[0014]

In order to achieve the above object, in the present invention, a bias generator is provided with the following (1) to (1).
Configure as in (5).

(1) The first high voltage generating means for generating a positive high voltage, the second high voltage generating means for generating a negative high voltage, and the output of the first high voltage generating means. First to turn on or off at the output end of the bias generator
Switch means, second switch means for turning on or off the output of the second high voltage generating means to the output terminal, the first switch means and the second switch means are periodically turned on, A bias generation device comprising: a control means for turning off, which periodically generates an intermediate voltage between the positive high voltage, the negative high voltage, and both high voltages,
A bias generator which is connected to the output terminal and includes a clipping unit that clips the voltage of the output terminal at the ground level during the generation of the intermediate voltage.

(2) The clip detecting means for detecting that the voltage is clipped by the clipping means is provided, and the first switch means is turned off by the output of the clip detecting means. Bias generator.

(3) High voltage generating means for generating a high voltage corresponding to the peak-peak value of a required bias waveform, and a first for turning on or off the output of the high voltage generating means to the output terminal of the bias generating device. Switch means, second switch means for turning the ground voltage on or off to the output terminal, control means for periodically turning on and off the first switch means and the second switch means, A bias generator that periodically generates an intermediate voltage between the high voltage corresponding to the peak-peak value and the ground voltage, the bias generator being connected to the output terminal, and generating the intermediate voltage during the generation period. A bias generator comprising clipping means for clipping the voltage at the output end at the intermediate voltage level.

(4) The bias generator according to (3), wherein the clipping means includes a varistor for generating an intermediate voltage.

(5) The clip switch means for detecting that the voltage has been clipped by the clip means is provided, and the first switch means is turned off by the output of the clip detect means. Bias generator.

[0020]

With the configurations (1) and (2), a positive high voltage, a negative high voltage, and an intermediate voltage of both high voltages are periodically generated, and an output terminal is provided during the generation of the intermediate voltage. Is clipped to ground level. (3),
According to the configurations of (4) and (5), the high voltage corresponding to the peak-peak value of the required bias waveform, the ground voltage, and the intermediate voltage between the both are periodically generated, and during the generation period of the intermediate voltage. The output is clipped to an intermediate voltage level.

[0021]

EXAMPLES The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 is a block diagram of a "three-valued bias circuit" according to the first embodiment.

In the figure, reference numerals 6, 7, 10 and 12 denote the same circuits as in the conventional example, and therefore the description thereof is omitted here. In other words, 14 is a clipping circuit, which is the main part of this embodiment, and its operation is enabled according to the 0 timing signal from the timing signal generating circuit 10 so that the voltage at the switch point does not exceed the ground level. Performs clipping operation.

FIG. 2 is a timing chart showing the relationship between the output waveform and the timing signal for operating each circuit.

In the figure, (a) is an example of the output waveform by the circuit of this embodiment, and the broken line shown in the intermediate voltage section is the overshoot which is a problem of the present invention. (B) is a (+) timing signal for controlling ON / OFF of the high-voltage switch circuit (A) 6, and in this figure, the switch of the high-voltage switch circuit (A) 6 is switched depending on the “L” level of the signal. O
N, and the voltage at the switch point rises toward + V. Similarly, (c) is ON / OF of the high voltage switch circuit (B) 7.
This is a (-) timing signal for controlling F, and the switch of the high-voltage switch circuit (B) 7 is turned on by the "L" level of the signal, and the voltage at the switch point drops toward -V. Further, (d) is a 0 timing signal for enabling the clipping circuit 14, the clipping circuit 14 is enabled by the "L" level of the signal, and the voltage at the switch point is clipped at the ground level.

With the above circuit operation and timing signal, the output signal can maintain the intermediate voltage without causing the overshoot shown by the broken line.

FIG. 3 shows a detailed view of the clipping circuit.

In the figure, Tr1 is a transistor switch which is turned on / off according to a 0 timing signal,
In the configuration shown, the transistor Tr1 is turned off when the 0 timing signal is at "L" level. This turns on the transistor Tr2 in the figure,
The switch point and the ground are connected through the diode D1 and the resistor R1. Here, the diode D1 is a transistor T when the voltage at the switch point is negative.
This is to prevent a negative voltage from being applied to r2. On the other hand, the resistor R1 is set to an extremely small value and is provided to detect the current flowing from the switch point in the ground direction. That is, when a current flows through the resistor R1, the voltage on the emitter side of the transistor Tr2 rises, turning on the transistor Tr3. This allows the error amplifier IC
The voltage at the (-) input of 1 drops, and "H" appears at the current detection output.
Level output voltage is generated. This "H" level output is because the configuration of the error amplifier IC1 is a hysteresis comparator, and the circuit connected to the (-) input of the error amplifier IC1 is a circuit having a rising time constant. Hold for a certain period of time. Therefore,
The switch circuit (A) 6 is turned off by using this current detection signal.
If it is configured to cause F, it is possible to prevent the + V high-voltage output point from being connected to the ground.

(Second Embodiment) FIG. 4 is a block diagram of a "three-valued bias circuit" according to a second embodiment.

In the figure, the difference from the first embodiment is that the voltage switched by the high-voltage switch circuit (A) 6 is + 2V corresponding to the peak-peak value of the desired output waveform, and the switch circuit (B) switches. The voltage to be applied is at the ground level, that is, the 0 [V] switch circuit is used. In such a circuit configuration, the voltage to be clipped by the clipping circuit 14α is the intermediate voltage +
Therefore, the main part of the clipping circuit 14α is constructed as shown in FIGS.

First, in FIG. 5, a varistor Va of voltage + V is connected below the diode D1 in order to clip the voltage at the switch point to + V. 0 by this
Transistor Tr2 is turned on by inputting a timing signal
Then, the voltage at the switch point is clipped to + V.

Next, the clipping circuit of FIG. 6 will be described. In the circuit shown in the figure, when the 0 timing signal is input, the transistor Tr1 is turned off and the transistor Tr2 is turned on. However, in the circuit in this case, since the emitter current of the transistor Tr2 is made constant by the resistor R1 and the transistor Tr3, the collector voltage of the transistor Tr2 is maintained at a certain level or higher. This collector voltage is determined by a circuit including the floating power source E, resistors R2, R3, R4, transistors Tr3, Tr4, and diode D2, and is + V in the figure. That is,
The voltage + 2V is divided by the resistors R2 and R3 to generate a voltage + V, which is input to the base of the transistor Tr4. The floating power supply E is connected to the collector of the transistor Tr4, and the resistor R4 is connected to the emitter between the floating power supply E and the ground side. By this connection, the emitter voltage of the transistor Tr4 becomes + V (more accurately, + V-Vbe (Tr4)), and this voltage is supplied to the base of the transistor Tr5. Transistor Tr
Since the voltage + 2V is supplied to the collector of 5 (however, resistance R5≈0), + V is applied to the emitter (more precisely, + V).
A voltage of V-Vbe (Tr4) -Vbe (Tr5)) appears and is sent to the collector of the transistor Tr2 through the diode D2. Here, the transistor Tr5 is a high-voltage transistor, and generally has a low current amplification factor hfe, so that the floating power source E, the transistor Tr4, and the resistor R4.
The circuit of 4 makes it possible to earn the base current of the transistor Tr5. Therefore, when such a circuit is not necessary, a circuit having the same function can be configured only by the resistors R2 and R3 and the transistor Tr5. Further, when the transistor Tr2 is in an OFF state, the collector voltage of the diode D2 rises in the diode D2, and
It is connected so as not to destroy the.

On the other hand, the circuit of the resistors R5 and R6 and the capacitor C1 is a circuit for detecting a rapid change in the current flowing through the resistor R5, and it is possible to detect that a current has flowed through the diode D1. If the switch circuit (A) 6α of + 2V is turned off by using
It is possible to prevent unnecessary connection between the voltage point of 2V and the voltage point of + V.

[0034]

As described above, according to the present invention,
Overshoot does not occur at the output end during the intermediate voltage generation period. According to the second and fifth aspects of the invention, the high voltage generating means is not short-circuited by the clipping means during the intermediate voltage generation period.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a timing chart of the first embodiment.

FIG. 3 is a circuit diagram of a clipping circuit 14.

FIG. 4 is a block diagram of a second embodiment.

FIG. 5 is an explanatory diagram of an example of a clipping circuit 14α.

FIG. 6 is an explanatory diagram of an example of a clipping circuit 14α.

FIG. 7 is a block diagram of Conventional Example 1.

FIG. 8 is a block diagram of Conventional Example 2.

[Explanation of symbols]

 6 High-voltage switch circuit (A) 7 High-voltage switch circuit (B) 10 Timing signal generation circuit 14 Clipping circuit

Claims (5)

[Claims] 1. A first high voltage generating means for generating a positive high voltage, a second high voltage generating means for generating a negative high voltage, and an output of the first high voltage generating means for the bias. First switch means for turning on or off the output terminal of the generator; second switch means for turning on or off the output of the second high voltage generating means to the output terminal; and the first switch means. A bias generator that includes a control unit that periodically turns on and off the second switch unit and that periodically generates an intermediate voltage between the positive high voltage, the negative high voltage, and both high voltages. A bias generator connected to the output terminal, and for clipping the voltage of the output terminal at the ground level during the generation of the intermediate voltage. 2. A clip detecting means for detecting that the voltage is clipped by the clip means, and the first switch means is turned off by the output of the clip detecting means. 1. The bias generator according to 1. 3. A high voltage generating means for generating a high voltage corresponding to a peak-peak value of a required bias waveform, and a first for turning on or off an output of the high voltage generating means to an output terminal of the bias generating device. A switch means, a second switch means for turning on or off a ground voltage at the output terminal, a control means for periodically turning on and off the first switch means and the second switch means, A bias generator that periodically generates an intermediate voltage between the high voltage corresponding to the peak value and the ground voltage, and is connected to the output terminal, and outputs the intermediate voltage during the generation period. A bias generator comprising clipping means for clipping an end voltage at the intermediate voltage level. 4. The bias generator according to claim 3, wherein the clip means includes a varistor that generates an intermediate voltage. 5. A clip detection means for detecting that the voltage is clipped by the clipping means is provided, and the first switch means is turned off by the output of the clip detection means. 3. The bias generator according to item 3.