JPH07162813A - Decoder for television signal - Google Patents

Abstract

PURPOSE:To obtain a high-definition image prevented from distortion in a picture out of synchronism by providing a processing part for detecting the discontinuity of synchronizing signals in accordance with the switching of a call originating station and for exchanging the discontinuous distorted video signals with arbitrary exchange video signals set in advance. CONSTITUTION:At the time of a normal operation, a switching signal from a frame pulse discontinuity detection part 32 for frame pulses is set at an L level '0'. When the detection part 32 detects the discontinuity of frame pulses, the switching signal is turned to an H level '1' and corresponding to this H level signal, a selector 21 is switched to select the output of a register 23. When a power source is turned on, at the same time, the exchange video signal is read from a non-volatile memory 22 and set to the register 23 by a CPU 16. Accordingly, the exchange video signal set to the register 23 is outputted to a video signal processing part at a following step. Therefore, even when the out-of-synchronism of the frame pulse is caused, the exchange video signal is passed through the video signal processing part at the following step or an inverse matrix circuit and displayed on a display device and the image distortion is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE type television signal (M) which is one of the high definition satellite broadcasting systems.
The present invention relates to a television signal decoder such as a MUSE decoder that decodes USE signals).

[0002] In recent years, with the progress of television technology, MUSE (Multip
The le Sub-Nyquist Sampling Encording) method has been developed. In this MUSE method, the sampling clock is not transmitted from the encoder side, and the clock is reproduced using the synchronization signal on the MUSE decoder side.

MUS adopting such MUSE system
In the E decoder, further improvement in image quality and the like is demanded.

[0004]

2. Description of the Related Art FIGS. 11 and 12 are views showing a conventional example, in which 1 is a television receiver,
2 is a BS antenna, 3 is a BS tuner, 4 is a MUSE decoder, 5 is an audio device, 6 is a display device, 7 is an analog / digital converter (hereinafter referred to as "ADC"), 8 is a signal separation circuit, and 9 is an audio decoder. Reference numeral 10 denotes a video signal processing unit, 12 denotes an inverse matrix circuit, and 13 denotes a digital / analog converter (hereinafter referred to as "DAC") unit. Hereinafter, an example of the television receiver using the MUSE decoder will be described.

§1: Description of television receiver ...
See FIG. 11. FIG. 11 is a block diagram of a conventional television receiver. The outline of a conventional television image receiving device will be described below with reference to FIG.

As shown in the figure, this television receiver 1 is provided with a BS tuner 3 connected to a BS (BS: Broadcasting Satellite) antenna 2, a MUSE decoder 4, an audio device 5, a display device 6 and the like. is there.

Further, the MUSE decoder 4 has an AD
A C7, a signal separation circuit 8, an audio decoder 9, a video signal processing unit 10, an inverse matrix circuit 12, a DAC unit 13 and the like are provided. Functions and the like of the above-mentioned respective parts are as follows.

(1): The BS tuner 3 is the BS antenna 2
Of the output signal of the converter (output signal of the converter)
It outputs the SE signal. (2): The MUSE decoder 4 inputs the MUSE signal output from the BS tuner 3 and performs a decoding process.

(3): The audio device 5 has an amplifier, a speaker and the like inside, and inputs the audio signal decoded by the audio decoder 9 and converts it into audio. (4): The display device 6 inputs the red (R), green (G), and blue (B) signals output from the video signal processing unit 10 to display a video on the display.

(5): The ADC 7 converts the MUSE signal (analog signal) output from the BS tuner 3 into a digital signal. (6): The signal separation circuit 8 separates the audio signal from the output signal (digitized MUSE signal) of the ADC 7.

(7): The audio decoder 9 includes a signal separation circuit 8
The audio signal separated by is decoded. (8): The video signal processing unit 10 inputs the output signal of the ADC 7 (digitized MUSE signal) and processes the video signal.

(9): The inverse matrix circuit 12 converts the luminance signal (Y) and the color difference signals (RY, BY) output from the video signal processing unit 10 into red (R) and green ( G) and blue (B) signals are converted.

(10): The DAC section 13 converts each signal converted by the inverse matrix circuit 12 into a digital signal. §2: Description of MUSE signal format--see FIG. 12 FIG. 12 is a diagram showing a MUSE signal format.
The outline of the MUSE signal will be described below with reference to FIG.

As shown in the figure, the MUSE signal includes a control signal, a sync signal, a VIT signal (transmission path equivalent signal), a voice / voice signal in addition to a Y video (luminance signal) and a C video (color signal). Independent data is multiplexed in each blanking period.

The "HD" inserted in each line is
The "period" is an area to which the horizontal synchronizing signal is assigned. Further, the frame pulse area (2 lines) is an area in which a frame pulse (signal for establishing synchronization) is inserted.

In this MUSE format, the sample number for each line (horizontal direction) is 1 to 480 (1 line = 480 clocks), and the line number (vertical direction) is 1 to 1125 (scan number = 1125 lines). Has become.

§3: Outline of Operation of Television Receiver The outline of operation of the television receiver is as follows. The MUSE decoder 4 reproduces a sync signal from the MUSE signal input from the BS tuner 3. And
The image is reproduced according to the timing of this synchronization signal.
In this case, the sync signal is reproduced with reference to the frame pulse sent in the first two lines of each frame.

First, the ADC 7 converts the input MUSE signal (analog signal) into a digital signal. After that, in the signal separation circuit 8, the MUSE converted by the ADC 7
The audio signal is separated from the signal, and the audio signal is decoded by the audio decoder 9 and output to the audio device 5. With this processing unit, a voice is output from the voice device 5 (a sound is output from a speaker).

Further, in the video signal processing section 10, the ADC 7
The video signal processing is performed by inputting the converted MUSE signal, and the luminance signal (Y) and the color difference signals (RY, BY) are output to the inverse matrix circuit 12.

Thereafter, the inverse matrix circuit 12 converts the luminance signal (Y) and the color difference signals (RY, BY) into red (R), green (G) and blue (B) signals. And DAC
It is output to the unit 13.

The DAC section 13 converts each of the red (R), green (G) and blue (B) signals (digital signals) into an analog signal and outputs it to the display device 6. In the display device 6, the red (R), green (G), and blue (B) signals output from the DAC unit 13 are input and displayed (display an image) on the display.

[0022]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. : For example, if switching is performed without performing synchronization at the time of switching the station, the synchronization signal disappears and the synchronization is lost on the MUSE decoder side. In this case, the MUSE decoder performs synchronization after switching, but the video on the display screen is disturbed during that period.

As described above, when the image is disturbed due to the out-of-sync, the quality of the displayed image is deteriorated, and a high-quality image suitable for a high-definition television receiver or the like cannot be obtained.

It is an object of the present invention to solve such a conventional problem, to avoid the image disturbance due to the out-of-synchronization at the time of switching the station, and to always obtain a high quality display image. To do.

[0025]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the same parts as those in FIGS. 11 and 12 are designated by the same reference numerals. Further, 16 is a CPU (central processing unit), 17 is a video replacement processing section, 21 is a selector, 2
2 is a non-volatile memory, 23 is a register, and 32 is a frame pulse discontinuity detection unit.

The present invention has the following constitution to solve the above problems. : In a television signal decoder for decoding a television signal, from the input television signal,
A means for detecting the discontinuity of the synchronization signal (dissynchronization) due to switching of the station and the like, and a video signal disturbed by the discontinuity of the synchronization signal based on the discontinuity detection signal of the synchronization signal by the means,
A television signal decoder provided with a video replacement processing unit 17 that replaces a preset arbitrary replacement video signal.

In the configuration, as a means for detecting the discontinuity of the synchronizing signal, a frame pulse discontinuity detecting section 32 for detecting the discontinuity of the frame pulse from the input television signal is used, and the frame pulse discontinuity detecting section is used. A television signal decoder that outputs the frame pulse discontinuity detection signal by 32 to the video replacement processing unit 17 as a switching signal at the time of video replacement.

In the configuration, the register 23 for setting the replacement video signal in the video replacement processing section 17
And a selector 21 for replacing the video signal disturbed by the discontinuity of the sync signal by switching based on the sync signal discontinuity detection signal with the replacement video signal set in the register 23.

An analog / digital converter for converting the input television signal into a digital signal,
A video signal processing unit for inputting a digital signal converted by the analog / digital converter, performing video signal processing, and outputting a luminance signal (Y) and a color difference signal (RY, BY), and the video signal. An inverse matrix circuit that inputs the luminance signal (Y) and the color difference signals (RY, BY) output from the processing unit and converts the signals into red, green, and blue (R, G, B) signals. And a frame pulse discontinuity detection unit 32 for detecting a discontinuity of frame pulses due to switching of the station from the input television signal, and the following stage of the analog / digital converter. , A video difference for replacing the video signal disturbed by the discontinuity of the frame pulse with a preset arbitrary replacement video signal based on the discontinuity detection signal of the frame pulse Changing the processing unit 17 is provided, the video signal replacement by the image replacement processing unit 17, the television signal decoder which enables output to the video signal processing unit.

An analog / digital converter for converting the input television signal into a digital signal,
A video signal processing unit for inputting a digital signal converted by the analog / digital converter, performing video signal processing, and outputting a luminance signal (Y) and a color difference signal (RY, BY), and the video signal. An inverse matrix circuit that inputs the luminance signal (Y) and the color difference signals (RY, BY) output from the processing unit and converts the signals into red, green, and blue (R, G, B) signals. In a television signal decoder having, a frame pulse discontinuity detection unit 32 for detecting a discontinuity of frame pulses due to switching of a station from an inputted television signal is provided, and in the preceding stage of the inverse matrix circuit, Based on the discontinuity detection signal of the frame pulse, a frame pulse is generated for each of the luminance signal (Y) and the color difference signals (RY, BY) output from the video signal processing unit. Image replacement processing portion 17 for the signal disturbed by continuous, replacing in any color video signal
Decoder for television signal provided with.

An analog / digital converter for converting the input television signal into a digital signal,
A video signal processing unit for inputting a digital signal converted by the analog / digital converter, performing video signal processing, and outputting a luminance signal (Y) and a color difference signal (RY, BY), and the video signal. An inverse matrix circuit that inputs the luminance signal (Y) and the color difference signals (RY, BY) output from the processing unit and converts the signals into red, green, and blue (R, G, B) signals. In a television signal decoder having, a frame pulse discontinuity detection unit 32 for detecting a discontinuity of frame pulses due to switching between stations is provided from an input television signal, and at the subsequent stage of the inverse matrix circuit, Based on the discontinuity detection signal of the frame pulse, red output from the inverse matrix circuit,
A television signal decoder provided with a video replacement processing section 17 for replacing the green and blue (R, G, B) signals disturbed by frame pulse discontinuity with arbitrary color video signals.

[0032]

The operation of the present invention based on the above construction will be described with reference to FIG. (1): The operation when the video replacement processing unit 17 is provided in the subsequent stage of the ADC is as follows.

When the power is turned on, first, the CPU 16
Reads the replacement video signal stored in the nonvolatile memory 22 and sets it in the register 23. And
Start normal operation.

In the normal operation, when the frame pulse is continuous and there is no loss of synchronization, the switching signal (frame pulse discontinuity detection signal) output from the frame pulse discontinuity detection section 32 becomes low level "0". ing.
In this state, the selector 21 selects the output of the ADC in the previous stage.

That is, in the video replacement processing section 17,
The output of the ADC in the front stage is output as it is to the video signal processing unit in the rear stage. However, when the frame pulse discontinuity detector 32 detects the discontinuity of the frame pulses,
The switching signal becomes a high level "1". The selector 21 is switched to select the output of the register 23 by this high-level switching signal.

Then, the replacement video signal set in the register 23 is output to the video signal processing unit in the subsequent stage. By this processing, even if the frame pulse is out of synchronization, the replacement video signal is output to the display device via the video signal processing unit in the subsequent stage, the inverse matrix circuit, etc., and displayed. Disturbance can be avoided.

(2): The operation when the video replacement processing section 17 is provided in the preceding stage of the inverse matrix circuit is as follows. When the power is turned on, first, the CPU 16 reads out the three replacement video signals stored in the non-volatile memory 22 and sets them in the three registers of the register 23. Then, the normal operation is started.

In the normal operation, when the frame pulse is continuous and there is no loss of synchronization, the switching signal (frame pulse discontinuity detection signal) output from the frame pulse discontinuity detection section 32 becomes low level "0". ing.

In this state, the selector 21 selects the output of the video signal processing section in the preceding stage. That is, the output (Y, RY, BY) of the video signal processing unit in the previous stage is directly output to the inverse matrix circuit 12.

However, the frame pulse discontinuity detector 32
Thus, when the discontinuity of the frame pulse is detected, the switching signal becomes the high level "1". The selector 21 causes the register 23 to operate in response to the high-level switching signal.
It is possible to switch to select each register output of.

Then, the video replacement processing section 17 outputs the three replacement video signals set in the register 23 to the inverse matrix circuit 12 in the subsequent stage. By this processing, even if the frame pulse is out of synchronization, the replacement video signal is output to the display device through the inverse matrix circuit, and thus the video disturbed on the screen is replaced with an arbitrary color video for display. can do.

(3): The operation when the video replacement processing section 17 is provided in the subsequent stage of the inverse matrix circuit is as follows. When the power is turned on, first, the CPU 16 reads out the three replacement video signals stored in the non-volatile memory 22 and sets them in the three registers of the register 23. Then, the normal operation is started.

In the normal operation, when the frame pulse is continuous and there is no loss of synchronism, the switching signal (frame pulse discontinuity detection signal) output from the frame pulse discontinuity detection section 32 becomes low level "0". ing.

In this state, the selector 21 selects the output of the preceding inverse matrix circuit. That is, in the video signal processing unit 10, the outputs (R, G,
B) is output as it is to the subsequent stage (DAC section).

However, the frame pulse discontinuity detector 32
When the discontinuous state of the frame pulse is detected,
The switching signal becomes a high level "1". The selector 21 is switched to select each register output of the register 23 by this high level switching signal.

Then, the video replacement processing section 17 outputs the three replacement video signals set in the register 23 to the subsequent stage (DAC section). By the above process,
Even if the frame pulse is out of synchronization, the replacement video signal can be output to the display device, and the video disturbed on the screen can be replaced with an arbitrary color video for display.

(4): As described above, it is possible to avoid the image disturbance due to the out-of-synchronization at the time of switching the station, and always obtain a high-quality display image.

[0048]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 10 are views showing an embodiment of the present invention. In FIGS. 2 to 10, the same parts as those in FIGS. 1, 11 and 12 are designated by the same reference numerals.

Further, 18 is a clock reproduction / synchronization signal processing unit, 19 is an audio signal processing unit, 25 is a clock reproduction unit, 2
6 is a frame pulse detection unit, 27 is a control unit, 28 is a synchronization counter unit, 29 is a frame counter, 30 is a horizontal counter, 31 is a vertical counter, 32 is a frame pulse discontinuity detection unit, 33 is a counter value decoding unit, and 34 is a counter value decoding unit. Is a frame pulse position comparison unit, and 35 is a set-reset type flip-flop (hereinafter referred to as "FF").

An example in which the MUSE decoder is used in a television receiver will be described below. (Explanation of First Embodiment) FIGS. 2 to 6 are views showing a first embodiment of the present invention. Hereinafter, the first embodiment will be described with reference to FIGS.

§1: Structure explanation of television receiver
.. see FIG. 2. FIG. 2 is a block diagram of the television receiver of the first embodiment. The configuration of the television receiver will be described below with reference to FIG. The television receiver shown is
1 is an example of a high-definition television image receiving apparatus provided with a MUSE decoder for decoding a high-definition MUSE signal.

As shown in the figure, the television receiver 1 has BS tuners 3 and M connected to a BS antenna 2.
A USE decoder 4, an audio device 5, a display device 6 and the like are provided.

Further, the MUSE decoder 4 has an AD
C7, video signal processing unit 10, inverse matrix circuit 12, D
AC unit 13, CPU 16, video replacement processing unit 17, clock reproduction / synchronization signal processing unit 18, audio signal processing unit 19
Etc. are provided.

Further, the audio signal processing section 19 is provided with a signal separation circuit 8 and an audio decoder 9, and the DAC section 1
3 has three DACs. Functions and the like of the above-mentioned respective parts are as follows.

(1): The MUSE decoder 4 inputs the MUSE signal output from the BS tuner 3 and performs a decoding process. In this MUSE decoder 4,
The audio signal processing and the video signal processing are separately performed to output the audio signal to the audio device 5 and the R, G, B video signals to the display device 6.

(2): Clock recovery / synchronization signal processing unit 18
Is for inputting the MUSE signal (digital signal) converted by the ADC 7 and performing clock reproduction processing and synchronization signal processing.

In this synchronization signal processing, frame pulse discontinuity detection processing is performed, and the signal of the detection result (frame pulse discontinuity detection signal) is output to the video replacement processing section 17 as a selector switching signal. Further, the reproduced clock is supplied to each unit, and the synchronization signal is output to the display device 6.

(3): The video replacement processing section 17 uses the ADC
The MUSE signal (digital signal) converted by the ADC 7 is connected to the subsequent stage to perform processing. In the video replacement processing unit 17, when the clock reproduction / synchronization signal processing unit 18 detects a discontinuity (out of synchronization) of frame pulses, a replacement video signal (for example, a gray level video) that is internally set in advance. Signal) instead of the MUSE signal, and the video signal is replaced by the video signal processing unit 1.
It outputs to 0.

(4): The CPU 16 controls the entire MUSE decoder. The rest of the configuration is the same as that of the conventional example, and the description thereof is omitted. §2: Description of the operation of the television receiver ... See FIG. 2 The operation of the television receiver is as follows. B
The S tuner 3 extracts the MUSE signal from the output signal of the BS antenna 2 (the output signal of the converter), and outputs the MUSE signal to the MUSE decoder 4.

The MUSE decoder 4 inputs the MUSE signal and performs a decoding process. In this case, first, the input MUSE signal is converted into a digital signal by the ADC 7 and output to the audio signal processing unit 19, the clock reproduction / synchronization signal processing unit 18, the video replacement processing unit 17, and the like.

In the audio signal processing section 19, first, the signal separation circuit 8 separates the audio signal from the input MUSE signal, and the audio decoder 9 decodes the separated audio signal and outputs it to the audio device 5.

Further, the clock recovery / synchronization signal processing section 18
Then, the clock reproduction processing is performed, the reproduced clock is supplied to each unit, and the synchronization signal processing is performed. In this synchronization signal processing, a discontinuous state (out-of-sync) of the frame pulse due to switching of the station or the like is detected.

When the frame pulse discontinuity is detected, the detection signal is output to the video replacement processing section 17 as a switching signal for a selector (details will be described later).

In the video replacement processing section 17, normally,
The MUSE signal output from the ADC 7 is directly output to the video signal processing unit 10, but when the switching signal is output from the clock reproduction / synchronization signal processing unit 18, the MUSE signal is output.
As an alternative to the USE signal, a replacement video signal (for example, a gray level video signal) preset inside is output to the video signal processing unit 10 (the video signal is replaced).

In the video signal processing unit 10, normally, the MUSE signal output from the video replacement processing unit 17 is input and various video signal processing (non-linear processing, moving image processing, still image processing, mixing processing, etc.) is performed. Then, the Y, RY, and BY signals are output to the inverse matrix circuit 12.

However, in the video signal processing unit 10, when the replacement video signal is input from the video replacement processing unit 17, the video signal corresponding to that signal is output to the inverse matrix circuit 12.

In the inverse matrix circuit 12, the Y, RY, and BY signals from the video signal processing unit 10 are input and converted into R, G, and B signals (digital signals), and DA
Output to C section 13. In the DAC unit 13, the R, G,
Each signal of B is converted into an analog signal and output to the display device 6.

In the display device 6, the R, G and B signals output from the DAC unit 13 and the synchronization signal from the clock reproduction / synchronization signal processing unit 18 are input to display an image on the display.

In this case, when the frame pulse becomes discontinuous due to switching of the station or the like, an image (for example, a gray level image) by the "replacement image signal" is displayed.

§3: Description of video replacement processing unit--see FIG. 3 FIG. 3 is a block diagram of the video replacement processing unit. As shown in the figure, the video replacement processing unit 17 is provided with a selector 21, a register 23, a non-volatile memory 22, and the like. Functions and the like of the above-mentioned respective parts are as follows.

(1): The non-volatile memory 22 is a memory for presetting (storing data) the replacement video signal. The replacement video signal may be any video signal, but for example, a gray level (512 level) video signal is used.

(2): The register 23 is the nonvolatile memory 2
2 is a register for setting the replacement video signal stored in 2. For example, when the power is turned on, the CPU 16
Is to read the replacement video signal from the non-volatile memory 22, set it in the register 23, and output the set signal to the selector 21.

(3): The selector 21 follows the AD signal according to the switching signal (low level "0" / high level "1" signal) output from the clock recovery / synchronization signal processing unit 18.
The selection operation of the output of C7 (MUSE signal) and the output of the register 23 (replacement video signal) is performed, and one of the selected signals is output to the video signal processing unit 10.

In this case, the selector 21 selects the output (MUSE signal) of the ADC 7 during the normal operation,
When the frame pulse becomes discontinuous (out of sync),
The output of the register 23 is selected by the switching signal from the clock reproduction / synchronization signal processing unit 18.

The operation of the video replacement processing section 17 is as follows. When the power of the television receiver is turned on, the CPU 16 first reads the replacement video signal stored in the non-volatile memory 22 and sets it in the register 23. Then, the normal operation is started.

In the normal operation, when the frame pulse is continuous and there is no loss of synchronization, the switching signal (frame pulse discontinuity detection signal) output from the clock recovery / synchronization signal processing unit 18 is at low level "0". Has become. In this state, the selector 21 selects the output of the ADC 7. That is, the output (MUSE signal) of the ADC 7 is output to the video signal processing unit 10 as it is.

However, the clock recovery / synchronization signal processing unit 1
When the discontinuous state of the frame pulse is detected by 8, the "switching signal" becomes the high level "1".
The selector 21 is switched to select the output of the register 23 by this high-level switching signal.

Then, the replacement video signal set in the register 23 is output to the video signal processing section 10. By this processing, even if the frame pulse is out of synchronization, the replacement video signal is output to the video signal processing unit 10,
It is possible to avoid image distortion on the screen.

§4: Description of Clock Recovery / Synchronization Signal Processing Unit ... See FIG. 4 FIG. 4 is a block diagram of the clock recovery / synchronization signal processing unit. As shown, the clock recovery / synchronization signal processing unit 18
Includes a clock regenerator 25 and a frame pulse detector 2
6, a control unit 27, a synchronization counter unit 28, a frame pulse discontinuity detection unit 32, and the like are provided.

Further, the synchronous counter unit 28 is provided with a frame counter 29, a horizontal counter 30, and a vertical counter 31, and the frame pulse discontinuity detecting unit 32 is provided with a counter value decoding unit 33, a frame pulse position comparing unit 34, F.
An F (SR type flip-flop) 35 and the like are provided. Functions and the like of the above-mentioned respective parts are as follows.

(1): The clock reproducing section 25 reproduces a clock from the MUSE signal converted by the ADC 7. (2): The frame pulse detector 26 detects a frame pulse from the MUSE signal converted by the ADC 7. When the frame pulse detector 26 detects a frame pulse, it outputs a high level signal “1”,
Low level signal "0" when no frame pulse is detected
Is output.

In the frame pulse detection processing of the frame pulse detection unit 26, for example, inversion every 4 clocks and every line (low level “0” and high level “1”).
Inversion) continues 35 times and there is a period of 16 clock low level “0”, 1 clock high level “1”
Output pulse.

(3): The control unit 27 controls the clock recovery / synchronization signal processing unit 18 by various means, for example, the synchronization counter unit 2
8 and the frame pulse discontinuity detection unit 32 is controlled. The control unit 27 inputs the frame pulse detected by the frame pulse detection unit 26 and performs the following control.

That is, the control unit 27 first resets each counter of the synchronization counter unit 28 with the preceding frame pulse. After that, the position of the frame pulse is predicted from the counter values of the horizontal counter 30 and the vertical counter 31, and if it coincides with the output pulse of the previous stage, the horizontal counter 30 and the vertical counter 31 remain unchanged and the frame counter 29 is reset.

If they do not match, the frame counter 29 is counted up (counter value is +1) and 8
If the frame counts do not match, the frame counter 29, the horizontal counter 30, and the vertical counter 31 are reset.

(4): The synchronization counter unit 28 includes the control unit 27
The clock is counted under the control of (1) to create various timing signals (horizontal synchronization, vertical synchronization, etc.). (5): The frame counter 29 counts the number of frames.

(6): The horizontal counter 30 counts the number of clocks in the horizontal direction (the number of clocks for each line). In addition, in this horizontal counter 30, 1 to 4
When the clock up to 80 is counted, it is reset to the initial value.

That is, the count value = 0 at the first position of each line, and then the clocks are sequentially counted. The current position (sample number) in the horizontal direction can be confirmed from this count value.

(7): The vertical counter 31 counts the number of lines. The vertical counter 31 increments (+1) after the horizontal counter 30 counts clocks up to 480, and sequentially counts the number of lines in the vertical direction (1 to 1125). The current position (line number) in the vertical direction can be confirmed from this counter value.

(8): Frame pulse discontinuity detector 32
Under the control of the control unit 27, is for detecting a discontinuous state of frame pulses (out-of-synchronization state occurring at the time of switching stations, etc.).

(9): The counter value decoding unit 33 obtains the current position (current scanning position) by decoding the output signal (counter value) of the synchronous counter unit 28,
The position where the frame pulse exists is predicted based on the current position information. Then, when the predicted position where the frame pulse is present is reached, the high level signal "1" is output.

In this case, the current value in the vertical direction (line number) is known from the counter value of the vertical counter 31, and the current position in the horizontal direction (sample number) is known from the counter value of the horizontal counter 30. Therefore, the position where the frame pulse exists can be predicted based on each counter value.

(10): The frame pulse position comparison unit 34
The position of the frame pulse predicted by the counter value decoding unit 33 is compared with the position of the frame pulse detected by the frame pulse detecting unit 26.

In this case, the counter value decoding unit 33 outputs the high level signal "1" at the predicted position of the frame pulse.
Since the frame pulse position comparing section 34 outputs the high level signal “1” and the frame pulse detecting section 26,
Detection signal (which becomes a high level signal “1” when a frame pulse is detected).

When the frame pulse detector 26 detects a frame pulse at the position (output signal = "1") predicted by the counter value decoder 33 (output signal of the frame pulse detector 26 = high level "1"). )), It is determined that they match (a frame pulse exists at the predicted position),
If the frame pulse detector 26 does not detect a frame pulse at the predicted position (the frame pulse detector 2
6 output signal = low level “0”), it is determined that the two do not match (no frame pulse exists at the predicted position).

The frame pulse position comparison section 34 outputs a high level signal "1" to the set terminal (S) of the FF 35 when the both do not match by the above processing, and resets the FF 35 when both match. The high level signal "1" is output to the terminal (R).

(11): The FF (flip-flop) 35 is
The set / reset is performed according to the position comparison result (match, mismatch) of the frame pulse position comparison unit 34. That is, if the position comparison result of the frame pulse position comparison unit 34 is “match”, the FF 35 is reset (Q output = 0), and if “mismatch”, the FF 35 is set (Q output = 1).

The Q output output from the FF 35 is a frame pulse discontinuity detection signal, and this signal is output to the selector 21 as a "switching signal". §5: Description of frame pulse discontinuity detection process ... FIG.
Reference FIG. 5 is a flowchart of frame pulse discontinuity detection processing. Hereinafter, the frame pulse discontinuity detection process by the clock recovery / synchronization signal processing unit 18 will be described with reference to FIG.

In the frame pulse detector 26, the ADC 7
When a frame pulse is detected from the output signal (MUSE signal) of the controller, and the frame pulse is detected (S1), the frame pulse detection signal (high level signal "1") is output to the control unit 2.
7 and the frame pulse discontinuity detector 32.

The control section 27 first resets each counter of the synchronization counter section 28 by the preceding frame pulse (S2). After that, each counter of the synchronous counter unit 28 sequentially counts.

Then, in the counter value decoding section 33,
The current line and sample (current position information) are obtained by inputting and decoding the counter value of the synchronization counter unit 28 (S3).

That is, the horizontal counter 30 counts clocks (1 to 480), and the counter value indicates which position (sample number) of each line. The vertical counter 31 counts the number of lines, and the counter value indicates the line number. Further, the counter value of the frame counter 29 indicates the number of frames.

Therefore, the current position can be known by decoding the counter values. Therefore, the counter value decoding unit 33 predicts the position of the frame pulse from the decoding information.

Then, the frame pulse position comparison unit 34 performs frame pulse position comparison processing based on the information decoded by the counter value decoding unit 33, and the frame pulse detected by the frame pulse detection unit 26 is at the predicted position. Or not exists.

That is, the frame pulse position comparison unit 34
Then, when the predicted position of the frame pulse is reached (S4), it is determined whether or not the frame pulse exists at that position (S5).

As a result, if there is no frame pulse at the predicted position (mismatch), the frame pulse position comparison unit 3
4 sets the discontinuous signal to the FF 35 (S6). If the frame pulse exists at the predicted position (coincidence), the discontinuous signal is reset to the FF 35 (S7), and the process from S3 is repeated.

In the FF 35, when the set signal is input, the Q output becomes high level (Q = 1), and when the reset signal is input, the Q output becomes low level (Q = 0). Then, the Q output of the FF 35 is output to the selector 21 as the “switching signal”.

§6: Description of operation based on timing chart--see FIG. 6 FIG. 6 is a time chart when frame pulse discontinuity is detected. Hereinafter, the processing when the frame pulse discontinuity is detected in the television receiver will be described with reference to FIG.

Since the MUSE signal normally sent has the same video and sync signal, the video can be displayed normally except that the input video is switched or cannot be reproduced due to noise or the like.

However, when video is sent from a plurality of broadcast transmission stations due to diversification of broadcast video, video switching is performed without completely matching frames (out of synchronization) (see “Before switching” in the figure). , "" After switching ").

In this case, since the video is reproduced at the new timing after the frame pulse after the switching is detected (refer to the arrow of "new timing detection" in the figure), the disordered video is displayed until that time. (“Disturbed video period” in the figure)
See).

In order to shorten the disturbed image display period,
When it detects that the frame pulse has become discontinuous as described above (refer to the arrow of "Discontinuity detection" in the figure), the video can be played at new timing (refer to the arrow of "Start new timing" in the figure) For a constant brightness level (for example,
Replace with a gray level video signal (see "Replacement period" in the figure).

(Explanation of Second Embodiment) FIGS. 7 and 8 show a second embodiment.
It is the figure which showed. The second embodiment will be described below with reference to FIGS. 7 and 8.

§1: Description of configuration of television receiver
.. see FIG. 7. FIG. 7 is a block diagram of the television receiver of the second embodiment. The second embodiment is an example in which the video replacement processing unit 17 is inserted in the preceding stage of the inverse matrix circuit 12.

As shown in the figure, the television receiver 1 includes a BS tuner 3 and a MUSE as in the first embodiment.
A decoder 4, an audio device 5, a display device 6 and the like are provided.

Further, the MUSE decoder 4 has an AD
C7, video signal processing unit 10, inverse matrix circuit 12, D
AC unit 13, CPU 16, video replacement processing unit 17, clock reproduction / synchronization signal processing unit 18, audio signal processing unit 19
Etc. are provided. Further, the audio signal processing unit 19 has
The signal separation circuit 8 and the audio decoder 9 are provided, and the DAC
The part 13 is provided with three DACs.

In this case, the output of the ADC 7 is directly connected to the video signal processing unit 10, and the video replacement processing unit 17 is connected to the output of the video signal processing unit 10. Further, the inverse matrix circuit 12 is connected to the output of the video replacement processing section 17. The rest of the configuration is the same as that of the first embodiment, so the description is omitted.

§2: Description of Video Replacement Processing Unit--See FIG. 8 FIG. 8 is a block diagram of a video replacement processing unit according to the second embodiment. Hereinafter, based on FIG. 8, the video replacement processing unit 17
Will be described.

As shown in the figure, this video replacement processing section 1
7, the nonvolatile memory 2 is the same as in the first embodiment.
2, a register 23 and a selector 21 are provided. in this case,
The register 23 has a Y signal (luminance signal), an RY signal (color difference signal), and a BY output from the video signal processing unit 10.
Three registers are provided corresponding to signals (color difference signals), and the selector 21 is also provided with three selectors corresponding to the Y signal, RY signal, and BY signal.

Further, the non-volatile memory 22 stores the data of the "replacement video signal" in advance. In this case as well, the data (Y, Y, Y) corresponding to the Y signal, the RY signal and the BY signal is stored. R-Y and B-Y are set to arbitrary values).

The operation of the video replacement processing section 17 is as follows. When the power of the television receiver is turned on, first, the CPU 16 reads out the three replacement video signals stored in the nonvolatile memory 22 and sets them in the three registers of the register 23. Then, the normal operation is started.

In the normal operation, when the frame pulses are continuous and there is no loss of synchronization, the switching signal (frame pulse discontinuity detection signal) output from the clock recovery / synchronization signal processing unit 18 is at low level "0". Has become.

In this state, the selector 21 selects the output of the video signal processing section 10. That is, the output (Y, RY, BY) of the video signal processing unit 10 is directly output to the inverse matrix circuit 12.

However, the clock recovery / synchronization signal processing unit 1
When the discontinuity of the frame pulse is detected by 8, the switching signal becomes the high level "1". By this high-level switching signal, the selector 21 causes the register 2
It is switched so as to select each register output of 3.

Then, the three replacement video signals set in the register 23 are output to the inverse matrix circuit 12. By this processing, even if the frame pulse is out of synchronization, the replacement video signal is output to the inverse matrix circuit 12, and the display device 6 is further supplied via the DAC unit 13.
It is possible to display the image that has been distorted on the screen by replacing it with an arbitrary color image.

(Explanation of Third Embodiment) FIGS. 9 and 10 are views showing a third embodiment of the present invention. The third embodiment will be described below with reference to FIGS. 9 and 10.

§1: Explanation of configuration of television receiver
.. Refer to FIG. 9. FIG. 9 is a block diagram of the television receiver of the third embodiment. The third embodiment is an example in which the video replacement processing unit 17 is inserted in the subsequent stage of the inverse matrix circuit 12.

As shown in the figure, the television receiver 1 has the same BS tuner 3 and MUSE as in the first embodiment.
A decoder 4, an audio device 5, a display device 6 and the like are provided.

In addition, the MUSE decoder 4 has an AD
C7, video signal processing unit 10, inverse matrix circuit 12, D
AC unit 13, CPU 16, video replacement processing unit 17, clock reproduction / synchronization signal processing unit 18, audio signal processing unit 19
Etc. are provided. Further, the audio signal processing unit 19 has
The signal separation circuit 8 and the audio decoder 9 are provided, and the DAC
The part 13 is provided with three DACs.

In this case, the output of the ADC 7 is directly connected to the video signal processing unit 10, the inverse matrix circuit 12 is connected to the output of the video signal processing unit 10, and the inverse matrix circuit 1 is connected.
The video replacement processing unit 17 is connected to the second stage. The rest of the configuration is the same as that of the first embodiment, so the description is omitted.

§2: Description of Video Replacement Processing Unit--See FIG. 10 FIG. 10 is a block diagram of a video replacement processing unit according to the third embodiment. Hereinafter, based on FIG. 10, the video replacement processing unit 1
7 will be described.

As shown in the figure, this video replacement processing section 1
7, the nonvolatile memory 2 is the same as in the first embodiment.
2, a register 23 and a selector 21 are provided. in this case,
The register 23 is provided with three registers corresponding to the R, G, B signals output from the inverse matrix circuit 12, and the selector 21 is also provided for the R, G, B signals. Provide three selectors.

Further, the non-volatile memory 22 stores the data of the "replacement video signal" in advance, and this data is also the data (R, G, B) corresponding to the R, G, B signals.
(G and B are arbitrary values) are stored.

The operation of the video replacement processing section 17 is as follows. When the power of the television receiver is turned on, first, the CPU 16 reads out the three replacement video signals stored in the nonvolatile memory 22 and sets them in the three registers of the register 23. Then, the normal operation is started.

In the normal operation, when the frame pulses are continuous and there is no loss of synchronization, the switching signal (frame pulse discontinuity detection signal) output from the clock recovery / synchronization signal processing unit 18 is at low level "0". Has become.

In this state, the selector 21 selects the output of the inverse matrix circuit 12. That is, the output (R, G, B) of the inverse matrix circuit 12 is directly used in the DAC.
It is output to the unit 13.

However, the clock recovery / synchronization signal processing unit 1
When the discontinuous state of the frame pulse is detected by 8, the switching signal becomes the high level "1". The selector 21 is switched to select each register output of the register 23 by this high level switching signal.

Then, the three replacement video signals set in the register 23 are output to the DAC unit 13. By this processing, even if the frame pulse is out of synchronization, the replacement video signal is output to the DAC unit 13, and
It is possible to output the image from the AC unit 13 to the display device 6 and replace the image distorted on the screen with an arbitrary color image for display.

(Other Embodiments) The embodiments have been described above, but the present invention can be implemented as follows. The frame pulse discontinuity detector 32 shown in FIG.
You may provide in the control part 27.

The replacement video signal is not limited to the gray level video signal, and any video signal can be used. The replacement video signal to be set in the register 23 is not limited to the signal read from the non-volatile memory 22, and the CPU 16 may set an arbitrary video signal, for example.

The method of detecting out-of-sync due to switching of station is not limited to the method by the means of the above-mentioned embodiment, and it is possible to detect by any method. For example, "ITE Technical Report Vol.1"
7, No.54, PP.19-24, BCS 93-35, ROFT 93-52 (Sep. 1
993)} '3. Proposed processing flow (abandonment of synchronization)'
The method for checking continuity of synchronization described in section (especially,
It is also possible to detect the out-of-synchronization described in the above embodiment by using (see pages 21 and 22).

According to the above inspection method, the inspection items are "frame pulse undetected frequency", "horizontal synchronization undetected frequency", "2.025 MHZ component power", and "PL".
There is a “phase error voltage of L”, and the continuity of synchronization is checked by checking these items.

For example, according to the items described in the above inspection item, the MUSE decoder uses the pattern pulse detection method by pattern matching regardless of the reception status.
When the frame pulse is not detected continuously for 16 to 16 times,
It is described that the synchronous reset operation is started.

If the threshold value of the number of undetected horizontal synchronizations of 1125 times in one frame is controlled by the reception C / N by using the horizontal synchronization detection method by pattern matching, the continuity of synchronization is detected. It is stated that it is possible.

Further, in the MUSE decoder, the reproduction clock frequency is controlled by the phase error of the horizontal synchronizing signal. If this error voltage continuously exceeds the normal pull-in range, it means that the internal frequency of the MUSE decoder is not locked to the received signal, and therefore the continuity of synchronization can be checked based on this information. It is stated that it can be done.

Therefore, if the continuity of synchronization can be detected by the above-mentioned method, it is possible to detect out-of-sync due to switching of the station. That is, in the embodiment of the present invention, by using the out-of-synchronization detection signal as the "switching signal" of the selector, it is possible to carry out the same operation as in the embodiment.

Not limited to the MUSE decoder, the present invention can be applied to various television receivers, VTR (video tape recorder) decoders, and other various devices.

[0148]

As described above, the present invention has the following effects. : When the MUSE decoder is used, for example, if switching is performed without synchronization at the time of switching the source station, MUS
On the E decoder side, the sync signal disappears and the sync is lost.
In this case, in the MUSE decoder, the video that has been out of sync is replaced by the preset replacement video signal, so that the video on the display screen can be prevented from being disturbed.

Since it is possible to avoid the image disturbance due to the loss of synchronization, it is possible to prevent the deterioration of the display image quality. Therefore, it is possible to obtain a high-quality image suitable for a high-definition television image receiving device or the like according to the high-definition system.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a television receiver according to the first embodiment.

FIG. 3 is a block diagram of a video replacement processing unit according to the first embodiment.

FIG. 4 is a block diagram of a clock recovery / synchronization signal processing unit according to the first embodiment.

FIG. 5 is a flowchart of frame pulse discontinuity detection processing according to the first embodiment.

FIG. 6 is a time chart when the frame pulse discontinuity is detected in the first embodiment.

FIG. 7 is a block diagram of a television receiver according to a second embodiment.

FIG. 8 is a block diagram of a video replacement processing unit according to the second embodiment.

FIG. 9 is a block diagram of a television receiver according to a third embodiment.

FIG. 10 is a block diagram of a video replacement processing unit according to the third embodiment.

FIG. 11 is a block diagram of a conventional television receiver.

FIG. 12 is a MUSE signal format.

[Explanation of symbols]

 4 MUSE Decoder 16 CPU 17 Video Replacement Processing Unit 21 Selector 22 Nonvolatile Memory 23 Register 32 Frame Pulse Discontinuity Detection Unit

Claims (6)

[Claims] 1. A television signal decoder for decoding a television signal, said means for detecting a discontinuity (out-of-synchronization) of a synchronization signal due to switching of a station from an input television signal, and synchronization by said means. For a television signal, which is provided with a video replacement processing section (17) for replacing a video signal disturbed by the discontinuity of the sync signal with a preset arbitrary replacement video signal based on the signal discontinuity detection signal. decoder. 2. The television signal decoder according to claim 1, wherein the frame pulse discontinuity detecting section (22) for detecting frame pulse discontinuity from the input television signal is used as means for detecting the discontinuity of the synchronization signal. 32) is used, and the frame pulse discontinuity detection signal by the frame pulse discontinuity detection unit (32) is output to the video replacement processing unit (17) as a switching signal at the time of video replacement. Signal decoder. 3. The television signal decoder according to claim 1, further comprising: a register (23) for setting a replacement video signal in the video replacement processing section (17), and switching based on the discontinuity detection signal of the synchronization signal. A decoder for a television signal, comprising: a selector (21) for replacing a video signal disturbed by discontinuity of a sync signal with a replacement video signal set in the register (23). 4. An analog / digital converter (7) for converting an input television signal into a digital signal.
And a video signal processing unit for inputting a digital signal converted by the analog / digital converter (7) to process a video signal and outputting a luminance signal (Y) and a color difference signal (RY, BY). (10), the luminance signal (Y) output from the video signal processing unit (10), and the color difference signals (RY, BY) are input,
In a television signal decoder having an inverse matrix circuit (12) for converting each signal of red, green, and blue (R, G, B), a frame pulse from an input television signal due to switching to a station is input. A frame pulse discontinuity detection unit (32) for detecting discontinuity is provided, and an image disturbed by frame pulse discontinuity based on the frame pulse discontinuity detection signal is provided after the analog / digital converter (7). A video replacement processing unit (17) for replacing a signal with a preset replacement video signal is provided, and the video signal replaced by the video replacement processing unit (17) can be output to the video signal processing unit (10). A television signal decoder characterized in that 5. An analog / digital converter (7) for converting an input television signal into a digital signal.
And a video signal processing unit for inputting a digital signal converted by the analog / digital converter (7) to process a video signal and outputting a luminance signal (Y) and a color difference signal (RY, BY). (10), the luminance signal (Y) output from the video signal processing unit (10), and the color difference signals (RY, BY) are input,
In a television signal decoder having an inverse matrix circuit (12) for converting each signal of red, green, and blue (R, G, B), a frame pulse from an input television signal due to switching to a station is input. A frame pulse discontinuity detection unit (32) for detecting discontinuity is provided, and is output from the video signal processing unit (10) in front of the inverse matrix circuit (12) based on the frame pulse discontinuity detection signal. For each of the luminance signal (Y) and the color difference signals (RY, BY) that are generated, the image replacement processing unit that replaces the signal disturbed by the discontinuity of the frame pulse with an arbitrary color video signal ( A decoder for television signals, characterized in that the decoder 17) is provided. 6. An analog / digital converter (7) for converting an input television signal into a digital signal.
And a video signal processing unit for inputting a digital signal converted by the analog / digital converter (7) to process a video signal and outputting a luminance signal (Y) and a color difference signal (RY, BY). (10), the luminance signal (Y) output from the video signal processing unit (10), and the color difference signals (RY, BY) are input,
In a television signal decoder having an inverse matrix circuit (12) for converting each signal of red, green, and blue (R, G, B), a frame pulse from an input television signal due to switching to a station is input. A frame pulse discontinuity detection unit (32) for detecting discontinuity is provided, and is output from the inverse matrix circuit (12) at a subsequent stage of the inverse matrix circuit (12) based on the discontinuity detection signal of the frame pulse. Red, green, blue (R,
A television signal decoder comprising a video replacement processing unit (17) for replacing the signals G and B) disturbed by the discontinuity of frame pulses with an arbitrary color video signal.