JPH07162467A - Clock extractor - Google Patents

Abstract

PURPOSE:To correctly extract clock timing even if there is a frequency offset between an input signal carrier and a local signal. CONSTITUTION:Quadrature detection is performed for the input signal, the I signal and Q signal of the detection output are squared respectively and summed together, and an extractor 24 calculates the square root. Variance values at respective sample points in one symbol period of the output of the extractor 24 are calculated by a computing element 25. A decision means 27 decides the minimum value among the variance values and outputs the sampling point corresponding to the minimum value as clock timing. The variation state of the variance values becomes a curve 28 and the eye pattern of momentary electric power has an envelope maximum value 38 and a minimum value 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mounted on a satellite in satellite communication, for example, and receives an M-phase (M = 2 ⁿ , n is an integer of 1 or more) PSK (phase shift keying) modulated signal and modulates it. The present invention relates to a clock extractor that extracts a clock used for demodulating a digital signal.

[0002]

2. Description of the Related Art In a conventional clock extractor of this type, a demodulated output of a modulated digital signal of an input PSK modulated wave is a signal in which 1 and -1 are randomly generated, and a point which passes 0 of this signal. Was detected and the clock was extracted. However, in the case of multi-phase phase modulation, that is, in the case of a PSK modulation signal of two or more phases, if there is a frequency shift between the carrier wave of the received wave and the local signal, that is, if there is a so-called frequency offset, the 0 point fluctuation of the demodulation signal is large. It becomes difficult to extract the clock.

That is, the demodulated 1 and -1 continuous baseband digital signal waveforms are superimposed on each other in synchronization with the symbol lock and displayed on a cathode ray tube. A so-called eye pattern has a correct reception carrier frequency and local signal frequency. In the matched state, as shown in FIG. 3A, the digital signal 1
The state of -1, the state of -1, or the state in which they are continuous appears clearly, and the so-called eye is in a wide open state. Therefore, by determining the signal at the state where the eye is most open, 1 and -1 can be correctly identified, and the clock can be correctly extracted.

However, when the frequency of the received carrier wave and the frequency of the local signal are deviated and a frequency offset is generated, the phase is greatly rotated when the phase of the received signal is detected, and the eye pattern is as shown in FIG. 3B. And the eye does not open, that is, the envelope state of the signal changes even under the same digital signal condition, and it is impossible to know at what point to make the judgment, and it is possible to make judgments of 1 and -1. Also, the clock cannot be extracted. Therefore, when the phase shift between the input signal and the local signal is detected from the reproduced digital signal in the subsequent stage, the phase shift cannot be correctly detected, and it becomes difficult to pull the frequency of the local signal into the input carrier signal.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to correctly extract clock timing even if the difference between the frequency of the input carrier and the frequency of the local signal is relatively large and the frequency difference fluctuates due to fading or the like. Therefore, even in the carrier phase error detector placed after this clock extractor, the phase error between the input carrier and the local signal can be detected correctly, and the local signal frequency can be tracked to the input signal. It is to provide a clock extractor that enables the above.

[0006]

According to the present invention, the absolute value of the instantaneous in-phase component a (t) of the input M-phase PSK modulated signal is raised to the power x and the absolute value of the instantaneous quadrature component b (t) is raised to the power of y. Sum of P
The z-th power of x (x, y, and z are real numbers that are not 0) are detected by the instantaneous power detection means at each point obtained by dividing the symbol period of the modulated signal into equal intervals, and the clock timing is changed from the detected change state of P. It is judged by the judging means. In the invention of claim 2, the judging means calculates the variance value or standard deviation of the detected P for each of the division points, extracts the timing at which the calculated variance value or standard deviation is minimum, and extracts the point. It is the timing.

In the third aspect of the present invention, the determination means calculates the average value of P for each detected division point, and the timing at which the calculated average value becomes maximum is the clock timing. In the invention of claim 4, the determining means compares P for each detected division point, finds the timing at which the minimum value becomes maximum, and sets that point as the clock timing.

According to the fifth aspect of the invention, the determining means compares the detected P for each division point, finds the timing at which the maximum value becomes the minimum, and sets that point as the clock timing.

[0009]

FIG. 1A shows an embodiment of the invention of claim 2. The M-phase PSK input signal from the input terminal 11 is input to the instantaneous power detection means 12. In the instantaneous power detecting means 12, the input PS is supplied by the local signal from the local signal generator 13.
The K signal is quadrature-detected by the quadrature detector 14, and the I signal and the Q signal having mutually orthogonal components are detected. That is, the local signal from the local signal generator 13 and the input signal are multiplied by the multiplier 1
The signal is multiplied by 5 and is multiplied by the local signal whose phase is shifted by π / 2 by the phase shifter 16 by the multiplier 17, and the I signal and the Q signal are detected by these multipliers 15 and 17, respectively. For example, in a receiver mounted on a satellite, a carrier signal from the ground is dropped to a signal of about 100 KHz, and the signal of about 100 KHz is quadrature detected by a local signal of a local signal generator 13. Alternatively, in mobile communication, the received input carrier signal itself or the one converted into the intermediate frequency signal is quadrature detected by the local signal of the local signal generator 13.

In this example, the quadrature detection output is digitally processed to extract the clock timing. The I signal and Q signal from the quadrature detector 14 are analog low-pass filters not shown in the figure. After passing through A
The digital signals are converted into digital signals by the D converters 18 and 19, and after passing through a digital low-pass filter (not shown), these digital signals are squared by the squarers 21 and 22, respectively, and the squared outputs are added by the adder 23. Instantaneous power is obtained. The square root of the instantaneous power output is taken by the square root opener 24. In this way, the output of the square root breaker 24 is the square root of the instantaneous power, and is a value proportional to the instantaneous voltage amplitude value, which is another output of the detecting means 12.

The variance value of the detected instantaneous voltage amplitude value is calculated by the variance value calculating means 25. That is, a value (dispersion value) indicating the variation state of the instantaneous voltage amplitude value at each sampling point within one symbol period is stored in the memory 26, and the sampling point (timing) at which the dispersion value becomes the minimum is stored from the memory 26. The timing determined by the determination means 27 and having the minimum timing is output as the clock timing.

Assuming that there is a deviation Δf between the carrier frequency of the input signal from the input terminal 11 and the frequency of the local signal of the local signal generator 13, the I signal from the quadrature detector 14 is a (t) · cos. (2πΔft + θ) -b (t) si
n (2πΔft + θ) (a (t) and b (t) are symbol values, θ is the carrier initial phase difference), and the Q signal is a (t) sin (2πΔft + θ) + b (t) cos.
(2πΔft + θ). Therefore, the output of the adder 23 is A ² = I ² + Q ² = a ² (t) + b ² (t). No frequency error appears in the output of the adder 23.
This is displayed as an eye pattern as shown in FIG. 1B, which is an eye pattern in which the frequency offset between the local signal and the input signal is not affected. When the variance value of each sampling point in this eye pattern is obtained, the curve 28 in FIG. 1C is obtained. That is, in FIG. 1B, the sampling point P ₁ where the instantaneous voltage amplitude values are concentrated has the smallest variance value, and the curve 28 of this variance value has the minimum value P.
₁ is the clock timing, which corresponds to the point where the eye is most open in FIG. 3A. The variance value calculation unit 2
5, the memory 26, the minimum value determination unit 27, and the like are controlled by the control unit 29.

In the above description, the variance value is calculated for all the sampling points 0 to n (n is about 25, for example) in the AD converters 18 and 19 corresponding to one symbol length in the digital signal of the input signal. However, for example, in FIG.
As shown in, the three sampling points, that is, the first sampling point, the second sampling point, and the third sampling point, are focused, and the variance values σ ₀ ² , σ ₁ ² , and σ at 5 symbols or more for each of the three sampling points, for example. ₂ ² is obtained respectively, and considering the slope of the variance value curve 28, in the case of the figure, the variance value σ ₂ ² is smaller than σ ₀ ² , so the slope is to the right in the figure,
In other words, it can be seen that advancing the attention point of the sampling points approaches the point where the minimum value is obtained.
Similarly to the sampling points, the third sampling points, and the fourth sampling points, variance values of about 5 symbols for these three sampling points are obtained as shown in FIG. Of 3
Figure 2 shows that the center of the two is the smallest and both sides are almost the same.
Obtain as shown in C. By doing so, it is possible to obtain the clock timing with a smaller amount of calculation than when obtaining the variances for all the sampling points. In order to calculate the variance value for all sampling points in real time, it is necessary to significantly increase the calculation speed, and all the instantaneous data must be processed for 5 symbols or more, which takes a relatively long time. Like 3
The point-by-point processing requires less computation time at a time. Instead of paying attention to three adjacent sampling points, pay attention to three sampling points that are appropriately spaced, find the minimum value point, and reduce the spacing between the sampling points of the three points of interest. You can also speed up the time to reach the clock timing.

Like the preamble data, + 1,-
When 1 is taken alternately, the dispersion value becomes zero, and the invention of claim 2 cannot be applied, but since the digital signal of communication data takes +1 and -1 at random, the present invention can be applied. In the embodiment of the invention of claim 3, as shown in FIG. 2D, the average value of the instantaneous power detected by the instantaneous power detecting means 12 is calculated by the average value calculating means 31, and the average value is supplied to 32 and the average value is supplied. The maximum value of the determination means 33
Then, the sampling point having the maximum average value is output as the clock timing. That is, when the average value of the instantaneous power at each sampling point is calculated in FIG.
As shown by the curve 34 of C, the average value curve 34 becomes maximum at the point where the variance value curve 28 becomes minimum, and this sampling point is output as clock timing.

Further, as can be seen from the minimum value envelope 35 in FIG. 1B, the point where the minimum value envelope 35 becomes maximum is the timing P ₁ . Therefore, in claim 3, among the detected instantaneous powers as shown in FIG. 2E, the point of the minimum value is stored in the minimum value storage memory 36, and the maximum value is determined from the stored value of the minimum value storage memory 36. The determination is made at 37, and the sampling point having the maximum value is output as the clock timing.

Similarly, since the minimum value of the envelope 38 at the maximum instantaneous power value in FIG. 1B is the clock timing P ₁ , the instantaneous power detected as shown in FIG. Is stored in the maximum value storage memory 39, the minimum value among the maximum values in the memory 39 is determined by the determination means 41, and the sampling point having the minimum value is output as the clock timing.

In the cases shown in FIGS. 2D, 2E and 2F, respectively.
However, if it is the same as described in FIGS. 2A, 2B and 2C,
3 sumps instead of focusing on all sampling points
Pay attention to the ring point and obtain each maximum or minimum value
You can also do it. So each sampling point like this
If you calculate all of
Since there is no such calculation, pay attention to the three sampling points
By doing so, it is possible to reduce the calculation time as a whole.
It will be possible. Also, in the above, the instantaneous power detection means 12
The output of the square root breaker 24 was used as the output of
The output of the calculator 23 may be used as the instantaneous power. One more
Generally, the instantaneous in-phase component a (t) of the M-phase PSK modulated wave is 2
2 of the nth power (n is an integer of 1 or more) and the instantaneous orthogonal component b (t)
Sum Pp with nth power or nth root Pq of Pp =ⁿ√ Detect Pp
Then, for Pp or Pq, the variance value, standard deviation, average value,
Find the maximum sampling point of minimum and minimum sampling point of maximum
You may do it. More generally, the absolute value of a (t)
Sum of the power of x and the power of y of the absolute value of the instantaneous orthogonal component b (t) P
Z power (x, y, z are real numbers that are not 0) P = (| a (t)
｜^x+ | B (t) |^y)^zMay be detected. This
Is the minimum when x and y are negative in the case of
To obtain the maximum value, and when x and y are negative,
Will seek the maximum. x = y = 3, z = 1, tab
R | a (t) |³+ | B (t) |³And its variance
Is obtained | a (t) |²+ | B (t) |²(X = y =
As shown in FIG. 4, the variance value of z, z = 1)
The curve of the spread curve is sharp and the timing of the minimum value
Judgment is easy and accurate. Dispersion value when x = y = 4
The curve becomes sharper. In terms of simplifying calculations
| A (t) | + | b (t) | That is, x = y = z = 1
Good. Differentiate x and y, for example x = 2.5, y = 2,
z = 1, that is, | a (t) |^2.5+ | B (t) | ²age
Then, as described above, the clock timing is calculated by obtaining the variance value.
The component of a (t) is stronger than the component of b (t).
Will contribute a lot.

FIG. 5A shows an embodiment of the invention of claim 6.
The I signal and the Q signal are input to the sign inversion detector 45, which is shown in FIG.
As shown in B, the state where the sign of each of the I signal and the Q signal is inverted compared to the one symbol before is detected. In order to check the sign inversion, it is possible to determine by multiplying the one delayed by one symbol and the one not delayed so that the sign becomes negative, or by taking the exclusive OR of both. The minimum point determination unit 46 detects the minimum point of I ² + Q ² in one symbol in which this state is detected. If both ends of a point separated between one symbol are at or near the minimum point, the sign inversion detection will be inaccurate. In order to relieve such a case, it is more accurate if it is performed at a point shifted by half a symbol. In the initial stage, it is better to judge the code for each half symbol in this way. In the minimum value determination unit 40, the current time and the one symbol before are marked at equal intervals, for example, at 25 points, and the value of I ² + Q ² at each point is checked,
As shown in FIG. 5C, the minimum point is obtained, and the position shifted by half a symbol from the timing at this point is determined as the clock timing.

This clock extraction method can be obtained by accumulating data for only one symbol. When it is necessary to reduce the amount of calculation in real-time processing, the number of points may be appropriately reduced without performing processing for all points in one symbol. At a minimum, I ² + Q ² is calculated with only two points, the clock is shifted to the smaller side, and the same process is performed on the next data, and the correct clock timing is sequentially approached. If it is not shifted, the decision point is left as it is and compared with a point in the opposite direction. If it is smaller, the point is shifted in that direction, and if not, that point becomes the minimum point. To make the clock extraction a little faster, there is also a method of calculating three points and shifting to the minimum value. Further, even when the determination is made by two points or several points, the intervals may be provided instead of the adjacent points. The interval may be initially set, and may be reduced over time. By doing so, the amount of calculation can be reduced and the clock extraction time can be shortened.

Even in the determination of the minimum value in this case, (│I
| ^X + | Q | ^y ) ^z (where x, y, and z are real numbers that are not zero) may be used. The clock extraction of FIG.
Clocks can be extracted from any signal as long as the signals are simultaneously sign-inverted. Further, it is not necessary to store data for one symbol or more, which simplifies. Although the amount of calculation is a little large, it is possible to reliably extract the clock timing even for a signal having a frequency offset, as compared with the conventional method of extracting the clock only at one zero-cross point of I or Q.

As can be understood from the above description, the clock timing can be generally judged from the changing state of P, such as monitoring the turning point of P over time and the state of the differential value.

The local signal generator 13 and the quadrature detector 14 may also be constituted by digital circuits. Also, the input signal is the I signal,
It may be given as a Q signal. In this case, digital processing is performed, and the input signal and the local signal are subjected to complex multiplication instead of quadrature detection. I signal like this,
When the Q signal is input and digitally processed and the deviation of the carrier frequency of the input baseband signal with respect to the reference frequency is zero, the frequency of the local signal is set to zero, and the frequency corresponding to the deviation of the reference frequency of the carrier frequency of the input signal. The present invention is also applied to the case where the local signal of 1 is generated to correct the frequency shift.

[0023]

As described above, according to the present invention, even if there is an error between the carrier wave of the input signal and the frequency of the local signal, the clock timing can be correctly extracted regardless of the error. Therefore, the carrier phase error detection unit can correctly detect the phase shift, can perform the frequency tracking of the input signal of the local signal in a wide range, and can synchronize the signals quickly, thereby ensuring stable operation. Become.

[Brief description of drawings]

1A is a block diagram showing an embodiment of the invention of claim 2, B is a diagram showing an eye pattern of instantaneous power, and C is a diagram showing a dispersion value and an average value of instantaneous power.

2A, 2B and 2C are diagrams for explaining a method for obtaining a minimum point of a variance value, D is a block diagram showing an essential part of the invention of claim 3, and E is an embodiment of the invention of claim 4. Is a block diagram showing an essential part of the invention, and F is a block diagram showing an essential part of the invention of claim 5.

FIG. 3A is a diagram showing an eye pattern when there is no carrier frequency offset, and B is a diagram showing an eye pattern when there is a frequency offset.

FIG. 4 is a diagram showing a variance value of P in each case of x = y = 2, x = y = 3, and x = y = 4 in P = | a (t) | ^x + | b (t) | ^y . .

FIG. 5A is a block diagram showing an embodiment of the invention of claim 6, and B and C are diagrams used for the explanation.

Claims (8)

[Claims] 1. M phase (M = 2 ⁿ , n is an integer of 1 or more) P
Sum of the absolute value of the instantaneous in-phase component a (t) of the SK modulated signal to the power of y and the absolute value of the instantaneous quadrature component b (t) to the power of z (x, y, and z are real numbers that are not 0) M-phase PSK modulation clock extractor comprising: instantaneous power detection means for detecting each symbol period at equal intervals, and determination means for determining clock timing from the detected change state of P. 2. The calculating means calculates the dispersion value or standard deviation of the detected P for each point obtained by dividing the symbol period into equal intervals, and the calculated dispersion value or standard deviation is the minimum value. 2. A means for setting the timing to be a clock timing.
A clock extractor for M-phase PSK modulation as described. 3. The determination means calculates the average value of the detected P for each point obtained by dividing the symbol period at equal intervals, and the timing at which the calculated average value is maximum is the clock timing. The clock extractor for M-phase PSK modulation according to claim 1, further comprising: 4. The determining means is means for comparing the detected P at each point obtained by dividing a symbol period into equal intervals, and setting a timing at which the minimum value becomes maximum as a clock timing. The M-phase PS according to claim 1,
K-modulated clock extractor. 5. The determining means is means for comparing the detected P at each point obtained by dividing a symbol period into equal intervals, and setting a timing at which the maximum value is minimum as a clock timing. The M-phase PS according to claim 1,
K-modulated clock extractor. 6. The determining means includes the instantaneous in-phase component a (t) and the instantaneous quadrature component b (t) within one symbol period.
And a means for detecting a state in which the sign is inverted at the same time, a means for detecting a time point when the sum P becomes the minimum in the one symbol period in the detection state, and a point deviated from the detected time point by a half symbol period. The M-phase PS according to claim 1, further comprising means for setting a clock timing.
K-modulated clock extractor. 7. The clock extractor for M-phase PSK modulation according to claim 1, wherein x and y are integers equal to each other, and z is 1. 8. The determining means detects a state in which the instantaneous in-phase component a (t) and the instantaneous quadrature component b (t) are both sign-reversed within one symbol period, and the state is detected. Then, a (t) ² + b (t) ² of the two sampling points in the above 1 symbol period is calculated, and the sampling points are shifted to the smaller one, thereby sequentially a (t) ² + b ^2. The clock extractor according to claim 1, further comprising means for setting a clock timing at a point shifted by a half symbol period from a sampling point which is closest to the minimum point of (t) ² .