JPH07115446A - Clock regenerator for digital phase modulation - Google Patents

Abstract

PURPOSE:To find a clock decision point correctly and with small computing quantity even when carrier frequency difference exists between an input signal and a local signal. CONSTITUTION:The input signal is orthogonally detected by an orthogonal detector 17, and each detected output is supplied to square devices 23, 24 via poliphase filters 21, 22, and the output of them are squared, respectively, and they are added by an adder 25, then, a momentary power is detected. The momentary power delayed by a one symbol delay device 27 is subtracted by a subtractor 26. The power is sampled at 1/2 symbol period, and the lead/lag of a clock is discriminated from the codes of three sampling values by a discrimination part 29 so that the center sampling value of continuous three points can be set at zero and the codes of the sampling values before and behind can be set reversely, and either one of poliphase filters 21, 22 is selected sequentially corresponding to the discriminated result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mounted on a satellite in satellite communication, for example, and receives an M-phase (M = 2 ⁿ , n is an integer of 1 or more) PSK (phase shift keying) modulated signal and modulates it. The present invention relates to a clock extractor that extracts a clock used to demodulate a digital signal.

[0002]

2. Description of the Related Art A demodulated output of a modulated digital signal of an input PSK modulated wave is a signal in which 1 and -1 occur randomly,
In the conventional clock extractor of this type, the clock is extracted by detecting the point at which 0 of this signal passes. However, if there is a frequency shift between the carrier wave of the received wave and the local signal, that is, if there is a so-called frequency offset, the 0 point of the demodulated signal fluctuates greatly and it becomes difficult to extract the clock.

That is, the demodulated 1 and -1 continuous baseband digital signal waveforms are superimposed on each other in synchronization with the symbol lock and displayed on a cathode ray tube. A so-called eye pattern has a correct reception carrier frequency and local signal frequency. In the state of coincidence and no noise, as shown in FIG. 3A, the state of the digital signal 1, the state of −1, or the state in which they are continuous appears clearly, and the so-called eye is wide open. Therefore, by judging the signal when the eye is in the most open state, 1 and -1 can be correctly discriminated, and the clock can be correctly extracted.

However, when the frequency of the received carrier wave and the frequency of the local signal are deviated and a frequency offset is generated, the phase is greatly rotated when the phase of the received signal is detected, and the eye pattern is as shown in FIG. 3B. And the eye does not open, that is, the envelope state of the signal changes even under the same digital signal condition, and it is impossible to know at what point to make the judgment, and it is possible to make judgments of 1 and -1. Also, the clock cannot be extracted. Therefore, when the phase shift between the input signal and the local signal is detected from the reproduced digital signal in the subsequent stage, the phase shift cannot be correctly detected, and it becomes difficult to pull the frequency of the local signal into the input carrier signal.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to correctly extract a clock decision point even if the difference between the frequency of an input carrier and the frequency of a local signal is relatively large and the frequency difference fluctuates. Therefore, in the carrier phase error detector installed in the subsequent stage, the phase error between the input carrier and the local signal can be accurately detected, and the local signal frequency can be made to follow the input signal. It is to provide a clock extractor.

[0006]

According to the present invention, the absolute value of the instantaneous in-phase component a (t) of the M-phase (M = 2 ⁿ , n is an integer of 1 or more) PSK-modulated input signal is raised to the s-th power (s). Is a non-zero real number) and the sum P of the absolute value of the instantaneous orthogonal component b (t), P
x or the r-th root Py = ^r √Px (real number r is not 0)
Is obtained by the instantaneous power detection means, and the detected Px
Alternatively, the difference between Py and Px or Py one symbol period before the digital signal in the input PSK modulated signal is obtained, the 0 crossing point of the difference is searched, and the searched 0 crossing point is set as the clock decision point. .

[0007]

FIG. 1 shows an embodiment of the present invention. Input terminal 1
The M-phase PSK signal is input from 1, and the instantaneous power is detected by the instantaneous power detecting means 12. In the instantaneous power detecting means 12, the input phase modulated signal is multiplied by the local signal from the local oscillator 13 by the multiplier 14, and the local signal is shifted by π / 2 phase by the phase shifter 15 to be multiplied by 1.
It is multiplied by 6 with the input signal. That is, the input signal is orthogonally detected by the orthogonal detector 17 by the local signal. A signal converted into a carrier frequency of the received radio wave or an intermediate frequency signal is input to the input terminal 11 and converted into a baseband signal by the local signal.

In this embodiment, the quadrature-detected I and Q signals are digitally processed to obtain instantaneous power, and the subsequent processing is also digitally processed. In this case, the quadrature detector 17 converts the I signal into an AD signal. A converter 18 converts the digital signal into a digital signal, and an AD converter 19 converts the Q signal into a digital signal. The outputs of these AD converters 18 and 19 are passed through polyphase filters 21 and 22 as phase shift means for detecting a 0 crossing point, which will be described later, and then squarers 23 and 24.
And the outputs of the squarers 23 and 24 are added by the adder 25. This added value becomes the output of the instantaneous power detection means 12. The instantaneous power detected by the adder 25 is supplied to the subtractor 26 and the 1-symbol delay unit 27. The 1-symbol delay unit 27 delays the PSK modulated signal at the input terminal 11 by the 1-symbol period of the digital signal. The output of the 1-symbol delay unit 27, that is, the instantaneous power detected one symbol period before is subtracted by the subtractor 26 from the instantaneous power detected this time. Depending on the state of the output of the subtracter 26, the 0 crossing point is searched.

Now, the carrier frequency of the input signal at the input terminal 11
And the frequency of the local signal of the local oscillator 13 is Δf.
Then, the I signal obtained from the quadrature detector 17 is √P / 2 {a
(T) · cos2πΔft-b (t) sin2πΔf
t}, and the Q signal is √P / 2 {a (t) sin2πΔ
ft + b (t) cos2πΔft}. Therefore squared
The output A of the adder 25 obtained by adding the outputs of the adders 23 and 24 is A = P / 2 {a²(T) + b²(T)}. Where P is the average power and a (t) and b (t) are
Envelope that takes +1 or -1 at lock timing
Indicates. The eye pattern of the output of the adder 25 is shown in FIG. 2A.
This eye pattern is a frequency offset
It is not related to Δf. In the figure, as an example,
When the waveform is shaped by a roll-off filter with a rule-off rate of 1
Is shown. This eye pattern is a regular black
Judgment point P ₁Has converged to one point in
It Therefore, take the difference from the one symbol delayed.
The eye pattern of the differential instantaneous power is as shown in FIG. 2B.
Next to the clock judgment point P₁At 0. this
If one of the patterns is taken out, for example, the song shown in FIG.
Line, AD converter 1 for symbol period T in this example
The sampling cycle in 8 and 19 is T_SThe symbol lap
If it is set to 1/2 of period T,
Period T_SThe calculation processing is performed for each
At line 28, for example at time t₀, T₁, T₂At
Is performed, in which case the normal 0 crossing is
Sampling point t₁Let τ be the deviation of
Pulling point t₁Is sampled at mT + τ,
Point t when one sampling period before₀Is (m-1 / 2) T
+ Τ, which is the point t after one sampling period₂Is (m + 1
/ 2) T + τ. These three sampling points
t₀, T₁, T₂Sample values of curve 28 in
S₀, S₁, S₂Sampling pulse
It is possible to determine the lead / lag of the clock with respect to the regular clock. This
2C, the sample value S₀Is positive, sample value S
₁, S₂Both are negative, which is also clear from the figure
So that only τ of the receiving side clock (regular clock)
The state where the judgment point is advanced is shown. Therefore these 3
Two sampling points t₀, T ₁, T₂Each sump in
Value S₀, S₁, S₂Local clock from the sign state of
The lead / lag of (sampling signal) can be determined. this
The judgment conditions are as shown in FIG. Case 2 is here
2C, the local clock is advanced
Case 1 is the case where the curve 28 of FIG. 2C is delayed.
Is the sampling point t₁Cut later than
Case 3 shows a delayed state and case 3 is a song
Case 4 shows the case where the polarity of the line 28 is reversed.
The reverse state of the case 1 is shown. Therefore this figure
1 from the output of the subtractor 26 shown in FIG.
In 29, determine what kind of state it is, and
Phase of the received clock and the local clock according to
Control so that

The clock of this input signal and the local clock
In order to eliminate the phase difference of
Polyphase filters 21 and 22 on the output side of 18 and 19
Is inserted in the polyphase filter 21.
Pass filter 21₀Through 21 _n-1Is provided, and the n
One of the filters is the determination of the clock correction direction determination unit 29.
It is selected according to the result. Low pass filter 21₀Through
21_n-1Respectively impinges on the output of the AD converter 18.
The loose response is convolved and the input signal is band-limited.
And the intersymbol interference is eliminated. For that now
Impedance of low-pass filter to obtain desired waveform of
Filter is given as shown in FIG. 3A.
21₀As shown in FIG. 3B, the tap coefficient of the response of FIG.
The characteristic is T / before and after the center.
2 intervals, that is, sampling interval Ts
Then, each value is given as a tap coefficient.
Against this filter 21₁For when compared to Figure 3B
Figure at each point deviated by a constant value ΔT (1 tap) in the axial direction
3A response characteristic is taken out and each value is taken as a tap coefficient.
Given by the filter 21₂Is more than twice the ΔT
The value of the impulse response at each point is the tap coefficient.
Given by the filter 21_n-1For the in
Deviation from the center of the pulse response by (n-1) ΔT, and
The value for each Ts is taken out and these are given as tap coefficients.
available.

Therefore, the filter 21₀Through 21_n-1Which one
The input signal is filtered by selecting₀To
Any of 0 to (n-1) ΔT for the output that has passed
A signal whose phase is shifted by only is output. Polyphase
The filter 22 is also composed of similar n low-pass filters.
Has been. As described above, the clock correction direction determination unit 29
Input signal clock and local signal clock depending on the output of
The polyphase filter 21, so that
One of the 22 filters is selected and the selected
The filter is the sampling point t in FIG. 2C.₁The sun
Pull value S₁Becomes 0, and sampling points before and after that
t₀And t₂Sample value S in₀And S ₂Is a mark
Until the signals have opposite signs.
Select the filter from the filter filters 21 and 22
U When this selection is completed, the subtractor 26
The search for the output 0 crossing is completed, and the 0 crossing at that time
The sampling point corresponding to the point is output as the clock judgment point.
I will be forced. Based on this clock decision point
The outputs of the filters 21 and 22 by +1 or -1
The digital signal can be decoded.

The procedure of the zero-crossing search process described above will be described with reference to FIG. First the current sample value S _j, compared with the threshold value in one period T before the sample values S _j-2 and the half period T _s prior to the sample value S _{j- 1} each processing step and is performed. Here, each sample value is reset to 0 if it is less than or equal to the threshold value. This process is 0
The sample value at the intersection is basically 0, but it is not always 0 due to imperfections in the hardware and Gaussian noise, so this is done to absorb this. It is desirable that the threshold value be as close to 0 as possible, but it must be a value that takes into consideration the dispersion caused by the above-mentioned inhibiting factors.

In the step, it is checked whether the current sample value S _j is 0 and the sample value S _j-2 one cycle before is 0, and the local clock is a half cycle (half a symbol cycle) with respect to the input clock. It is determined whether T _{s is} deviated. The reason for performing this process is that if the process is performed in steps with a half-cycle offset, it will proceed, and delay control will not be performed.
This is because it is locked in this state. The half-cycle shift is detected when the current sample value S _j and the sample value S _j-2 one symbol period before (two samples before) are both 0. When this is detected, the operation of kicking off the local clock timing for a half cycle is performed.

When S _j = 0 and S _j-2 = 0 are not satisfied, advance or delay of the local clock is detected in step.
First, the sign a of each sample value S _j , S _j-2 , S _j-1 ,
b and c are determined (3a). These codes a, b, and c take values of +1, -1, and 0, respectively. It is checked whether the sign of the current sample value S _j and the sample value S _j-2 one cycle before is inverted, that is, whether the product of a and b is -1 (3
In the case of b) and -1, it is an object of control. In other cases, that is, when the product is 0 or +1 is excluded from the control target. Further advance and delay detection is performed by detecting the current sample value S _j.
And the sample value S _j-1 of a half cycle before, that is, the product of a and c is checked (3c). That is, if the product of a and c is +1 it is determined that the local clock is advanced,
In the case of -1, it is judged to be late. This is 0
If, the control is not performed.

When the advance or delay of the clock is detected in step, this information is output as tap control information for each symbol period, and the polyphase filter 21,
Returned to 22. The clock phase shift is corrected by switching the filters one by one to search for an accurate clock phase. Each output of the polyphase filters 21 and 22 is taken out every other sample and supplied to the carrier wave regenerating unit.

In the above description, the polyphase filter 2
The input signals sampled at 2 samples / symbol by 1 and 22 were detected and the phases of I and Q signals were shifted. However, the complex baseband input signal was sampled many times during one symbol period by the A / D converter. In addition, by providing one of the filters 21 and 22 corresponding to the filter 21 ₀ , the phase of the local clock is shifted, that is, the sampling point t ₀ in FIG. 2C,
These t ₁ and t ₂ may be sequentially shifted, for example, by ΔT so that τ in FIG. 2C becomes smaller according to the determination result of the clock correction direction determination unit 29. As the polyphase filters 21 and 22 without providing the filter 21 ₀ to 21 _n-1 individually, the filter 21 ₀ to the digital signal processor (DSP) 21
_The phase shift may be performed by performing each calculation of _n-1 . Further, a square root calculation of the output of the adder 25 may be used as the instantaneous power output. Generally, in the instantaneous power detection unit 12 in FIG. 1, between the s-th power of the absolute value of the instantaneous in-phase component a (t) (s is a real number that is not 0) and the s-th power of the absolute value of the instantaneous quadrature component b (t). sum Px or r-th root Py = ^r √Px calculated in (the r real number not zero), may be supplied to Px or Py to the adder 26 and the one-symbol delay unit 27.

Further, the input signal may be input as the I signal and the Q signal, and in this case, the quadrature detector 17 is a complex multiplier of the input signal and the local signal. When there is no deviation of the input carrier frequency from the reference frequency, the frequency of the local signal is set to zero, and a local signal having a frequency corresponding to the deviation of the input carrier frequency from the reference frequency is generated. This invention can be applied.

[0018]

As described above, according to the present invention, the instantaneous power in the input signal is detected so that there is no influence of the frequency offset between the input signal and the local signal, and the clock is correct and fast. A decision point can be obtained. Moreover, the sampling period for the calculation may be performed for two samples within one symbol period of the digital signal in the input signal, and in such a relatively long sample period, the central value at the three sample points is used. By obtaining the relationship between the symbol and the code before and after the symbol, it is possible to easily detect the delay of the phase, the calculation time is short, and the power consumption is small. Therefore, even if the input signal frequency is unstable in the carrier phase error detector installed in the latter stage of this clock regenerator, the carrier phase error signal with the local signal can be correctly and quickly obtained. The local signal can be quickly tracked to the.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A is a diagram showing an eye pattern of the instantaneous power of an input signal, FIG. 2B is a diagram showing an eye pattern of the difference between the instantaneous power of the input signal and the instantaneous power one symbol before, and FIG. 2C is one of FIG. The figure which shows a curve and three sampling points, D is a figure which shows the sign of the sampling value in those three sampling points, and the advance or delay state of a clock signal.

3A is a diagram showing an impulse response of a low-pass filter with waveform shaping, and FIGS. 3B to 3E are conceptual diagrams of tap coefficients of filters 21 ₀ , 21 ₁ and 21 _{n-1 in} the polyphase filter 21, respectively. It is a figure.

FIG. 4 is a flowchart showing an example of 0-intersection search processing.

5A is a diagram showing an eye pattern when there is no frequency offset, and FIG. 5B is a diagram showing an eye pattern when there is a frequency offset.

Claims (1)

[Claims] 1. M phase (M = 2 ⁿ , n is an integer of 1 or more) P
Sum Px of the absolute value of the instantaneous in-phase component a (t) of the SK modulated signal (s is a real number that is not 0) and the absolute power of the absolute value of the instantaneous orthogonal component b (t) Px or its rth root Py = ^r √Px (r is a real number other than 0) for detecting an instantaneous power, and means for obtaining a difference between the detected Px or Py and Px or Py one symbol period before the digital signal of the PSK modulated signal. A digital phase modulation clock regenerator comprising means for searching for a 0-crossing point of Px or Py of the difference and using the 0-crossing point as a clock determination point.