JPH07161183A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce an area of a chip by using a column address bus (YBUS) in common among a plurality of memory banks, taking a column address into a column decoder via a bank selector, reducing an occupying area by the YBUS and making a distance of memory banks small. CONSTITUTION:A YBUS is shared between memory banks 1 and 0. A column address is selectively taken into decoders 101-108 by bank selectors BS1-BS8. By utilizing a time required for comparing an input address with an address for saving a redundancy, the column address is transmitted to the neighborhood of all the column decoders. The column address has reached the BS1-BS8 by the time when the comparison result by a redundancy comparison circuit 118 is obtained. When the result is obtained, a normal column address or an redundancy-saving address is selectively transmitted to the decoders 101-108 promptly. Therefore, an irregularity in a delay amount of a data line selection signal 121 among memory mats is greatly reduced, a margin for an operation timing is made small, and addressing of a column is conducted at high velocity, so that the memory device is operated at high velocity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a technique for increasing the operating speed of the semiconductor memory device, for example, a synchronous DRAM (dynamic random access memory).
Memory) and effective technology.

[0002]

2. Description of the Related Art In a DRAM, dynamic circuits operating in synchronization with a clock are used for peripheral circuits such as an address buffer, a decoder and a sense amplifier to reduce power consumption. Therefore, external clocks of one to three phases are required, and internal circuit clocks are generated based on these clocks to control or drive the peripheral circuits. In such a DRAM,
Random access is mainly performed, and a memory cell is selected by sequentially reading a row address and a column address for each access. Each part of the peripheral circuit is controlled by an internal clock so as to follow the procedures of row selection, detection of memory cell information, and column selection in order to prevent information destruction of the memory cell.

An example of a document describing DRAM is "LSI Handbook (Page 486-)" issued by Ohm Co., Ltd. on November 30, 1984.

[0004]

By the way, in recent years, MPU
Due to the improvement of the operation cycle of (micro processing unit), the operation time difference between it and DRAM becomes a problem, and one of the solutions is to write and read data in synchronization with the clock of MPU. , A synchronous DRAM is proposed. Conventional D
In the RAM, when one word line is driven to a selection level, all the memory cells connected to it are activated, which enables high-speed read / write by activating only the column decoder. There is a page mode, and by realizing a mode corresponding to the page mode in the burst mode of DRAM, the speed of data input / output can be increased.

FIG. 5 shows an example of the structure of a synchronous DRAM.

This synchronous DRAM has a memory bank 1 (Bank 1) and a memory bank 0 (Bank 0).
Have and. This memory bank (hereinafter simply “bank”)
1) and memory bank 0 have basically the same structure, and memory mats 511, 512, 513, 514 each having a plurality of memory cells arranged in an array.
including. Also, the column address buffer 515, the column address predecoder 517, and the column decoders 501 to 501
508, redundancy comparison circuit 518, column control circuit 51
6. A main amplifier MA is provided. The column address fetched through the column address buffer 515 is predecoded by the column address predecoder 517. The predecoded output of the column address predecoder 517 is the column address bus YBUS formed corresponding to bank 0 and bank 1, respectively.
1, YBUS0 to the column decoders 501 to 50
4 and the column decoders 505 to 508 to be decoded there, so that each memory mat 531
The data line selection signal 512 for controlling the column selection switch is generated at ˜538. That is, based on the column decoding result, the corresponding data line selection signal 521 is asserted to the selection level, and the data lines in each of the memory mats 531 to 538 are selectively coupled to the common data line, whereby the memory cell data Can be read. The read memory cell data can be externally output via the corresponding main amplifier MA. When the column address is input to the redundancy comparison circuit 518, the input address is compared with the redundancy repair address, and if they match, the redundancy repair address is selected instead of the regular column address. It has become.

In a semiconductor memory having a plurality of banks such as the synchronous DRAM shown in FIG. 5, a column decoder 50 is used in order to achieve a high speed operation of a column circuit.
The distributed arrangement of 1 to 508 is indispensable, but in the banks B0 / 1, activation mat selection is performed independently of each other, and therefore it is necessary to supply a column address signal for each bank. Therefore, the column address predecoder 51
8 predecode output to column address decoder 501
Column address bus YBUS for transmission to ~ 508
It has been found by the present inventor that 1 and YBUS0 have to be formed corresponding to the banks 1 and 0, which is a main factor inhibiting the reduction of the chip area of the semiconductor memory device. It was

In the column circuit operation, the address output from the address buffer 515 and the redundancy repair address are compared by the redundancy comparison circuit 518. Based on the result of the judgment, the column address predecoder 517 outputs the normal address / redundancy repair address. One of the predecode signals is output from the redundancy comparison circuit 518 even though the column address to be predecoded has already been taken in by the column address predecoder 517. Pre-decode output cannot be performed until the comparison result is transmitted. The present inventor has clarified that this is the main factor that hinders the speeding up of column addressing.

Further, since the signal for activating the main amplifier MA is generated based on the delay signal from the column system control circuit 516, it is necessary to consider the variation of the data line selection signal 512 in the generation. . That is, it is necessary to set the delay amount of the activation signal of the main amplifier MA in consideration of the responses of the redundancy comparison circuit 518 as the generation system of the data line selection signal 512 and the column decoders 501 to 508. In that case, it is necessary to take a large timing margin in consideration of variations in the delay amount of the column address, which also hinders the operation speeding up.

An object of the present invention is to reduce the chip area of a semiconductor memory device. Another object of the present invention is to speed up the operation of the semiconductor memory device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a semiconductor memory device is provided with a column address bus shared by a plurality of memory banks, and a selection means for selectively fetching a column address transmitted via the column address bus into a column decoder. Constitute. At this time, the selecting means can be arranged in the vicinity of each of the column decoders. further,
Comparison means for comparing the input column address with a preset redundant relief address, and redundancy relief means for replacing the decoding target address of the column decoder with the redundancy relief address based on the comparison result. In the case of including, the redundancy repair means can be arranged in the vicinity of each corresponding column decoder.

[0014]

According to the above means, sharing a column address bus among a plurality of memory banks is more effective than providing a dedicated column address bus for each memory bank.
It acts to reduce the area occupied by the column address bus, which in turn reduces the chip area.

Further, by disposing the selecting means for each corresponding column decoder in the vicinity thereof, the wiring between the column address bus and the column decoder can be optimized.

Further, by disposing the redundancy relieving means for each of the column decoders in the vicinity thereof, the column address is assigned to all columns by utilizing the time required for the comparison operation of the input address and the redundancy relief address. It is possible to transmit even near the decoder. This makes it possible to reduce the operation timing margin in setting the delay amount of the start signal of the main amplifier MA, and achieves high speed column addressing, and thus high speed operation of the semiconductor memory device.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 functionally shows the overall structure of a synchronous DRAM which is an embodiment of a semiconductor memory device according to the present invention. Synchronous DRAM shown in FIG.
Is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The synchronous DRAM shown in FIG.
Although not particularly limited, two memory banks 1 (Ba) that can be selected by a part of the row address input from the outside
nk1) and memory bank 0 (Bank0). Banks 1 and 0 each have a plurality of memory mats each having dynamic memory cells arranged in an array. The bank selection circuit 405 selectively transmits a column address to the banks 1 and 0 to select an access target bank.
5 are provided. Bank selecting circuit 405 includes a plurality of bank selectors arranged corresponding to the memory mats, as described later in detail.

A row address buffer 411 is provided,
The row address fetched via the row address buffer 411 is used as the row address predecoder 410 in the subsequent stage.
Row decoding circuit 4 after being predecoded by
08 and 409 are transmitted. Based on the decoded outputs of the row decode circuits 408 and 409, the selection signals of the word lines included in the banks 1 and 0 are generated. The upper bits of the row address are used as selection bits for banks 1 and 0.

Further, the column address buffer 1 is externally supplied.
A column address counter 414 for generating a subsequent column address using the column address input via 15 as an initial address is provided, and the generated column address is transmitted to the column address predecoder 117 and predecoded there. After that, it is transmitted to the bank selection circuit 405.

When one word line is driven to the selection level based on the decoded output of the row address, the memory cell coupled to it is selected. At this time, by operating the column selection switch based on the data line selection signal generated by decoding the column address, the data line is selectively coupled to the common data line, and thereby the data to the memory cell is It is possible to write or read data from the memory cell. Since the signal level of the memory cell data is weak, sense amplifiers 403 and 407 for amplifying the signal level are provided. The memory cell data amplified by the sense amplifiers 403 and 407 are input / output circuits 401 and 402, respectively.
External output is possible via the main amplifier MA included in the. Further, write data from the outside is transmitted to the common data line after being amplified by the write amplifier WA included in the input / output circuit 401, and transmitted via the data line selected based on the column address as described above. Writing is enabled by transmitting to the corresponding memory cell.

FIG. 1 shows a configuration example of the main part of the synchronous DRAM in a form close to an actual layout.

Although not particularly limited, Bank 1 (Bank)
1) and bank 0 (Bank 0) are arranged corresponding to each other in the semiconductor chip. Bank 1 and bank 0 have basically the same configuration, and each include memory mats 131 to 138 each having a plurality of memory cells arranged in an array.
In addition, the column address buffer 115 and the column address predecoder 1 occupying a relatively large layout area
17, redundancy comparison circuit 118, column system control circuit 116
Are arranged at positions where access paths of all memory mats are as short as possible. In the present embodiment, the memory mat 132 in the bank 1 is not particularly limited.
The column address buffer 115, the column address predecoder 117, the redundancy comparison circuit 118, and the column control circuit 116 are arranged between the memory mat 133 and the memory mat 133.

A column address bus YBUS for transmitting a predecode signal is provided between banks 1 and 0. In this embodiment, in order to reduce the chip area, the column address bus YBUS is set to one system,
The bank 1 and the bank 0 share the column address bus YBUS of the one system. When the column address bus is shared in this way, the column address decoder 101 is provided in order to optimize the column address transmission.
To 108 are provided corresponding to the bank selectors BS1 to BS8, and the column addresses transmitted to the column address bus YBUS are selectively taken into the corresponding column decoders 101 to 108 by the bank selectors BS1 to BS8. Has become.

The column address fetched through the column address buffer 115 is predecoded by the column address predecoder 117, and the predecoded output is transmitted to the column decoders 101 to 108 and decoded there. Thereby, a control signal for selectively controlling the column selection switch is generated. By selectively coupling the data line to the common data line by this column switch, the memory cell data can be read. The read memory cell data can be externally output via the corresponding main amplifier MA. Main amplifier MA for enabling external output of read data from a memory cell
Are memory mats 131 to 131 for each bank 1 and 0.
A plurality of them are arranged in the vicinity of 138.

Further, the column address is the redundancy comparison circuit 11
When it is input to 8, the input address and the redundant relief address are compared, and if they match, the redundant relief address is selected instead of the regular column address.

Here, the redundant comparison circuit 118 is an example of comparison means in the present invention.

The comparison result in the redundancy comparing circuit 118 is transmitted to the bank selectors BS1 to BS8.
In the bank selectors BS1 to BS8, the logical state of the column redundancy repair signal to be output to the column decoder is determined based on the address comparison result transmitted from the redundancy comparison circuit 118. The column redundancy repair signal 125 is not particularly limited, but is a high active signal, and when the column redundancy repair signal is asserted to a high level, the column address decoders 101 to 108 replace the column address. It should be noted that the column redundancy repair signal has two systems. That is, in the present embodiment, although not particularly limited, two types of addresses that can be redundantly repaired are prepared.

The column system control circuit 116 receives the clock signal CLK, the row address strobe signal RAS *, and the column address strobe signal CA, which are taken in from the outside.
Depending on S *, the write enable signal WE *, etc., the column address predecoder 117 and the redundancy comparison circuit 11
8. It has a function of controlling the operation of the column system including the bank selectors BS1 to BS8. In particular, two column system activation signals 12 are supplied to the bank selectors BS1 to BS8.
0 is output, and bank 1 and bank 0 are individually controlled. That is, the column system activation signal 120A is supplied to the bank selectors BS1 to BS4 corresponding to the bank 1, and the column system activation signal 120B is supplied to the bank selectors BS5 to BS8 corresponding to the bank 0.
Are output respectively. The column system activation signals 120A and 120B of the two systems include a read activation signal for instructing a read operation and a write activation signal for activating a write operation.

Next, the bank selector will be described in detail.

FIG. 3 shows the plurality of bank selectors BS1.
Of BS8 to BS8, a configuration example is representatively shown for the bank selector BS1.

Although not particularly limited, the bank selector BS1 is composed of a combination of logic circuits such as an inverter, a NAND circuit, and a CMOS transfer gate as shown in FIG.

Although not particularly limited, the column address predecoder 117 to the column decoder 10 shown in FIG.
Upper gate circuit 301 and lower gate circuit 30 for restricting passage of a predecode signal to be transmitted to
Two are provided. The upper gate circuit 301 limits the transmission of the upper 12 bits of the predecode signal transmitted from the column address predecoder 117 under a certain condition. The upper gate circuit 301 is not particularly limited. CMO placed after it
Twelve sets of coupling circuits of the S transfer gate 304 and the inverter 305 for inverting the output logic of the CMOS transfer gate 304 are arranged. The lower gate circuit 302 limits transmission of the lower 8 bits of the predecode signal transmitted from the column address predecoder 117 under a certain condition. The input NAND circuit 306, an inverter 307 for inverting its logic output, a CMOS transfer gate 308 arranged at the subsequent stage thereof, and an inverter 30 for inverting the output logic of this CMOS transfer gate 308.
Eight sets of coupling circuits with 9 are arranged.

2 from the redundancy comparison circuit 118
A column redundancy system gate circuit 330 corresponding to the configuration of the redundancy repair signal 125 is provided to limit the transmission of the system redundancy repair signal 125 under a certain condition. The first gate circuit of the column redundancy system includes an input first stage inverter 310,
An inverter 312 for inverting its output logic,
A CMOS transfer gate 313 arranged in the subsequent stage of the inverter 312 and an inverter 314 for inverting the output logic thereof are connected. Similarly, the second gate circuit of the column redundancy system includes an inverter 315 at the input first stage, an inverter 316 for inverting the output logic of the inverter 315, a CMOS transfer gate 317 arranged at a stage subsequent to the inverter 316, and It is connected to an inverter 318 for inverting the output logic.

Further, all the MOS transfer gates 304 and 30 included in the upper gate circuit 301, the lower gate circuit 303, and the column redundancy system gate circuit 330.
A control logic circuit 331 is provided to control the operations of the 8, 313, 317 and the operations of the main amplifier MA and the write amplifier WA (see FIG. 4). This control logic circuit 3
Although not particularly limited, 31 is configured as follows.

In order to obtain the NAND logic of the column activation signal 120, that is, the read activation signal and the write activation signal, and the mat activation signal, the 2-input NAND circuits 319 and 3 are provided.
20 is provided, and inverters 321 and 322 for inverting the output logic thereof are provided. A 2-input NOR circuit 323 for obtaining the NOR logic of the logical outputs of the inverters 321 and 322, and an inverter 326 for inverting the output logic thereof are provided. This inverter 3
The logic output of 26 is used as a signal for controlling the CMOS transfer gate. In addition, the CMOS transfer gates 304, 308, 313, 317 are p
Channel type MOS transistor and n channel type MO
An inverter 3 for inverting the output logic of the above-mentioned inverter 326 including a S-transistor and supplying a signal of a complementary level for controlling the operation thereof.
29 are provided.

Here, the mat activation signal is a signal for selectively activating the memory mats 131 to 138 shown in FIG. 1. Although not particularly limited, the upper bits of the row address signal are decoded. Obtained by For example, the bank selector BS1 shown in FIG.
As is clear from FIG. 1, since it corresponds to the memory mat 131, the mat activation signal shown in FIG. 3 is a signal for instructing activation of the memory mat 131. That is, when the mat activation signal is asserted to the high level, one of the input terminals of the NAND circuits 319 and 320 in the control logic circuit 331 is set to the high level, so that the read activation signal and the write signal, respectively. Upper gate circuit 30 according to the logic state
1, lower gate circuit 302, column redundancy system gate circuit 3
All CMOS transfer gates 30 included in 30
4,308,314,317, and main amplifier MA
Also, it is possible to control the operation of the write amplifier WA.

For example, when the read activation signal is asserted to the high level by the column control circuit 116 while the mat activation signal is asserted to the high level, the logical output of the NAND circuit 319 is set to the low level. Therefore, the upper gate circuit 301, the lower gate circuit 302,
All CMOs included in the column redundancy system gate circuit 330
S transfer gates 304, 308, 314, 317
Is turned on, and at that time, the column address bus YB
Since the predecode signal transmitted from the column address predecoder 117 via the US is transmitted to the column decoder 101 shown in FIG. 1, the memory mat 131 can be accessed. That is, the column decoder 10
A predecode signal is input to 1 and is decoded to control the operation of the column selection switch included in the memory mat, so that the memory cell data can be read. Then, when the output logic of the NAND circuit is set to the low level by setting the read start signal to the high level as described above, the output logic of the inverter 327 is set to the high level, and the main amplifier start signal is set. Since 120 is asserted to the high level, the four main amplifiers MA corresponding to the memory mat 131 in FIG. 1 are simultaneously enabled, and the external output of the memory cell data is enabled.

Further, in the read mode, when the redundancy repair is performed in the memory mat 131, the column address replacement is performed as follows.

In the address comparison in the redundancy comparison circuit 118, when the input address and the redundancy relief address match, at least one of the two systems of the redundancy relief signal 125 of the redundancy relief circuit 118 is set to the high level. Therefore, all the NAND circuits 306 in the lower gate circuit 302 are inactivated, which blocks the output of the lower 8 bits of the predecode signal input via the column address bus YBUS. At this time, all the output stage inverters 309 in the lower gate circuit 302
The output logic of is at high level. Furthermore, since at least one of the inverters 314 and 318 becomes low level, in the column decoder 501 shown in FIG. 1, the redundant relief address is decoded instead of the regular column address. That is, depending on the redundancy repair signal 125 which is the comparison result of the redundancy comparison circuit 118, a plurality of 3
By controlling the logic of the input terminal of the input NAND circuit 306, the normal address can be replaced with the redundant relief address. In that sense, the logic circuit including the plurality of 3-input NAND circuits 306 and the column redundancy system gate circuit 330 is an example of the redundancy relieving means in the present invention.

On the other hand, if the write activation signal is asserted to the high level while the mat activation signal is asserted to the high level, the output logic of the NAND circuit 320 is set to the high level. Similarly, all the CMOS transfer gates 304, 308, 313, 317 included in the upper gate circuit 301, the lower gate circuit 302, and the column redundancy system gate circuit 330 are turned on, and at that time, via the column address bus YBUS. The pre-decode signal transmitted from the column address pre-decoder 117 is the column decoder 101 shown in FIG.
Is transmitted to the memory mat 131, the memory mat 131 can be accessed. That is, the predecode signal is input to the column decoder 101, and the predecode signal is decoded to generate the data selection signal 121 for controlling the operation of the column selection switch included in the memory mat, thereby selecting the data line. Therefore, the memory cell data can be read. Then, when the output logic of the NAND circuit 320 is set to the low level by setting the write start signal to the high level as described above,
When the output logic of the inverter 328 is set to the high level, the write amplifier activation signal 122 is asserted to the high level, so that the memory mat 131 in FIG.
The write amplifier WA (see FIG. 4) corresponding to is enabled almost at the same time, thereby enabling data writing to the memory cell.

Also in the write mode, if the memory mat 131 is subjected to redundancy repair, column address replacement is performed as follows.

In the address comparison in the redundancy comparison circuit 118, when the input address and the redundancy relief address match, at least one of the two systems of the redundancy relief signal 125 of the redundancy relief circuit 118 becomes high level, All NAND circuits 306 in the lower gate circuit 302
Is deactivated, the column address bus YBU
Lower 8 of the predecode signals input via S
Bit output is blocked. At this time, the inverter 31
When at least one of 4, 318 goes low, the column decoder 501 shown in FIG. 1 decodes the redundant relief address instead of the regular column address.

In the case of the synchronous DRAM, as shown in FIG. 4, since the data input / output port is shared by bank 1 and bank 0, the memory mat 131 in bank 1 is activated as described above. In the activated state, the memory mat in bank 0 is activated to avoid data collision, but the read / write activation signals of bank 0/1 are not asserted at the same time.

The other bank selectors BS2 to BS8 are similarly constructed.

FIG. 2 shows the operation timing of the main parts in the synchronous DRAM of this embodiment. For comparison, the operation timing in the circuit configuration shown in FIG. 5 is shown in FIG.
Shown in.

For example, in the circuit configuration shown in FIG. 5, in the column circuit operation, the address output from the address buffer 515 and the redundant relief address are compared by the redundant comparison circuit 518, and the column address pre-charge is determined by the result of the comparison. Since the decoder 517 outputs the predecode signal of either the normal address or the redundant repair address, even if the column address to be predecoded is already taken in by the column address predecoder 517. Nevertheless, predecode output cannot be performed until the address comparison result is transmitted from the redundancy comparison circuit 518. In addition, the column decoder 501 compared to the column address predecoder 517 side (near end side).
The pre-decode address on the side of -508 (far end side) is delayed. Therefore, the read data can be accurately transmitted to the main amplifier MA.
In order to take into account, it is necessary to secure a sufficient timing margin by making the time from the assertion of the data line selection signal 521 to the assertion of the main amplifier activation signal 520 relatively long. .

On the other hand, in the present embodiment, the column address bus YBUS is shared by the plurality of memory banks 1 and 0, and the column addresses are selectively taken into the column decoders 101 to 108 by the bank selectors BS1 to BS8. In this way, the column address can be transmitted to the vicinity of all the column decoders by utilizing the time required for the comparison operation of the input address and the redundant repair address. Therefore, for example, as shown in FIG. In the case of being operated in synchronization with the clock CLK from the column, the column address strobe signal CAS *, etc., the redundancy comparison circuit 118
At the time when the address comparison result is output at the bank selectors BS1 to BS1.
It can be transmitted to BS8 (far end side). Therefore, the normal column address or the redundant repair address can be quickly and selectively transmitted to the column decoder 101108 after the address comparison result in the redundancy comparison circuit 118 is output. As a result, the variation in the delay amount (generation timing) of the data line selection signal 121 between the memory mats can be significantly reduced, so that the operation timing margin can be reduced in setting the delay amount of the main amplifier start signal 120. be able to. Since the timing margin can be reduced as described above, the column addressing can be speeded up, and thus the high speed operation of the semiconductor memory device can be achieved.

According to the above embodiment, the following operational effects can be obtained.

(1) By sharing the column address bus YBUS among a plurality of memory banks 1 and 0,
Since the area occupied by the column address bus can be reduced as compared with the case where the column address bus is provided for each memory bank as in the configuration shown in FIG.
And the memory bank 0 can be made smaller, and the area of the semiconductor chip can be reduced accordingly.

(2) Further, it has a function as a selection means for selectively fetching the column address into the column decoders 501 to 508, a generation logic of the main amplifier start signal 120, and a generation logic of the write amplifier start signal. The bank selectors BS1 to BS8 are connected to the column decoder 10 respectively.
The column address bus YBUS is arranged every 1 to 108 and in the vicinity of the corresponding column decoder.
And the wiring between the column decoders 101 to 108 can be optimized. In other words, it is possible to avoid unnecessary wiring.

(3) By arranging a plurality of NAND circuits 306 and column redundancy system gate circuits 330 as redundancy relief means in the vicinity of the corresponding column decoders 101 to 108, the input address and the redundancy relief address are compared. By using the time required for the operation, the column address can be transmitted to the vicinity of all the column decoders.
That is, in the configuration shown in FIG.
The address output from 15 and the redundant relief address are compared by the redundant comparison circuit 518, and the predecode signal is output from the column address predecoder 517 based on the determination result. In the present embodiment, however, In the redundancy comparison circuit 118, a predecode signal is sent from the column address predecoder 117 to the column address bus YBUS while the input address and the redundancy relief address are being compared, so that the redundancy comparison circuit 118, for example, can be used. By the time the address comparison result is output, the predecode signal of the column address can be transmitted to the bank selectors BS1 to BS8.
Therefore, in the present embodiment, it is possible to greatly reduce the variation in the delay amount (generation timing) of the data line selection signal 121 between the memory mats, and thereby set the delay amount of the activation signal of the main amplifier MA. Since the operation timing margin can be reduced, the column addressing can be speeded up, and the semiconductor memory device can be operated at high speed. Further, as shown in FIG. 5, when the control signal for the main amplifier or the write amplifier is generated in the column control circuit 516, each main amplifier and each main amplifier are controlled by the column control circuit 516, which is the signal generation means. Because the distance to the light amplifier is different,
Although variations in signal delays inevitably increase there, the logic for generating the main amplifier activation signal 120 and the write amplifier activation signal 122 should be formed in the bank selectors BS1 to BS8 as in the above embodiment. Therefore, in other words, the generation logic of the activation signal 120 and the write amplifier activation signal 122 is changed for each corresponding column data.
By arranging the distributed logic in the vicinity of it, the distance from the generation logic to the corresponding main amplifier or write amplifier can be shortened and can be made almost equal to each other.
As compared with the case shown in FIG. 5, the signal delay amount and its variation can be reduced. This is very effective in speeding up the operation.

(4) A plurality of three-input NAND circuits whose active and inactive states are controlled by the logical outputs of the inverters 310 and 315 as a redundant relief means for replacing the decoding target address of the column decoder with the redundant relief address. Since the 306 and the column redundancy gate circuit 330 are provided in each of the plurality of bank selectors BS1 to BS8, waste in the configuration of the logic circuit can be suppressed.

FIG. 7 shows a computer system including a semiconductor memory device according to the present invention.

This system includes a CPU (central processing unit) 701, a DRAM control unit 703, an SRAM (static random access memory) 706, a ROM (read only memory) via a system bus 700.
705, peripheral device control unit 707, display system 710,
By being communicatively coupled to each other,
It is configured as a computer system that performs predetermined data processing according to a predetermined program.

The CPU 701 is the logical core of the present system, and mainly addresses, information reading and writing, data operation, instruction sequence, interrupt acceptance, and information exchange between storage device and input / output device. It has a function of activating, etc., and is composed of various units such as an arithmetic control unit, a bus control unit and a memory access control unit.

As an internal storage device, a DRAM 702 controlled by the DRAM control unit 703 or an SRAM
706, a backup control unit 704 for controlling the backup of the SRAM 706, and a ROM 705 are provided. The RAM 702 and SRAM 706 are the CPU 70
Programs and data required for calculation and control in 1 are stored. Since the ROM 705 is read-only, a program that normally does not require modification is possible.

The peripheral device control unit 707 is not particularly limited, but the external storage device 70, which is a magnetic storage device as an example, is used.
8 and a peripheral device such as an input device such as a keyboard (KB) 709 as an example.

The display system 710 is a VRAM (video.
Random access memory) 710A and its control circuit, and the display data transferred via the system bus 700 is output to the display device 712 in synchronization with the CRT display device 712. Also,
A power supply unit 711 is provided, and various voltages generated here are supplied to each unit of this system.

In such a computer system, as the DRAM 702 and the VRAM 710A,
The synchronous DRAM according to the above embodiment can be applied. In that case, the DRAM 702
In addition, since speeding up the operation of the VRAM 710A is important for speeding up the entire system, such a D
The application of the synchronous DRAM according to the above embodiment to the RAM 702 and the VRAM 710A is extremely effective in constructing a high speed system.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the redundancy comparison circuit 1
Column decoder 1 based on the address comparison result in 18
A plurality of 3-input NAND circuits 306 are provided as a redundancy repair means for replacing the decoding target addresses 01 to 108 with the redundancy repair addresses, and the 3-input NAND circuits 306 are provided near the corresponding column decoders 101 to 108. Although it is arranged, the column address bus YB
By sharing the US between multiple memory banks,
As long as the area of the semiconductor chip is simply reduced, the formation of the redundancy relieving means and the location of the arrangement are not limited. In addition, CMOS transfer gates 304, 30
Instead of 8, 313, 317, a clocked inverter,
Further, an appropriate gate circuit such as an AND circuit and a NAND circuit can be applied. Although the above embodiment has described the one having two memory banks, even when more memory banks are provided, the column address bus is shared between them, which is similar to the case of the above embodiment. The effect can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM which is the field of use which is the background of the invention has been described, but the present invention is not limited to this and is not limited to the ordinary DRAM. DRAM
It can be widely applied to various semiconductor memory devices such as or static RAM, and various data processing devices such as microcomputers including such semiconductor memory devices.

The present invention can be applied on condition that it has at least a plurality of memory banks.

[0065]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by sharing the column address bus among a plurality of memory banks, the area occupied by the column address bus can be reduced as compared with the case where a column address bus is provided for each memory bank.
The chip area of the semiconductor memory device can be reduced.

By disposing the selecting means for each corresponding column decoder in the vicinity thereof, the wiring between the column address bus and the column decoder can be optimized.

Furthermore, by disposing the redundancy relieving means for each corresponding column decoder in the vicinity thereof, the column address can be used for all columns by utilizing the time required for the comparison operation of the input address and the redundancy relief address. Since the data can be transmitted to the vicinity of the decoder, the column addressing can be speeded up, and the semiconductor memory device can be operated at high speed.

[Brief description of drawings]

FIG. 1 is a synchronous DRA according to an embodiment of the present invention.
It is a principal part block diagram of M.

FIG. 2 is an operation timing chart of the synchronous DRAM.

FIG. 3 is a circuit diagram of a bank selector included in the synchronous DRAM.

FIG. 4 is an overall configuration block diagram of the synchronous DRAM.

FIG. 5 is a block diagram of a main part of a synchronous DRAM which is a comparison target of the synchronous DRAM.

6 is an operation timing chart of the synchronous DRAM shown in FIG.

FIG. 7 is a block diagram of a configuration example of a computer system including a synchronous DRAM according to the present invention.

[Explanation of symbols]

 101-108 column decoder 115 column address buffer 116 column system control circuit 117 column address predecoder 118 redundancy comparison circuit 120 (120A, 120B) column system activation signal 125 redundancy repair signal 131-138 memory mat 301 upper gate circuit 302 lower gate circuit 306 NAND circuit 330 Column redundant system gate circuit 331 Control logic circuit BS1 to BS8 Bank selector Bank1 bank Bank2 bank MA main amplifier YBUS column address bus

Claims (4)

[Claims] 1. A bit line select signal is generated based on a plurality of memory mats each having a plurality of memory cells coupled to each of a plurality of bit lines and a column address input via a column address bus. In a semiconductor memory device having a plurality of memory banks including a column decoder for storing the column address bus shared by the plurality of memory banks and transmitted through the column address bus. 2. A semiconductor memory device characterized by comprising selection means for selectively taking in the column decoder into the column decoder. 2. The semiconductor memory device according to claim 1, wherein said selecting means is arranged in the vicinity of each corresponding column decoder. 3. A comparison means for comparing an input column address with a preset redundant relief address, and the decoding target address of the column decoder is replaced with the redundant relief address based on the comparison result. 3. The semiconductor memory device according to claim 1, further comprising: a redundant relieving unit for each column decoder, which is arranged in the vicinity of each corresponding column decoder. 4. The generation logic of a signal instructing activation of a main amplifier for amplifying read data from the memory cell and the generation logic of a signal instructing activation of a write amplifier for amplifying write data are provided. 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is arranged in the vicinity of the selecting means or the redundancy repairing means.