JPH0715989B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and particularly to a fine structure having low resistance when electrically connecting to a semiconductor substrate.

[Background of the Invention]

In a semiconductor integrated circuit, transistors, resistors, capacitors, etc. are formed on a semiconductor substrate by photolithography. At this time, since the semiconductor substrate has conductivity, it is necessary to provide a terminal for electrically connecting to the semiconductor substrate (hereinafter referred to as a substrate terminal) to maintain a constant potential to prevent malfunction of the circuit. FIG. 1 shows a cross-sectional structure of a base terminal which has been generally used conventionally.
An n-type epitaxial layer 14 is provided on the p-type semiconductor substrate 10. Surface of semiconductor substrate 10 and n-type epitaxial layer 14
A high-impurity concentration layer 11 having the same conductivity type as the semiconductor substrate and low resistance is formed on the side surface of the. Layer 12 is an oxide film for device isolation,
13 is a metal. The metal 13 passes through the high-concentration p-type layer 11,
It is electrically connected to the semiconductor substrate 10.

FIG. 2 is an example of a manufacturing method for realizing the structure of FIG. FIG. 2A: An n-type epitaxial layer 14 is grown on the p-type semiconductor substrate 10. After that, a thermal oxide film 20, a silicon oxynitride film 21 and a photoresist 22 are provided on the entire surface.
FIG. 2 (b): Silicon fluorinated film 21 using resist as a mask
And the thermal oxide film 20 is etched. Then, the resist is removed and the epitaxial layer 14 is etched using the silicon oxynitride film 21 and the thermal oxide film 20 as a mask. FIG. 2 (c): Boron is implanted on the entire surface to form the high concentration p-type layer 11. FIG. 2 (d): The silicon oxide film 21 is used as a mask to thermally oxidize the epitaxial layer or the semiconductor substrate to form the thermal oxide film 12. The silicon oxynitride film 21 and the thermal oxide film 20 are removed,
An Al electrode is provided to obtain the structure shown in FIG.

The substrate terminal of FIG. 1 is widely used because of its simple manufacturing method, but has the following drawbacks.

The element isolation oxide film 12 is formed by thermal oxidation of the epitaxial layer 14 or the semiconductor substrate 10. Since boron easily enters the oxide film during oxidation, most of the boron implanted in the step of FIG. 2C does not contribute to conduction. Therefore, the resistance of the high-concentration p-type layer 11 increases, and it is necessary to increase the peripheral length of the same element in order to make sufficient electrical connection for stable operation of the circuit. Therefore, there is a drawback that the occupied area of the base terminal is large.

As an example of the above, Japanese Patent Laid-Open No. 56-1556 can be cited.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a fine base terminal having low resistance.

[Outline of Invention]

The structure of the present invention for achieving the above object is to provide a polycrystalline silicon layer containing a high concentration impurity on a side wall of single crystal silicon.

A technique for forming a polycrystalline silicon layer on the side wall of single crystal silicon is disclosed in Japanese Patent Application No. 54-75715. In this patent application, a fine and high-speed transistor having a small parasitic capacitance is realized by using the same technology. The present invention is particularly effective when used at the same time as the transistor because no additional process is required in manufacturing the same transistor.

Example of Invention

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a sectional structural view of a base terminal as an embodiment of the present invention. In order to clearly show the present invention, the numbers of the drawings used in FIG. 1 of the above-mentioned conventional example are used unless otherwise specified. In the present invention, the polycrystalline Si 32 on the oxide film 31 is provided in contact with the side wall of the single crystal Si 14. Polycrystalline Si contains high-concentration impurities of the same conductivity type as the substrate 10 and the high-concentration layer 11. A high-concentration region 33 is formed by diffusing impurities from the polycrystalline Si 32.
The metal 13 is electrically connected to the substrate through the polycrystalline Si 32 and the high concentration regions 33 and 11.

FIG. 4 shows an example of a manufacturing process for embodying the semiconductor device of the present invention, which is shown before the sectional structure of FIG. The manufacturing process will be described below according to the drawing numbers.

FIG. 4A: A p-type semiconductor substrate 10 is prepared. Impurity is n
However, in that case the following impurities must be of opposite conductivity type. Further, instead of using the substrate as a conductor, the substrate may be a substrate having the meaning of the meaning that an electric conductor is placed on an insulator. This is SOI (Sillicon on Insnlato
r) or SOS (Sillicon on Sapphire).

The inventors of the present invention used the substrate as an impurity type p-type and an impurity concentration of 5
The one of × 10 ¹⁴ cm ^-3 was selected.

Next, the p-type single crystal layer 14 is formed by the epitaxial growth method.
To form.

The epitaxial layer 14 can have a desired thickness depending on the growth time, temperature and the like.

The inventors obtained a 1 μm epitaxial growth layer 14.

Next, the thermal oxide film 41 is formed on the entire surface. The oxide film 41 may be formed by deposition.

Next, a silicon oxynitride film 42 is formed by deposition. Further, a silicon oxide film 43 is formed by deposition. The present inventors formed a three-layer film of an oxide film 41, a fluorinated film 42, and an oxide film 43 of 50 nm, 120 nm, and 900 nm, respectively.

FIG. 4B: A photoresist is applied on the entire surface and patterned, and a part of the three-layer film 41, 42, 43 is removed using the photoresist as a mask. Then, the photoresist is removed.

FIG. 4 (c): Next, the epitaxial growth layer is etched using the three-layer film as a mask to form a convex region. Since formation uses unidirectional dry etching, there is almost no side etching.

FIG. 4D: The thermal oxide film 44 is formed again. This may be formed by deposition. However, in that case, the shape is slightly different. Further, a silicon oxynitride film 45 is formed thereon by deposition. The inventors formed a silicon oxide film and a silicon oxynitride film of 50 nm and 120 nm.

FIG. 4 (e): Next, etching is performed by unidirectional dry etching to leave the silicon oxynitride film 45 only on the side surface of the convex region. Since this is formed by unidirectional dry etching, a photo mask for etching is unnecessary.

Then, boron is implanted on the entire surface to form a high concentration p-type region 11.

FIG. 4 (f): Next, thermal oxidation is performed using the silicon oxynitride film 45 as a mask to form a thick oxide film 31. The present inventors formed a 700 nm oxide film.

FIG. 4 (g): Next, the silicon oxynitride film 45 is removed, and further the silicon oxide film 44 is removed.

FIG. 4 (h): Polycrystalline silicon 32 is deposited on the entire surface, and a silicon oxide film 46 is further formed by deposition.

The inventors deposited polycrystalline silicon twice at 350 nm to form a total of 700 nm, and formed a silicon oxide film to 200 nm.

FIG. 4 (i): A resist 47 is applied to the entire surface, and the resist in a region slightly larger than the convex region is removed by a photo mask process.

The inventors have removed the resist in the area 1 μm larger on each side from the convex area.

FIG. 4 (j): Photo resist 47 and another photo resist
Apply 48 to the entire surface to make the surface flat.

FIG. 4 (k): Sputter etching is performed in an O ₂ atmosphere to uniformly remove the photo resist 48 until the oxide film 46 is exposed.

FIG. 4 (l): The exposed oxide film is removed by wet etching, and the exposed polycrystalline silicon layer is removed by dry etching.

FIG. 4 (m): Photo resists 47 and 48 and oxide film 46 are removed.

FIG. 4 (n): A silicon oxide film 49 is formed on the surface of the polycrystalline silicon 32 by a thermal oxidation method, and a silicon oxynitride film is formed on the entire surface.
Deposit 50. After that, a part of the silicon oxynitride film and the silicon oxide film is selectively removed by a photo mask process.

Further, the polycrystalline silicon layer 32 is etched by dry etching to reduce the thickness of the same. This process is
This is performed to form the element surface flat later, but it may be omitted.

FIG. 4 (o): Polysilicon is selectively oxidized using the silicon oxynitride film 50 as a mask to form an oxide film 12. After that, the silicon oxynitride film 50 is removed, and boron is added to the polycrystalline silicon by the ion implantation method.

This boron diffuses into the single crystal Si14 by a thermal process and forms a p-type region 33.

After that, the oxide films 49, 43, 41 and the silicon oxynitride film 42 are removed, and a metal electrode is attached by a usual method to obtain the structure shown in FIG.

〔The invention's effect〕

According to the present invention, the resistance between the electrode 13 and the substrate 10 is about 100Ω, which is a value smaller by one digit or more than the conventional example shown in FIG. As a result, it is enough to make the element small,
Since it functions as a base terminal, it is possible to improve the integration density of a circuit using the same element.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view showing a conventional example, FIG. 2 is a sectional view showing a manufacturing process of a conventional example in process order, FIG. 3 is a structural cross-sectional view showing the present invention, and FIG. 4 is a manufacturing process of the present invention. It is sectional drawing shown in order of a process. 10 ... Substrate, 14 ... Epitaxy layer, 11,33 ... High concentration p-type layer, 12,31 ... Oxide film, 13 ... Metal, 32 ... Polycrystalline Si.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Hayashida 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP 58-93220 (JP, A) JP 56 -157058 (JP, A)

Claims (1)

[Claims] 1. A single crystal semiconductor substrate having a p-type, an insulating film having an opening and formed on the surface of the substrate, and connected to the substrate and formed almost vertically just above the opening. And a first region formed of a single crystal semiconductor layer thicker than the insulating film, and a surface in contact with the insulating film and the base and a sidewall surface of the first region in the base and the first region, respectively. The p-type third region that is formed and has a concentration higher than the impurity concentration of the base has substantially the same thickness as the first region protruding above the insulating film, and a sidewall of the first region. A second region formed of a polycrystalline semiconductor layer having a p-type and formed in contact with the first region, a metal electrode formed on the first region and the second region, the metal electrode and the third region. And the distance from the sidewall surface of the first region exceeds the depth of the third region. Wherein a and a fourth region of the p-type formed on the upper portion of the side wall of the first area as.