JPH0715835B2 - Fluorescent light dimmer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a fluorescent lamp dimming device used for dimming a light source such as a liquid crystal display device.

“Prior Art” As a fluorescent lamp light control device of this type, the one shown in FIG. 9 has been conventionally used. That is, the AC signal is supplied from the AC signal generator 1 to the gate circuit 2 (FIG. 10A), while the clock signal is supplied from the clock generator 3 to the duty ratio adjusting circuit (for example, a monostable multivibrator) 4. Given (Fig. 10B), the duty ratio D is the set value of the dimming ratio.
P / n (where 1 / n represents the minimum dimming ratio, Is. ) Is adjusted almost equally and is given to the gate circuit 2 as a control signal (FIG. 10C). The gate circuit 2 interrupts the input AC signal by this control signal, and outputs the obtained burst signal to the output terminal 5 as a fluorescent lamp driving signal (FIG. 10D).

"Problems of the prior art" Since ambient light in which a liquid crystal display device is placed has a wide dynamic range from direct sunlight to darkness at midnight, the brightness of the display device is generally 300 cd / m ^{2 to} 0. .
It is said that it is desirable to be able to finely adjust the value within the range of 3 cd / m ² . Therefore, as a fluorescent lamp dimming device used for dimming the light source (fluorescent lamp) of this display device, the dimming ratio
It is desirable that 1 / n can be set in the range of 1/1000 to 1000/1000, and the adjustment pitch thereof is quite small (for example, about 1/1000). However, even if the conventional device is used in such a wide dynamic range, the following inconvenience occurs and it is difficult to actually use the device.

In order to reduce the flicker of the fluorescent light source, it is desirable that the cycle of the control signal be as small as possible. By the way, if the duty ratio of the control signal is gradually changed, the number of cycles of the AC signal included in one burst signal gradually decreases. In order to turn on the fluorescent lamp, from the point of view of its life, the two electrodes A and B facing each other of the fluorescent lamp (from A to B
And then B to A). Therefore, it is desirable that the drive signal is an alternating signal and does not include a DC component. However, since there is no continuity between the final phase of one burst signal and the initial phase of the next burst signal, a DC component may appear. For example, when the positive period of the burst signal waveform is larger than the negative period. When the number of cycles contained in the burst signal is large, even if the above-mentioned DC component appears, it is very small and does not pose a problem, but if the number of cycles decreases to several cycles or even half cycles, this DC component may appear large. Yes, significantly shorten the life of the fluorescent light. Therefore, such a signal cannot be used.

In order to reduce the DC component contained in the fluorescent lamp drive signal, although better to maximize the number of cycles included in the burst signal, but the frequency of the AC signal from the discharge time constant of the fluorescent lamp approximately 40K _Hz Is the limit. In order to set the dimming ratio to the minimum (1 / n), when the duty ratio D is set to 1 / n, the number of cycles included in the burst signal is α
Then, the on-time Δ of the gate signal is Δ = α × T (1). Here, T is the period of the AC signal (frequency is f), and T = 1 / f. In order that the duty ratio D can be varied and dimming can be performed in the range of 1 / n to n / n, the cycle of the control signal of the gate circuit 2 (equal to the cycle of the clock signal) T _c
Must be T _c = Δ × n = αT n (2) Therefore, the frequency f _{c of the} control signal is Becomes In order to set the minimum dimming ratio 1 / n small, n must be increased.
It is necessary to reduce f _c , but in order to reduce the flickering of the fluorescent lamp, f _c cannot be smaller than about 50 Hz, for example. As an example, Is given, the minimum dimming ratio 1 / n can be calculated from equation (3). Becomes In order to further reduce the minimum dimming ratio 1 / n, the number of cycles α included in the burst signal must be made smaller than α = 4. However, if this is done, it is composed of a large number of burst signals. Between the sum of the positive period and the sum of the negative period of the drive signal waveform, that is, the total time of discharging from electrodes A to B and the total time of discharging from B to A in the fluorescent lamp. The imbalance between them may increase and the life of the fluorescent lamp may decrease.

Further, the phase of the AC signal (frequency f) at the rising and falling edges of the burst signal is not limited to 0, π or an integral multiple thereof, but is cut off in the middle of the peaks and valleys of the waveform and becomes discontinuously zero. . When the fluorescent lamp is driven by such a signal, the power efficiency of the fluorescent lamp dimming device may generally be deteriorated when the cycle number α included in the burst signal is small.

As described above, in the conventional technique, when the minimum dimming ratio is reduced, AC driving for the fluorescent lamp becomes incomplete, which may shorten the life and deteriorate the power efficiency.
There is a drawback that the minimum dimming ratio cannot be set small.

By the way, the liquid crystal display device is also driven by alternating current for its display from the viewpoint of life, but its driving frequency is 30 to 300 Hz for refreshing information or scanning driving. In order to reduce the minimum dimming ratio 1 / n in the fluorescent light control device, the frequency f _{c of the} control signal is, for example, 50 Hz as described above.
It must be reduced to a certain degree. When a fluorescent lamp lighting device driven by this light control device and having no flicker by itself is used as a light source in a liquid crystal display device, the driving frequency of the lighting device,
That is, since the repetition frequency of the burst signal (equal to the frequency f _{c of the} control signal) and the drive frequency of the liquid crystal have the same magnitude, interference occurs between them. However, the dimming ratio P /
If n is small, it does not matter much, but as the dimming ratio P / n is increased, flicker appears and gradually increases.
Give interference. The reason is that the larger the dimming ratio,
This is because the brightness of the liquid crystal display is increased and flicker is easily noticeable.

An object of the present invention is to set the minimum dimming ratio 1 / n smaller than the conventional one, that is, the dynamic range of dimming can be greatly expanded as compared with the conventional one, and a fluorescent lamp dimming that does not cause flicker in the liquid crystal display device. To provide a device.

"Means for Solving Problems" In the fluorescent light control device of the present invention, a clock generator having a minimum lighting time of the fluorescent lamp as one cycle, and 0 to n (n is a positive integer, 1 / n represents the minimum dimming ratio) and the dimming ratio setter for setting the integer P of
A counter that is reset each time it counts is compared with a numerical value R'obtained by reversing the bit arrangement sequence from the maximum bit to the minimum bit of the count value R of the counter and the setting value P of the dimming ratio setting device. When P> R ', it turns on, A comparator that outputs a control signal that is turned off at the time of, and a first output that alternately outputs an on signal having the same time length as the period T of the clock signal in synchronization with the clock signal during the on period of the control signal. A distribution logic circuit having a second output terminal and an inverter that outputs a fluorescent lamp driving signal whose polarity is inverted every time the outputs of the first and second output terminals thereof are supplied as a control signal are provided.

"Embodiment" As will be described in detail below, a fluorescent lamp dimmer according to the present invention outputs a fluorescent lamp drive signal that is completely converted into an alternating current and does not include a direct current component. The fluorescent lamp discharges from the electrode A to the electrode B or from the electrode B to the electrode A according to the positive or negative polarity of the drive signal. The minimum duration of time that the fluorescent light will illuminate is approximately equal to the duration of its positive or negative half-wave of the drive signal and is termed the minimum duration of lighting.

FIG. 1 is a block system diagram showing an embodiment of the present invention. A clock signal is applied from the clock generator 3 to the control signal generation circuit 6. The period T of the clock signal is set equal to the minimum lighting time of the fluorescent lamp. Minimum dimming ratio 1 / n
(N is an integer), the numerical value P of the numerator of the dimming ratio P / n (P = 0 to n) is preset in the dimming ratio setting device 7, and the dimming ratio setting device 7 sets the value. The value P is given to the control signal generation circuit 6.

When the minimum dimming ratio is set to 1/7 (hence n = 7), if the set dimming ratio P / n is sequentially changed to 1/7, 2/7, ..., 7/7, the control signal From the generating circuit 6, the C, D, ...
.., I is output as the control signal C. In the figure, A is a clock signal, and B is a signal obtained by dividing the clock signal by half.

In the same figure C (when P / n = 1/7), the control signal C is synchronized with the clock signal (frequency f _k , period T = 1 / f _k ) and every n = 7 clock signals are input. , Square wave of time width T is output. The number N of square waves in a unit time is given by N = _fk / n = _fk / 7 (5). The frequency f _c of the control signal C is f _c = N = f _k / 7.

When the dimming ratio is set to P / n = 2/7, as shown in D of the same figure, the control signal C is synchronized with the clock signal at approximately the middle position of the adjacent square waves in the case of C of the same figure. Then, a new square wave (marked with *) is added. Although the repetition period of the square wave in the control signal C is not constant, if the term “frequency” is continuously used to mean the number of square waves per unit time, the frequency f _{c of the} control signal is f _c = 2N = 2f _k / 7.

When the dimming ratio is set to P / n = 3/7, as shown in FIG. 6E, the clock signal is set to the middle position of the longest interval among the adjacent square wave intervals as shown in FIG. A new square wave (marked with *) is added in synchronization. The frequency f _{c of the} control signal is f _c = 3N = 3f _k / 7.

When the dimming ratio is set to P / n = 4/7, a new square wave (in the middle of the maximum adjacent interval in the square wave of FIG. (Marked with *) is added. Since this added square wave is connected to the first square wave of the next nT section, the number of square waves per unit time, that is, the frequency f _c of the control signal is the same as in the case of FIG.

When the dimming ratio is set to P / n = 5/7, one new square wave (nT) is added to one of the maximum intervals of adjacent square waves in FIG. Per section) will be added. Since the added square wave is connected to the square waves before and after it, the number of square waves in the nT section is reduced by one from the case of F in the figure, and 2
It becomes an individual. Therefore, the frequency f _{c of the} control signal is f _c = 2N = 2f _k / 7
Becomes

When the dimming ratio is set to P / n = 6/7, a new square wave with time length T is added in the middle of one of the maximum intervals of adjacent square waves in FIG. The added square wave is connected to the square waves before and after, and the number of square waves in the nT section is decreased by one to become one, and the frequency f _{c of the} control signal is increased.
Is f _c = N = f _k / 7.

When the dimming ratio is set to P / n = 7/7 (I in the same figure), one square wave is added as in the case of H in the same figure, and it is connected to the square waves before and after the control signal C. Is a DC signal with all square waves connected.

As described above, in the control signal C, as the set value P / n of the dimming ratio increases by 1 / n pitch from the minimum dimming ratio 1 / n, the adjacent square wave (time length) in each nT section is increased. One square wave (time length T) is added in synchronization with the clock signal at one center position of the maximum interval of T). The frequency f _{c of the} control signal is generally In the range of, f increases with P, and f _c = P × N = P × f _k / n (6). Further, when P> n / 2, f _c becomes f _c = (n−P) × N = (n−P) × f _k / n (7), and decreases as P increases.

FIG. 3 shows the waveform of the control signal C and the frequency f _c of the control signal when the dimming ratio P / n is changed when n = 8. n =
Since it is the same as FIG. 2 in the case of No. 7, its explanation is omitted.

In this way, when the control signal generation circuit 6 is supplied with the dimming ratio P / n (the minimum dimming ratio 1 / n and the numerator P of the dimming ratio P / n) and the clock signal (cycle T), When P = 1, a square wave with a time width T is output every time n clock signals are received, and every time P increases by 1, the adjacent square wave in the nT section in the control signal before that is output. A signal to which one square wave having a time width T is added is output in synchronization with the clock signal at approximately one center position of the maximum interval. Control signal frequency
f _c is Is expressed by equation (6), and when P> n / 2 is expressed by equation (7).

Such a control signal generation circuit 6 is configured as follows, for example. That is, as shown in FIG.
It is counted by the counter 6a. The counter 6a is reset to zero each time it counts n clock signals (1 / n is the minimum dimming ratio). A binary signal (when expressed as a decimal number) in which the order of arrangement of bits from the most significant bit (MSB) to the least significant bit (LSB) of the count output of the counter 6a (denoted by R when expressed as a decimal number) is reversed. R ') is applied to one input of the comparator 6b, and the dimming ratio setter 7 is applied to the other input.
A set value P (an integer of 0 to n) is given by the above. Comparator 6b
Compares these two input signals and outputs an ON signal (for example, a high level signal) if P> R ′ (8), If so, an off signal (for example, a low level signal) is output. The output of the comparator 6b is the control signal C already described. Let's talk about it next.

As an example, set the dimming ratio to P / n = 0,1 / 8,2 / 8, ..., 8/8
Consider the case of changing to. The counter 6a is reset to zero every n = 8 clock signals. Since 2 ³ = 8, the counter 6a has binary 3 digits. As shown in FIG. 4A, when the clock signal is input to the counter 6a, its count output (binary number) becomes as shown in FIG. 4B. 10 in parentheses
It is a value R expressed in a decimal number. Count output of counter 6a (2
By reversing the bit arrangement order of the (adic number), the binary number shown in FIG. The value in parentheses is the value R'expressed in decimal. The binary signal obtained by this inversion is given to one input terminal of the comparator 6b. The comparator 6b compares this input R'with the input P of the other input terminal, and P> R 'or Accordingly, the ON signal and the OFF signal having the time width T are output. In FIG. 6D, the output C of the comparator 6b is shown only by turning on the ON signal. (Locations without circles are off signals.) When P = 0, always Therefore, the output C is always off.

Then, when R '= 0, P>R' is satisfied, and C = 1 (○
Means the ON signal).

Then (of course, when R '= 0), when R' = 1, P
> R ′ is satisfied, and C = 1.

Then (of course, when R '= 0,1), when R' = 2, P> R 'is satisfied and C = 1.

Then (of course, when R '= 0,1,2), when R' = 3, P> R 'is satisfied, and C = 1. (The same applies to the following.) As is clear from FIG. 4, as P increases by 1, a new one is created at the center position of one of the longest periods in the output C before the nT section. ON signal (time width T) of is added. This added ON signal is indicated by * mark in FIG. When P = 8, one new ON signal is added, and C = 1 always.

In the case of n = 7, except that the counter 6a is reset to zero every time n = 7 clock signals are input, n in FIG.
= 8 is the same. As described above, the control signal generating circuit 6 can be easily configured by the counter 6a and the comparator 6b.

The output of the control signal generation circuit 6, that is, the control signal C and the clock signal (cycle T) are given to the distribution logic circuit 8, and the distribution logic circuit 8 outputs the control signal of the control signal C as shown in FIGS. During the ON period, ON signals M and Q having the same time length as the period T of the clock signal are output from the first and second output terminals 8a and 8b in synchronization with the clock signal. FIG. 5 shows the case of n = 7 and P = 2 shown in FIG. 2D, FIG. 6 shows the case of n = 8 and P = 6 shown in FIG. 3H, and FIG. Shows the case of n = P = 8 shown in FIG. 3J.

The distribution logic circuit 8 which operates in this manner is configured as shown in FIG. 1, for example. That is, the signal A obtained by dividing the clock signal in half is supplied from the LSB output terminal of the counter 6a. (However, this signal A may be obtained by dividing the clock signal 3a into 1/2 by a flip-flop (not shown) separately.) This signal A and its inverted signal are respectively supplied to one of the AND gates 8c and 8d. A control signal C is applied to the other input terminal. The inverted signal of the control signal C and the clock signal 3a are given to the AND gate 8e, the output signal E thereof is given to the flip-flop circuit 8l, and the flip-flop circuit 8l divides the input signal E into 1/2. Is output. The output AC of the AND gate 8c is given to one input terminal of each AND gate 8f, 8i, the output C of the AND gate 8d is given to one input terminal of each AND gate 8g, 8h, and the output of the flip-flop circuit 8l. F is given to the other input terminal of AND gates 8f and 8g, and the inverted signal of output F is AND gates 8h and 8i.
Applied to the other input terminal of. Signals represented by ACF and C are OR gates from AND gates 8f and 8h, respectively.
8j, and from its output, a signal M represented by M = ACF + C (10) is applied to the first output terminal 8a. On the other hand, the signals represented by CF and AC are applied to the OR gate 8k from the AND gates 8g and 8i, respectively, and the signal Q represented by Q = CF + AC (11) is applied to the second output terminal 8b from its output.

The signals of the respective parts of the distribution logic circuit 8 are shown in FIG. 8 by taking the case of n = 8 and P = 2 as an example. As is clear from the figure,
The distribution logic circuit 8 distributes the ON signal of the control signal C to the first and second outputs M and Q and alternately outputs them for each T time. It can be well understood from the following equation (12) that the control signal C is distributed to M and Q.

The first and second outputs M and Q of the distribution logic circuit 8 are given to the inverter 9 as control signals, and are output from the inverter 9 as shown in FIGS. 5E, 6E, 7E and 8N. The half-wavelength is equal to T, the AC signal is completely converted into AC, and a fluorescent lamp driving signal containing no DC component is output.

The inverter 9 is configured, for example, as shown in FIG. That is, the first and second outputs M and Q of the distribution logic circuit 8 are given to the bases of the transistors 9c and 9d via the resistors 9a and 9b, respectively. The emitters of the transistors 9c and 9d are connected to a common potential point, their collectors are connected to one end and the other end of the first winding of the transformer 9e, and the middle point of the first winding is connected to the DC power supply terminal + B. To be done. Both ends of the second winding of the transformer 9e are connected to the output terminals 5a and 5b. The transistors 9c and 9d are alternately turned on by the input signals M and Q, and the above-mentioned fluorescent lamp drive signal is output between the output terminals 9f and 9g.

Although the case where n = 7 or 8 has been described as an example in the above description, n> 1000 can be similarly set. counter
If 6a is set to 10 digits and is reset every time n = 1024 (= 2 ¹⁰ ) clock signals 3a are input, the minimum dimming ratio 1 /
n becomes 1/1024. Fluorescent lamp drive signal (inverter output)
As is clear from Fig. 7, the maximum frequency of is equal to 1/2 of the clock signal frequency f _k . Therefore, considering the discharge time constant of the fluorescent lamp, the frequency of the clock signal 3a is set to f _k = 80K _Hz . Then, the frequency f _c of the control signal C when the dimming ratio P / n is set to the minimum dimming ratio 1 / n is f _c = N = f _k / n = 80 × 10 ³ /102478.1Hz (13) Becomes Next, the repetition frequency f ₀ of the AC half-wave of the fluorescent lamp driving signal that has been converted into an alternating current is obtained. Assuming that the dimming ratio is P / n, as is clear from FIGS. 5 to 7, the total ON period of the control signal C per nT section is P × T, and therefore positive and negative AC The total number of half waves is P per nT section. Therefore, the repetition frequency f ₀ of the AC half wave is f ₀ = P / nT = (P / n) × f _k = P × N (14). In the above example, f ₀ = P × NP × 78.1 (P = 0,1,2, ... 1024) (15). In this way, the AC half-wave repetition frequency f ₀ increases in proportion to the dimming ratio P / n. Therefore, the driving frequency of the liquid crystal display element (30 to 300 Hz) is gradually increased (for example, P
= 100 becomes f ₀ 7810Hz) There is no visual interference between the mutual frequencies, and flicker does not occur.

In the present invention, in addition to the flicker prevention function described above, a function of finely adjusting or varying the frequency of the clock generator 3 so that flicker does not occur can be used together.

[Effect of the Invention] According to the present invention, even if the minimum dimming ratio 1 / n is set small, the positive half-wave and the negative half-wave of the fluorescent lamp drive signal are always repeated alternately, There is no possibility that the life of the fluorescent lamp will be shortened due to the imbalance between the sum of the positive period and the sum of the negative period as in the conventional case. The AC half-wave, which is the minimum unit that constitutes the fluorescent lamp drive signal, is synchronized with the clock signal, has a time length equal to the clock signal period T, and both the rising and falling edges of the waveform are zero. Even if the optical ratio 1 / n is reduced, the waveform is cut in the middle of the peaks or valleys at the rising and falling of the burst signal as in the past.
It becomes zero discontinuously and does not deteriorate the power efficiency of the fluorescent light control device. Therefore, according to the present invention, it becomes possible to set the minimum dimming ratio to be considerably smaller than the conventional one,
The dynamic range of the device can be greatly expanded. According to the present invention, the repetition frequency f ₀ of the AC half-wave of the fluorescent lamp driving signal increases in proportion to the dimming ratio. Even if the liquid crystal display is brightened by increasing the dimming ratio and the flicker becomes a conspicuous condition, at that time, the repetition frequency f ₀ of the AC half wave is equal to the driving frequency of the liquid crystal display element (30
.About.300 Hz), for example, by one digit or more, the difference between frequencies becomes large, and flicker does not occur unlike the conventional case.

[Brief description of drawings]

FIG. 1 is a block system diagram showing an embodiment of a fluorescent lamp dimming device of the present invention, and FIG. 2 is a first diagram when a dimming ratio P / n is changed between 1/7 and 7/7. 3 is a waveform diagram of the control signal C in the figure,
The figure shows the first when the dimming ratio P / n is changed between 1/8 and 8/8.
FIG. 4 is a waveform diagram of the control signal C in the figure, FIG. 4 is a diagram for explaining the operation principle when the control signal generating circuit 6 of FIG. 1 is configured by a counter and a comparator, FIG. 5, FIG. 7th
The figure shows the waveform diagram of each output signal of the distribution logic circuit 8 and the inverter 9 in FIG. 1 when the dimming ratio P / n is set to 2/7, 6/8 and 8/8, respectively. FIG. 1 is a waveform diagram of an essential part for explaining the operation of the distribution logic circuit 8 in FIG. 1, FIG. 9 is a block system diagram of a conventional fluorescent lamp dimming device, and FIG. 10 is an operational waveform of the essential part in FIG. It is a figure.

Claims (1)

[Claims] 1. A clock generator having a minimum lighting time of a fluorescent lamp as one cycle, and an integer P of 0 to n (n is a positive integer, 1 / n represents a minimum dimming ratio). The dimming ratio setter, the counter reset every time the clock signal of the clock generator is counted n, and the bit arrangement order from the maximum bit to the minimum bit of the count value R of the counter are obtained by reversing the order. The numerical value R'is compared with the set value P of the dimming ratio setting device, and when P> R ', it is turned on, And a comparator that outputs a control signal that is turned off when the control signal is ON, and that alternately outputs an ON signal whose period is equal to the period T of the clock signal in synchronization with the clock signal during the ON period of the control signal. A distribution logic circuit having a second output terminal, and an inverter that outputs a fluorescent lamp driving signal whose polarity is inverted every time the outputs of the first and second output terminals are supplied as a control signal. Fluorescent light control device.