JPH07154440A - Demodulator - Google Patents

Abstract

PURPOSE:To quickly restore the normal state after disappearance of a interference wave in the case of a strong intermittent interference wave like a radar wave in the demodulator used in a digital radio transmission system. CONSTITUTION:The reception input signal level is monitored by a detector 11, a low pass filter 13, and a voltage comparator 15, and the level of the clock component extracted from the reception input signal is monitored by a detector 12, a low pass filter 14, and a voltage comparator 16. If a strong interference wave interferences, the input signal level is increased but the extracted clock component level is reduced. This state is detected by an AND circuit 17, and the input offset control voltage of an AID converter 8 is switched to a standard voltage by a control voltage switch 18. Thus, saturation of the offset voltage is prevented, and the normal state is quickly restored after disappearance of the interference wave.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator, and more particularly to a demodulator used in a digital radio transmission system.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional demodulator used in a digital radio system. In FIG. 2, the received modulated wave input from the signal input terminal IN is amplified to a constant amplitude by the automatic gain control amplifier 1. Then, the reproduced carrier wave input from the local oscillator input terminal LO is multiplied by the multiplier 2. Then, the output signal of the multiplier 2 becomes a demodulated baseband signal after unnecessary harmonics are removed by the low-pass filter 3.

This demodulated baseband signal is amplified by a voltage control amplifier 4 to an amplitude suitable for an analog-digital converter 8 described later, and an offset control circuit 9 is also provided.
An appropriate offset voltage is given in accordance with the offset control voltage by. After this, the analog-digital converter 8
Is converted into a digital signal after being sampled and quantized by the burst error corrector 10 and the error is corrected by the burst error corrector 10.
It is output to T.

A clock component is extracted from the output of the voltage controlled amplifier 4 by the non-linear circuit 5 and the band pass filter 6. If the received input is, for example, a QPSK modulated signal,
Since the doubled wave (second harmonic) of the demodulated baseband signal becomes the clock component, the nonlinear circuit 5 performs the doubled operation and the bandpass filter 6 extracts the clock component. is there.

This clock component is supplied to the clock synchronization circuit 7
And a demodulated clock synchronized with this clock component is output by the clock synchronization circuit 7. The output of this clock synchronization circuit becomes the sampling clock signal of the analog-digital converter 8.

[0006]

However, in the above-mentioned conventional demodulator, when the interference is caused by a strong intermittent interference wave such as a radar wave, the offset voltage follows the offset level of the interference wave and reaches the saturation region. fluctuate.

Therefore, even if the interference time of the interfering wave itself is within the correctable range of the burst error corrector, it takes time for the offset voltage saturated at the time of interference to return to the normal state, and the burst error time has an error correction capability. There was a problem that it may exceed.

It is an object of the present invention to provide a demodulation system that quickly restores the offset voltage to the normal state even by the interference of strong intermittent disturbance waves.

[0009]

According to the present invention, there is provided a demodulator in a digital radio transmission system, which is an automatic gain control means for maintaining a received input signal at a constant level.
A means for converting the output of the automatic gain control means into a demodulation baseband signal by using a reproduction carrier, an offset giving means for giving an offset voltage according to an offset control voltage to the demodulated baseband signal, and an offset giving means. Clock extracting means for extracting a clock component from the output of the analog output, analog-digital converting means for converting the output of the offset applying means into a digital signal using the extracted clock as a sampling clock, and an input offset of the analog-digital converting means for the receiving input Means for generating the offset control voltage so as to maintain the level according to the level of the signal, and first comparing means for comparing the level of the received input signal with a first reference level.
A second comparison means for comparing the level of the extracted clock component by the clock extraction means with a second reference level, and the offset control voltage is kept constant according to the comparison result of the first and second comparison means. A demodulation device is obtained which includes control means for controlling the value.

[0010]

In the demodulator in the digital radio transmission system according to the present invention, the level increase of the input signal and the decrease of the extracted clock component, which occur when strong interference occurs, are detected by two level comparing means, respectively. When the two occur simultaneously, the input offset voltage of the analog-digital converter is fixed to a constant value which is smaller than the saturation level. By doing so, it becomes possible to quickly return to the normal state after the disturbance wave disappears.

[0011]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a demodulator according to the present invention. In this figure, the components denoted by reference numerals 1 to 10 are the same as those shown in FIG. 2, and detailed description thereof will be omitted.

That is, IN is a signal input terminal, LO is a local input terminal, 1 is an automatic gain control amplifier, 2 is a multiplier, 3 is a low-pass filter, 4 is a voltage control amplifier, 5 is a non-linear circuit, and 6 Is a band pass filter, 7 is a clock synchronization circuit, 8 is an analog-digital converter, 9 is an offset control circuit, and 10 is a burst error corrector.

In this embodiment, in addition to the demodulator of the prior art, detectors 11 and 12, low-pass filters 13 and 14, voltage comparators 15 and 16, an AND circuit 17, and a control voltage switch 1 are provided.
Eight.

Then, the input signal is input to the detector 11, the output of the detector 11 is input to the low-pass filter 13, and the output of the low-pass filter 13 is input to the voltage comparator 15 and REF.
1 is compared with the reference voltage input.

On the other hand, the output of the bandpass filter 6 is the detector 1
2, the output of the detector 12 is input to the low-pass filter 14, and the output of the low-pass filter 14 is input to the voltage comparator 16 and compared with the reference voltage input from REF2. The outputs of the voltage comparators 15 and 16 are both input to the AND circuit 17, and the output of the AND circuit 17 is input to the control voltage switch 18. The control voltage switch 18 switches the offset control voltage output to the voltage control amplifier 4 by the output of the AND circuit 17 from the output of the offset control circuit 9 to the reference voltage input from REF3.

According to the configuration of FIG. 1, a strong interfering wave which saturates the offset voltage, on the other hand, greatly increases the input signal level which is the sum of the desired wave and the interfering wave. Along with this, the gain of the automatic gain control amplifier 1 decreases, so that the clock component extracted from the desired wave by the nonlinear circuit 5 and the bandpass filter 6 decreases. As a result, the output voltage of the low-pass filter 13 greatly increases from the standard level, and the low-pass filter 1
The output voltage of 4 decreases.

Next, when there is no interfering wave and the input signal level increases due to a change in the received electric field strength or the like, the output voltage of the low-pass filter 13 increases or decreases, but the automatic gain control amplifier 1 causes the multiplier 2 to operate. Since the input level to the low-pass filter 14 is kept constant, the output voltage of the low-pass filter 14 does not change from the standard level.

When there is no interfering wave and the clock component extracted by the frequency selective fading decreases, the output voltage of the low-pass filter 14 decreases, but the increase of the input signal level is small, so that the low-frequency level is low. The output voltage of the filter 13 does not increase significantly.

That is, an appropriate voltage higher than the normal output voltage of the low-pass filter 13 is used as the reference voltage of REF1.
If an appropriate voltage lower than the normal output voltage of the low-pass filter 14 is selected as the output voltage of 2, the high level is output to the voltage comparators 15 and 16 only when a strong disturbance wave is input, and the logical product is obtained. A switching control signal is output from the circuit 17.

The switching control signal output from the AND circuit 17 is input to the control voltage switch 18, and the offset control voltage input to the voltage control amplifier 4 is input to the REF 3 instead of the output of the offset control circuit 9. Switch to standard offset voltage.

On the other hand, when the interfering wave disappears, the switching control signal is inverted, and the control voltage switch 18 switches the offset control voltage to the output of the offset control voltage 9 instead of the standard offset voltage. In this case, the time required for the offset voltage to converge from the standard offset voltage to the optimum offset voltage is much shorter than the time required to converge from the saturation voltage to the optimum offset voltage. This state is shown in FIG.

As a result, the offset voltage is not saturated while the interfering wave is input, and the offset can be promptly restored after the interfering wave disappears.

As the received input signal, a signal of 16QAM modulation system or other various modulation systems can be applied in addition to the signal of QPSK modulation system.

[0025]

As described above, according to the present invention, when interference is caused by a strong interference wave, it has an effect of promptly returning to the normal state after the interference wave disappears.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional demodulator.

FIG. 3 is a diagram showing an offset voltage waveform.

[Explanation of symbols]

 1 Automatic gain control amplifier 2 Multiplier 3 Low-pass filter 4 Voltage control amplifier 5 Non-linear circuit 6 Band pass filter 7 Clock synchronization circuit 8 Analog-digital converter 9 Offset control circuit 10 Burst error corrector 11, 12 Detection Device 13,14 Low-pass filter 15,16 Voltage comparator 17 AND circuit 18 Control voltage switching device

Claims (3)

[Claims] 1. A demodulator in a digital radio transmission system, wherein automatic gain control means for maintaining a received input signal at a constant level, and an output of the automatic gain control means is converted into a demodulated baseband signal by using a reproduced carrier wave. Means, an offset giving means for giving an offset voltage according to the offset control voltage to the demodulated baseband signal, a clock extracting means for extracting a clock component from the output of the offset giving means, and a sampling clock for the extracted clock. As an analog-digital conversion means for converting the output of the offset applying means into a digital signal, and a means for generating the offset control voltage so that the input offset of the analog-digital conversion means is maintained at a level corresponding to the level of the received input signal. Of the received input signal A first comparing means for comparing the bell with a first reference level; a second comparing means for comparing the level of the extracted clock component by the clock extracting means with a second reference level; A demodulation device including control means for controlling the offset control voltage to a constant value in accordance with the comparison result of the second comparison means. 2. The first comparing means detects that the level of the received input signal is higher than the first reference level, and the second comparing means detects the level of the extracted clock component. 2. The demodulator according to claim 1, wherein the control means is configured to set the offset control voltage to a constant value when it is detected that it is lower than the second reference level. . 3. The demodulator according to claim 1, wherein the offset voltage which is a constant value by the control means is a value smaller than a saturation level of the offset voltage.