JPH07152565A - Microprocessor - Google Patents

Abstract

PURPOSE:To eliminate such a cycle where the data written by a precedent instruction are read by a subsequent instruction by actuating the subsequent instruction with no waiting time by transferring data between buses when the subsequent instruction refers to the register to be updated by the precedent instruction during the operation of a pipeline. CONSTITUTION:A microprocessor is provided with a bus 20 which transfers the write data on a precedent instruction during the operation of a pipeline, a bus 21 which is set separately from the bus 20, a bypass control circuit 13 which controls the transfer of data between both buses 20 and 21, a bus emission buffer 11 which emits the data on the bus 20 to the bus 21 by an instruction of the circuit 13, a register file 10 where the write data on the bus 20 are written, and a bus emission buffer 12 which controls the output of the read data read out of the file 10 to the bus 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor which has a bus inside and operates by pipeline control, and more particularly to speeding up the pipeline.

[0002]

2. Description of the Related Art In a conventional microprocessor, when a register to be updated by a preceding instruction is referred to by a succeeding instruction, the succeeding instruction reads the register updated by the preceding instruction.

[0003]

In the conventional microprocessor described above, the write data of the preceding instruction is written in the register and then read by the succeeding instruction, so that the succeeding instruction is kept waiting during that time, and the pipeline becomes empty. was there.

[0004]

According to a first aspect of the present invention, there is provided a first microprocessor for transmitting write data of a preceding instruction in a microprocessor having a bus therein and operating by pipeline control.
Bus, a second bus existing for each of the first buses, a control circuit for controlling data transfer between the first and second buses, and a control circuit for controlling the first bus according to an instruction from the control circuit. First to emit data to the second bus
Bus emission buffer, a register for writing write data of the first bus, and a second bus emission buffer for controlling output of read data read from the register to the second bus. It is characterized in that data is transferred between the first and second buses. Further, an event in which the result of the preceding instruction is used by the succeeding instruction may be detected one cycle before to transfer the data between the first and second buses.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which a part of a microprocessor operating by pipeline control is simplified. First, the write data of the preceding instruction flowing through the pipeline is output from the result storage register 15 as the data A to the bus 20. Here, the bypass control circuit 13 receives the write address A of the preceding instruction from the pipeline control unit 14 via the write address data line 24 one clock before the data is output to the bus 20, and at the same time, receives the write address A of the succeeding instruction. The read address B is received from the pipeline control unit 14 via the read address data line 25.

The bypass control circuit 13 having received each address sends the write address to the register file 10 via the write address data line 22 at the timing of the next clock. The register file 10 receiving the write address receives the data A output to the bus 20 via the data line 28, and writes the data A according to the write address. Further, the bypass control circuit 13 that has received the address detects whether or not the write address A and the read address B match one clock before the data is output to the bus 20, and performs the following operation.

The pipeline controller 14 sends an interrupt instruction signal to the control signal line 26. This interrupt instruction signal is sent when the pipeline operation is temporarily stopped, and becomes an interrupt when it is "1". Next, the operation both when an interrupt occurs and when it does not occur will be described.

First, when no interrupt occurs, that is, when the interrupt instruction signal sent from the control signal line 26 is "0", the bypass control circuit 13 causes the control signal line 2 to operate.
9. The bus emission signal is sent to each of the control signal lines 30, but the bus emission signal A sent to the control signal line 30 becomes "1" when the address match is detected, and otherwise "1". Becomes 0 "and the bus emission signal B sent to the control signal line 29 is always" 0 ".
become. The bus emission buffer 11 receives the data A on the bus 20 via the data line 27 and sends the data A to the bus 21 when the bus emission signal sent via the control signal line 30 is “1”. .

Next, if there is an interrupt, that is,
When the interrupt instruction signal sent from the control signal line 26 is “1”, the bypass control circuit 13 controls the control signal line 2
9. The bus emission signal is sent to each of the control signal lines 30, but the bus emission signal A sent to the control signal line 30 is always "0", and the control signal line 29
When the interrupt instruction disappears, that is, when the interrupt instruction signal transmitted from the pipeline control unit 14 via the control signal line 26 changes from "1" to "0". Becomes "1", and otherwise becomes "0".

The bypass control circuit 13 holds the read address B during the interrupt instruction and sends it to the register file 10 via the read address data line 23. The register file 10 is caused by the read address B before the interrupt occurs. The data A written in the register file 10 is read out and sent to the read data line 31. The bus emission buffer 12 has a control signal line 2
When the bus emission signal B sent via 9 becomes “1”, the data A sent from the read data line 31 is sent to the bus 21. Bus 2 in this way
The data output to 1 is taken into the resource register 16 as the resource of the subsequent instruction.

[0011]

As described above, the present invention enables the transfer of data between buses so that the succeeding instruction can refer to the result of the preceding instruction without making a space in the pipeline. Further, by detecting the event that the result of the preceding instruction is referred to by the subsequent instruction one cycle before, the increase in the clock cycle due to the delay required to detect the event that the result of the preceding instruction is referred to by the subsequent instruction is prevented. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 10 register file 11, 12 bus emission buffer 13 bypass control circuit 14 pipeline control unit 15 result storage register 16 resource register 20, 21 bus 22, 24 write address data line 23, 25 read address data line 26, 29, 30 control signal Line 27, 28 Data line 31 Read data line

Claims (2)

[Claims] 1. A micro-processor which has a bus inside and operates under pipeline control, wherein a first bus for transmitting write data of a preceding instruction and a second bus existing separately from the first bus. Bus, a control circuit for controlling data transfer between the first and second buses, and a first bus for emitting data of the first bus to the second bus according to an instruction from the control circuit. An emission buffer, a register for writing write data of the first bus, and a second bus emission buffer for controlling output of read data read from the register to the second bus are provided. A microprocessor for transferring data between the second buses. 2. The data transfer between the first and second buses is performed by detecting the event that the subsequent instruction uses the result of the preceding instruction one cycle before.
The described microprocessor.