JPH07152503A - Semiconductor disk device - Google Patents

Abstract

PURPOSE:To improve the reliability of a semiconductor disk device by decreasing the number of error parts included in the data to undergo an ECC operation down to only one or less. CONSTITUTION:A date string 101a stored in the higher order bit side of the first row of a flush EEPROM 11 and a data string 101b stored in the lower order bit side belong to the ECC operational groups A and B respectively. Meanwhile a data string 102a stored in the higher order bit side of the second row of the EEPROM 11 and a data string 102b stored in the lower order bit side belong to the ECC operational groups B and A respectively. In such a constitution, only one defective cell is included in each ECC operational group even though the defective cells occur at the same bit positions of plural rows of the EEPROM 11. As a result, the data can be easily recovered by the ECC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor disk device, and more particularly to a semiconductor disk device having a flash EEPROM which is an electrically batch erasable non-volatile semiconductor memory.

[0002]

2. Description of the Related Art Many conventional information processing apparatuses such as workstations and personal computers use magnetic disk devices as storage devices. The magnetic disk device has advantages such as high recording reliability and a low bit unit price, but has drawbacks such as a large device size and weak physical shock.

The magnetic disk device has an operating principle of magnetically writing data on a rotating disk or reading them by running a magnetic head on the disk surface. Mechanically movable parts such as the rotating disk and the magnetic head may naturally malfunction or fail due to physical impact on the device. Further, the need for such a mechanically movable portion is an obstacle to reducing the size of the entire device.

For this reason, the magnetic disk device does not hinder the use of a desktop type computer fixedly mounted on a desk, but in the case of a portable and small laptop computer or notebook computer, these drawbacks are encountered. Is a big problem.

Therefore, in recent years, attention has been focused on a semiconductor disk device which is small in size and resistant to physical shock. The semiconductor disk device is a flash EEPR that is a non-volatile semiconductor memory that can be electrically collectively erased.
The OM is used as a secondary storage device such as a personal computer like the conventional magnetic disk device. Since this semiconductor disk device does not have a mechanically movable part like a magnetic disk device, malfunctions and failures due to physical shocks are unlikely to occur. Further, there is an advantage that the size of the device is reduced.

In such a semiconductor disk device, an ECC calculation function is provided, and the flash EE is used.
An ECC corresponding to the sector data written in the PROM is added. FIG. 8 shows a typical sector data format of a conventional semiconductor disk device having such an ECC calculation function.

As shown in FIG. 8, 512-byte sector data is stored in two rows of the flash EEPROM 1, and the sector data is followed by an EC.
C is stored. Sector data is flash EEP
How many rows of ROM1 are stored depends on the flash EE
Although it depends on the physical size of the PROM 1, if the largest size 16 Mbit flash EEPROM currently being developed is used, 512 bytes of sector data will be stored in the flash EEPR as shown.
It will be stored over two rows of OM1.

In this case, the ECC operation is executed in the format of the first row and the second row of the sector data, and the ECC calculated by the ECC operation is stored following the data of the second row.

However, in the conventional semiconductor disk device using such a sector format,
Considering the following error occurrence characteristics of a semiconductor memory such as a flash EEPROM, a problem arises in that the ECC operation becomes complicated and error correction cannot be performed.

That is, in a semiconductor memory such as a flash EEPROM, there is an error mode in which not only a specific memory cell but a plurality of memory cells connected to the same bit line are simultaneously defective. This error mode is, for example. It is caused by a defective bit line or a defective contact between the bit line and the cell.

When such an error mode occurs,
As shown in FIG. 8, the flash EEPROM 1
A defective cell is generated at the same bit position in each of the plurality of rows. In this case, in the conventional semiconductor disk device, two data errors are generated in the data to be subjected to the ECC calculation as shown in the figure.

Generally, in error correction using ECC, data can be recovered when there is one error, but it is difficult to correct the error when there are two or more errors. In order to deal with such an error, a complex ECC arithmetic expression having a high data recovery capability is required.

However, if the ECC arithmetic expression is complicated, the structure of the semiconductor disk device becomes complicated and the E
The CC calculation requires a lot of time, which causes a drawback that the data writing speed is reduced.

[0014]

In the conventional semiconductor disk device, if a defective cell is generated at the same bit position in a plurality of rows of the flash EEPROM, the data to be subjected to the ECC operation will include errors at a plurality of locations. Therefore, there is a drawback that the data cannot be recovered by the normal ECC calculation.

Further, a complex ECC having high data recovery capability
The use of the arithmetic expression causes a drawback that the structure of the semiconductor disk device is complicated and that the ECC calculation requires a lot of time, so that the performance is deteriorated in terms of data writing and reading speed.

The present invention has been made in view of the above circumstances, and even if a defective cell is generated at the same bit position in each of a plurality of rows of the flash EEPROM, the data to be subjected to the ECC operation has two or more errors. It is an object of the present invention to provide a semiconductor disk device capable of realizing a high data recovery capability by a simple ECC calculation without including the data.

[0017]

Means and Actions for Solving the Problems
In a semiconductor disk device having a non-volatile semiconductor memory having a multi-bit configuration and accessing the non-volatile semiconductor memory in response to a disk access request from a host device, the non-volatile semiconductor memory is stored in a plurality of rows. Write data is divided into multiple data strings containing different bits along the row direction, and multiple error corrections are performed for multiple operation data groups each composed of multiple data strings containing different bits in different rows. A first means for calculating a code; and a means for adding the plurality of error correction codes to a data string in the last row of each of the plurality of operation data groups and storing it in the nonvolatile semiconductor memory. Characterize.

In this semiconductor disk device, the operation of the error correction code for the write data is executed for each of the plurality of operation data groups. in this case,
The operation data group is composed of a plurality of data strings corresponding to different bit positions in each of a plurality of rows in which write data is stored.

Therefore, even if a defective cell is generated at the same bit position in each of a plurality of rows of the nonvolatile semiconductor memory, only one defective cell is included in each operation data group to be operated by the error correction code. Become. Therefore, it is possible to realize a high data recovery ability by a normal simple ECC operation without using a complicated ECC arithmetic expression having a high data recovery ability.

Further, by providing a plurality of error correction code arithmetic circuits corresponding to the plurality of divided data strings, the plurality of data strings can be processed in parallel by the plurality of error correction code arithmetic circuits. .
In this case, since the plurality of error correction codes corresponding to the plurality of operation data groups are calculated at the same time, the data writing speed to the nonvolatile semiconductor memory will not be reduced.

Further, for example, when the write data is divided into n data strings in the row direction, the data width of each data string is 1 / the data width of the write data.
n. Therefore, since the input data width of each error correction code arithmetic circuit is 1 / n of the data width of the write data,
The circuit scale of each error correction code arithmetic circuit can be small. Therefore, even if n error correction code arithmetic circuits are provided, the number of gates required for that is not increased.

Further, according to the present invention, in a semiconductor disk device having a non-volatile semiconductor memory having a multi-bit structure, the non-volatile semiconductor memory is accessed in response to a disk access request from a host device. The write data having a data size over a plurality of rows is divided for each row, the means for calculating the error correction code to be added to the data of each row, and the data for each row and the error correction code corresponding thereto are described above. And a means for storing in the same row of the nonvolatile semiconductor memory.
It is a feature of.

In this semiconductor disk device, since the operation of the error correction code is completed for each row, the operation of the error correction code is performed even if an error mode occurs in which defective cells occur at the same bit position in a plurality of rows. It is possible to easily limit the number of defective cells included in each target operation data group to 1 or less.

Further, according to the present invention, the nonvolatile semiconductor memory is provided with a function for limiting the number of defective cells included in each ECC operation group to one or less, and the data storage positions are automatically replaced in the nonvolatile semiconductor memory. The third characteristic is that the above configuration is adopted.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a relationship between a flash EEPROM used in a semiconductor disk device according to an embodiment of the present invention and an ECC operation executed on sector data stored in a plurality of rows of the flash EEPROM. Has been done.

This flash EEPROM 11 has × 8
16 Mbit NAND type EEP with bit configuration
A memory cell array 1 that is a ROM and has 8K rows and 264 columns
Eight 12 are provided. Also, in line units, that is, 25
In order to write / read data in 6 + 8 byte page units, a 256 + 8 bit data register 11
Eight 1s are provided. Data is erased in units of 4K bytes + 128 bytes erase blocks.

It is now assumed that sector data having a size of 512 bytes is written over the first row and the second row of the flash EEPROM 11. In this case, in the first row, the upper 4 bits (bit7-4)
The ECC operation A is executed at the time of writing to the data string 101a corresponding to, and the ECC operation B is executed at the time of writing to the data string 101b of the lower 4 bits (bit3-0).

On the other hand, in the second row, the data string 102a corresponding to the upper 4 bits (bit7-4).
, The ECC operation B is executed so as to continue to the data string 101b of the first row, and the lower 4 bits (bit 3-0) of the data string 102b are written.
On the other hand, at the time of writing, the ECC operation A is executed so as to continue to the data string 101a of the first row.

Further, in the second row, following the data string 102a, the error correction code (ECC-B) calculated by the ECC operation B is stored. This error correction code (ECC-B) corresponds to the data strings 101b and 102a, and is calculated including the contents of the error correction code itself. Therefore, if there is an error somewhere in the data strings 101b and 102a and the error correction code (ECC-B), the error is corrected to the error correction code (ECC-B).
It can be corrected by B).

Similarly, after the data string 102b, the error correction code (ECC-A) calculated by the ECC operation A is also stored. This error correction code (ECC-A) is used for the data strings 101a and 1a.
02b, which is calculated including the contents of the error correction code itself. Therefore, if there is an error somewhere in the data strings 101a and 102b and the error correction code (ECC-A), the error can be corrected by the error correction code (ECC-A).

Here, the ECC calculation A and the ECC calculation B are different only in the data to be calculated, and the same calculation formula can be used. Thus, in the semiconductor disk device of this embodiment,
Different ECC calculations are performed on the data at the same bit position in the first and second rows where the sector data is stored. Therefore, even if the above-mentioned error mode occurs in the flash EEPROM 11, each ECC operation group includes only one defective cell.

For example, as shown in the figure, when a cell defect occurs in the second column of the bit 6 from row 1 to row 16, the second column of the bit 6 in each of the first and second rows. Will result in an error.

However, the error location in the first line is EC
It belongs to the group of C operation A, and the error location in the second row belongs to the group of ECC operation B. Therefore,
Only one defective cell is included in each ECC operation group, and a high data recovery ability can be realized by a normal simple ECC operation without using a complicated ECC operation expression having a high data recovery ability.

Next, with reference to FIG. 2, the overall structure of the semiconductor disk device according to the embodiment of the present invention will be described.
This semiconductor disk device 10 is used by being connected to a host system 100 such as a personal computer as an alternative to a hard disk device, and includes flash EEPROMs 11-1 to 11-16 and a controller 20.

Flash EEPROM 11-1 to 11-
Reference numeral 16 is used as a recording medium of the semiconductor disk device 10.
It is composed of an AND type EEPROM 11.

These flash EEPROMs 11-1 to 11-1
11-16 are connected to the controller 20 via a common I / O bus and control signal line. Further, the controller 20 and the flash EEPROMs 11-1 to 11-11
-16 to the chip select signals (CS1 to CS
16) Lines are arranged independently for each chip.

These flash EEPROMs 11-1 to 11-1
In 11-16, as described above, data writing is executed in 256-byte + 8-byte page units,
Data erasing is executed in block units of 4 Kbytes + 128 bytes.

The controller 20 is realized by one LSI, and the LSI chip has a host interface 12, a control circuit 13, and an NA as shown in the figure.
ND interface 14 and data buffer 15
Are formed in an integrated manner.

The host interface 12 communicates with the host system 100 via a pin arrangement conforming to the IDE interface. The host interface 12 is provided with various interface register groups (sector number register, sector count register, data register, cylinder register, drive / head register, command register, status register) for communication with the host system 100. There is. These registers can be read / written by the host system 100.

The control circuit 13 includes an MPU and a local memory in which a firmware program for controlling the operation of this MPU is stored. In response to a disk access request supplied from the host system 100 via the host interface 12, Flash EEPROM 11
Access control of -1 to 11-16.

That is, the MPU of the control circuit 13 reads various commands and parameters set in the register group of the host interface 12 and controls access to the flash EEPROMs 11-1 to 11-16 according to the contents thereof. In this case, the MPU of the control circuit 13 refers to the address conversion table 131 to perform the address conversion from the logical address to the physical address.

The address conversion table 131 contains the logical address from the host system 100 and the flash EEP.
Address conversion information indicating a correspondence relationship with physical addresses for accessing the ROMs 11-1 to 11-16 is defined. Here, the logical address is an address for disk access and is determined by the cylinder number, head number, and sector number. The physical address is an address for selectively accessing the flash EEPROMs 11-1 to 11-16, and is determined by the chip number and the memory address.

The address conversion table 131 is stored in any of the flash EEPROMs 11-1 to 11-16, and is read into the control circuit 13 when the power is turned on. The NAND interface 14 uses the flash E according to the conversion result by the address conversion table 131.
The EPROMs 11-1 to 11-16 are selected, and data read / write control for the selected flash EEPROM is performed. In this case, the NAND interface 14 uses the flash EE corresponding to the memory chip number converted by the address conversion table 131.
To select PROM, first, flash EEPR
Chip selection signals CS1 to C to OM11-1 to 11-16
S16 is selectively supplied.

After that, the NAND interface 14
Generates a memory address converted by the address conversion table 131 as a start address, and sequentially reads the start address so that the read / write operation of data for the number of sectors sent from the host system 100 is executed. Count up.

In this case, the access to the flash EEPROM is performed by a command system in which the operation mode of the flash EEPROM is designated by a command. That is, the NAND interface 14 first specifies the operation mode (write mode, read mode, erase mode, verify mode, etc.) of the flash EEPROM, and then the address indicating the access position (address and write data in the write mode). Flash EEP
Supply to ROM. As described above, the flash EEPROM is provided with a data register of 256 + 8 bytes. Therefore, for example, in the light mode,
After the write data of 256 + 8 bytes is transferred to the register, the write operation for one page is automatically executed inside the flash EEPROM, so that the NAND interface 14 is released from the control of the write access.

Further, the NAND interface 14
Are two ECC calculation circuits (ECC-A, ECC-B)
141 and 142 are provided. These ECC arithmetic circuits 1
41 and 142 respectively calculate the ECC to be added to the write data in the write mode. In this case, E
The CC operation circuit 141 executes the ECC operation on the data strings belonging to the above-mentioned ECC operation A group,
The ECC operation circuit 142 executes an ECC operation on a data string belonging to the ECC operation B group. Each of these ECC arithmetic circuits 141 and 142 has a 4-bit width data arithmetic function.

Next, referring to FIG. 3, the control operation of the ECC operation using these ECC operation circuits 141 and 142 will be described. In FIG. 3, only the portion of the NAND interface 14 related to the ECC operation is extracted and shown.

The NAND interface 14 has an EC
In addition to the C arithmetic circuits 141 and 142, selectors 143 and 144 and a data output circuit 145 are provided as shown in the figure.

The control circuit 13 shown in FIG.
The write data for one sector stored in 5 is sequentially transferred to the NAND interface 14 in units of 8 bits. As described above, the write data for one sector has a data size (512 bytes) stored in two rows of the flash EEPROM 11, and is stored in the high-order bit position and the low-order bit position of the first row, respectively. The data strings 101a and 101b are stored, and the data strings 102a and 102b are stored in the upper bit and lower bit positions of the second row, respectively.

In the NAND interface 14, the write data is transferred to the data output circuit 145 and the selectors 143 and 144 in parallel. in this case,
The write data transferred to the selectors 143 and 144 is
Upper bit part (b7-b4) and lower bit part (b3-b)
0). As a result, the write data is divided into data strings 101a and 102a corresponding to the upper bit part and data strings 101b and 102b corresponding to the lower bit part along the length direction, that is, the row direction of the flash EEPROM 11.

The selector 143, for the data strings 101a and 101b stored in the first row, selects the data string 101a, that is, the upper bit data (b7-
b4) is selected and supplied to the ECC arithmetic circuit 141. Further, the selector 143, for the data strings 102a and 102b stored in the second row, the data string 102b, that is, the lower bit data (b3-b).
0) is selected and supplied to the ECC arithmetic circuit 141.

On the other hand, the selector 144 selects the data string 101b for the data strings 101a and 101b stored in the first row, that is, the lower bit data (b3-b0), and the ECC operation circuit 142 selects it.
Supply to. Further, the selector 144 selects the data string 102a, that is, the higher-order bit data (b7-b4) for the data strings 102a and 102b stored in the second row, and selects it from the ECC operation circuit 142.
Supply to.

By the selection operation by the selectors 143 and 144, the data strings stored in different bit positions in the first row and the second row are combined, and the ECC operation group composed of the data strings 101a and 102b. A and the data strings 101b and 102a
An ECC operation group B composed of is generated.

The ECC operation group A output from the selector 143 is supplied to the ECC operation circuit 141, and the ECC operation group B output from the selector 144 is ECC.
It is supplied to the arithmetic circuit 142.

The ECC operation circuit 141 is a 4-bit operation unit, and operates the ECC operation group A to calculate an error correction code (ECC-A) to be added to it. As the ECC calculation, it is preferable to use a redundant calculation capable of error correction as well as error detection, for example, CRC.

Similarly, the ECC operation circuit 142 is also a 4-bit operation unit, and operates the ECC operation group B to calculate an error correction code (ECC-B) to be added to it. The ECC arithmetic expression of the ECC arithmetic circuit 142 is E
It is the same as the CC arithmetic circuit 141.

Error correction codes (ECC-A, EC) calculated by the ECC arithmetic circuits 141 and 142, respectively.
CB) is supplied to the data output circuit 145 as an ECC having a total width of 8 bits. In this case, ECC-B is the upper 4 dots and ECC-B is the lower 4 bits ECC.

The data output circuit 145 is operated in parallel with the ECC operation circuits 141 and 142, and writes the write data for one sector in 8-bit units in the flash EEPROM 11.
Sequentially transferred to. Then, following the transfer of the write data, the data output circuit 145 causes the ECC operation circuit 14 to
The ECC obtained by 1, 142 is sequentially transferred to the flash EEPROM 11 in units of 8 bits.

In this way, the NAND interface 1
4, the data string divided into the upper bit part and the lower bit part is the ECC operation circuits 141 and 142.
The error correction codes ECC-A and ECC-B corresponding to the ECC operation groups A and B are calculated at the same time. Further, the ECC calculation process and the data output process by the data output circuit 105 are also performed in parallel. Therefore, two types of ECC operations can be executed without causing a delay in the data transfer rate to the flash EEPROM 11.

In FIG. 4, the sector data is the flash EE.
An example of grouping of the ECC operation groups when stored in four rows of the PROM 11 is shown. When the sector data is stored in four rows of the flash EEPROM 11, the data in each row is divided into four data strings each having a 2-bit width, as shown in the figure, and four rows and bit positions different from each other are divided. One ECC operation group is created by the data string.

Here, the data string 20 in the first line
1a, the data string 202c of the 2nd line, the data string 203b of the 3rd line, and the data string 204d of the 4th line constitute the ECC operation group A1, and similarly, the data strings 201b, 202d, 2
ECC calculation group A2 by 03a, 204c,
Data strings 201c, 202a, 203d, 20
4b shows an ECC operation group B1 and data strings 201d, 202b, 203c, 204a form an ECC operation group B2.

The error correction code (ECC-A1) calculated from the data of the ECC operation group A1 is the data string 204 of the fourth row belonging to the ECC operation group A1.
It is stored subsequent to d. Similarly, the error correction code (ECC) calculated from the data of the ECC calculation group A2
-A2) is stored subsequent to the data string 204c on the fourth row belonging to the ECC operation group A2, and the error correction code (ECC-B1) calculated from the data of the ECC operation group B1 belongs to the ECC operation group B1. It is stored after the data string 204b on the line
The error correction code (ECC-B2) calculated from the data of the CC operation group B2 is stored subsequent to the data string 204a in the fourth row belonging to the ECC operation group B2.

As described above, in FIG. 4, different ECC operations are executed between the same bit positions in the first to fourth rows where the sector data is stored. Therefore, even if the above-mentioned error mode occurs in the flash EEPROM 11, each ECC operation group includes only one defective cell.

For example, consider a case where a physical defect of the flash EEPROM 11 occurs at the position of bit 7 from the first row to the fourth row. In this case, the error occurrence point on the first line is the ECC operation group A1, the error occurrence point on the second line is the ECC operation group B1, the error occurrence point on the third line is the ECC operation group A2, and the error occurrence point on the fourth line is Since it belongs to the ECC operation group B2, each ECC operation group includes only one error.

Therefore, even when the sector data is stored in four rows, a normal simple EC operation is performed without using a complicated ECC arithmetic expression having a high data recovery capability.
A high data recovery capability can be realized by C calculation.

When four ECC operation groups are used as described above, it is desirable to provide four ECC operation circuits and four selectors respectively corresponding to the ECC operation groups. In this case, each ECC arithmetic circuit may have a 2-bit arithmetic function. The operations of these ECC operation circuit and selector are the same as in the case of FIG.

In FIG. 5, the sector data is the flash EE.
An example of grouping of ECC operation groups when stored in 8 rows of the PROM 11 is shown. When the sector data is stored in eight rows of the flash EEPROM 11, the data in each row is divided into eight data strings each having a 1-bit width as shown in the figure, and the row and bit positions are different from each other. One ECC operation group is created by the data string.

As a result, different ECC operations are executed between the same bit positions on the first to eighth rows, and the number of defective cells included in each ECC operation group can be limited to one or less.

When using eight ECC operation groups in this way, it is desirable to provide eight ECC operation circuits and eight selectors respectively corresponding to the ECC operation groups. In this case, each ECC arithmetic circuit may have a 1-bit arithmetic function.

Next, a second embodiment of the present invention will be described with reference to FIG. Here, in the case where the sector data is stored in the flash EEPROM 11 for two rows, the function for limiting the defective cells included in each ECC operation group to one or less is the flash EEPROM1.
1 is provided.

In this case, the NAND interface 14
In this case, since it is not necessary to switch the ECC calculation groups between the first line and the second line, as shown in the figure, EC
The C arithmetic circuit 141 is directly connected to the upper bit data (b7-b4) of the write data, and the ECC arithmetic circuit 142
Is directly connected to the lower bit data (b3-b0) of the write data.

The ECC calculation circuit 141 calculates the data strings 101a and 102a and calculates an error correction code (ECC-A) to be added to them. Similarly, E
The CC operation circuit 142 uses the data strings 101b, 1
02b is calculated, and the error correction code (ECC-B) to be added to them is calculated.

The data output circuit 145 is operated in parallel with the ECC operation circuits 141 and 142, and writes the write data for one sector in 8-bit units in the flash EEPROM 11.
Sequentially transferred to. Then, following the transfer of the write data, the data output circuit 145 causes the ECC operation circuit 14 to
The ECC obtained by 1, 142 is sequentially transferred to the flash EEPROM 11 in units of 8 bits.

In addition to the configuration of FIG. 1, the flash EEPROM 11 is provided with a data storage position changing circuit 113 as shown. In the write mode, the data storage position exchange circuit 113 transfers the data to be stored in the first row to the memory cell array 112 as it is, but the data to be stored in the second row is stored in the upper four positions. The bits and the lower 4 bits are exchanged for each column and transferred to the memory cell array 112.

As a result, the upper 4 bits (b7-
The data to be stored in b4) is the upper 4 bits (b3-
b0) and the lower 4 bits of the second row (b3-b
The data to be stored in 0) is the upper 4 bits (b7-b
4). Therefore, the flash EEPRO
It is possible to make the ECC operation groups different between the data stored in the same bit positions in the first and second rows of M11.

Further, the data storage position exchange circuit 113
Even in the read mode, for the data stored in the second row of the memory cell array, the high-order 4 bits and the low-order 4 bits are replaced for each column, and the data register 1
Transfer to 11.

As a result, the controller 20 has the ECC
Data read / write to the flash EEPROM 11 can be executed without being aware of the operation group replacement operation.

Incidentally, the data storage position exchange circuit 113
The replacement operation according to the above can be controlled by the value of the row address supplied from the NAND interface 14 to select the row of the memory cell array 112.

That is, when the sector data is stored in two rows, for example, assuming that the first row is designated by an even row address and the second row is designated by an odd row address, the lowest row address is stored. The replacement operation by the data storage position replacement circuit 113 may be executed only when the bit is “1”.

Further, even when sector data is stored in 4 or 8 rows, the data storage locations are switched in 2-bit width units or 1-bit width units so that they are stored in the same bit position. EC between existing data
It is possible to have different C operation groups.

Next, a third embodiment of the present invention will be described with reference to FIG. Here, instead of making the ECC operation groups different between the data stored in the same bit positions, the sector data format is improved to limit the error locations included in the ECC operation groups to 1 or less.

That is, the sector data format adopted in the third embodiment is the flash EE as shown in the figure.
The sector data stored in two rows of the PROM 11 is divided into blocks for each row, and an ECC is added to the data in each row. The sector data is divided into blocks by NAN
This can be realized by causing the ECC calculation circuit of the D interface 14 to calculate an ECC in a data unit of 256 bytes.

In this sector data format, since the ECC operation is completed for each row, even if an error mode occurs in which a defective cell occurs at the same bit position in a plurality of rows, the error location included in the ECC operation group is generated. Can be limited to 1 or less. In the sector data format as well, it is of course possible to store the sector ID at the beginning of the first line of each sector as in FIG.

[0084]

As described above in detail, according to the present invention, even if a defective cell is generated at the same bit position in each of a plurality of rows of the flash EEPROM, an error occurs in two or more places in the data to be ECC-calculated. Can be prevented, and high data recovery capability can be realized by a simple ECC calculation.

[Brief description of drawings]

FIG. 1 shows a relationship between a flash EEPROM used in a semiconductor disk device according to a first embodiment of the present invention and an ECC operation performed on sector data stored in two rows of the flash EEPROM. FIG.

FIG. 2 is a block diagram showing an example of a specific configuration of the semiconductor disk device of the same embodiment.

FIG. 3 shows N provided in the semiconductor disk device of the same embodiment.
The figure which shows an example of the concrete circuit structure of an AND interface.

FIG. 4 is a diagram showing a relationship between sector data stored in four rows in a flash EEPROM used in the semiconductor disk device of the embodiment and an ECC operation executed on the sector data.

FIG. 5 is a diagram showing a relationship between sector data stored in eight rows in a flash EEPROM used in the semiconductor disk device of the embodiment and an ECC operation executed on the sector data.

FIG. 6 is a diagram for explaining an ECC operation and a sector data storage position in a semiconductor disk device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a sector data format adopted in a semiconductor disk device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a sector data format in a conventional semiconductor disk device.

[Explanation of symbols]

10 ... Semiconductor Disk Device, 11, 11-1 to 11-1
6 ... Flash EEPROM, 12 ... Host interface, 13 ... Control circuit, 14 ... NAND interface, 15 ... Data buffer, 101a, 101b, 1
02a, 102b ... Data string, 141, 142
... ECC arithmetic circuit, 143, 144 ... Selector.

Claims (8)

[Claims] 1. A semiconductor disk device having a non-volatile semiconductor memory having a multi-bit structure, and accessing the non-volatile semiconductor memory in response to a disk access request from a host device, wherein the non-volatile semiconductor memory has a plurality of rows. The write data stored in this way is divided into multiple data strings containing different bits along the row direction, and it corresponds to multiple operation data groups each composed of multiple data strings containing different bits in different rows. Means for calculating a plurality of error correction codes, and adding the plurality of error correction codes to the data string of the last row of each of the plurality of operation data groups,
A semiconductor disk device comprising means for storing in the non-volatile semiconductor memory. 2. The error correction code calculation means calculates a plurality of error correction codes of input data, and a plurality of error correction code calculation circuits, and the data strings of the plurality of calculation data groups in the plurality of error correction code calculation circuits. 2. The semiconductor disk device according to claim 1, further comprising means for selectively supplying the divided data strings to the plurality of error correction code arithmetic circuits so that each of the divided data strings is input as input data. . 3. A semiconductor disk device having a non-volatile semiconductor memory having a multi-bit structure, wherein the non-volatile semiconductor memory is accessed in response to a disk access request from a host device. The write data stored in two rows of No. 2 are divided into first and second data strings including different bits along the row direction, and the first data string of the first row and the first data string are divided. A first operation data group consisting of a second data string of two rows, a second data string of the first row and a first data string of the second row. Means for calculating first and second error correction codes respectively corresponding to the second operation data group, and the first and second error correction codes for the second and third error correction codes. Added to each of the second data string and the first data string, the semiconductor disk device characterized by comprising a means for storing in the nonvolatile semiconductor memory. 4. The error correction code calculation means includes first and second error correction code calculation circuits for calculating an error correction code of input data, and the first and second error correction code calculation circuits include the first and second error correction code calculation circuits. The divided first and second data strings are alternately row by row so that the data strings of the first and second operation data groups are input as input data, respectively. 4. The semiconductor disk device according to claim 3, further comprising means for supplying the code operation circuit. 5. A data input / output terminal of n (≧ 2) bits,
And a semiconductor disk device having a non-volatile semiconductor memory including a memory cell array of xn-bit configuration and accessing the non-volatile semiconductor memory in response to a disk access request from a host device. The write data stored in the second two rows are stored in the upper n / n direction along the row direction.
First and second corresponding to 2 bits and lower n / 2 bits
A first operation data group composed of a first data string of the first row and a second data string of the second row, and a first operation data group of the first row. Means for calculating first and second error correction codes respectively corresponding to a second operation data group composed of two data strings and the first data string of the second row, and the first and second error correction codes. A semiconductor disk device, comprising means for storing a second error correction code in bit positions of lower n / 2 bits and upper n / 2 bits in the second row of the non-volatile semiconductor memory, respectively. 6. The error correction code calculation means includes first and second error correction code calculation circuits for calculating an error correction code of input data, respectively, and the first and second error correction code calculation circuits include the first and second error correction code calculation circuits. The divided first and second data strings are alternately row by row so that the data strings of the first and second operation data groups are input as input data, respectively. 6. The semiconductor disk device according to claim 5, further comprising means for supplying the code operation circuit. 7. A semiconductor disk device having a non-volatile semiconductor memory having a multi-bit configuration and accessing the non-volatile semiconductor memory in response to a disk access request from a host device, wherein the non-volatile semiconductor memory has a plurality of rows. The write data having a data size is divided into rows, means for calculating the data in each row and calculating an error correction code to be added thereto, and data in each row and the error correction code corresponding thereto are stored in the nonvolatile semiconductor memory. And a means for storing the same in the same row. 8. An n (≧ 2) -bit data input / output terminal,
And a semiconductor disk device having a non-volatile semiconductor memory including a memory cell array of xn-bit configuration and accessing the non-volatile semiconductor memory in response to a disk access request from a host device. The write data stored in the second two rows are first and second corresponding to upper n bits / 2 and lower n bits / 2 along the row direction.
And a means for calculating first and second error correction codes corresponding to the first and second data strings, respectively, and the first and second error correction codes for the first and second error correction codes. Means for adding to a second data string and transferring to the non-volatile semiconductor memory, wherein the non-volatile semiconductor memory comprises the first and second data strings in one of the first and second rows. Is stored in the storage locations corresponding to the lower n bits / 2 and the upper n bits / 2 of the row, respectively, and means for switching the storage locations of the first and second data strings is provided. Semiconductor disk device.