JP3181452B2 - Semiconductor disk drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor disk device, and more particularly, to a semiconductor disk device having a flash EEPROM which is a nonvolatile semiconductor memory which can be electrically erased in a batch.

[0002]

2. Description of the Related Art Many conventional information processing apparatuses such as workstations and personal computers use a magnetic disk device as a storage device. A magnetic disk device has advantages such as high recording reliability and low unit cost per bit, but has disadvantages such as a large device size and weakness against physical impact.

The operating principle of a magnetic disk drive is that data is magnetically written on or read from a rotating disk by running a magnetic head over the disk surface. Mechanically movable parts such as the rotating disk and the magnetic head may naturally malfunction or fail due to a physical shock applied to the apparatus. The need for such mechanically movable parts is an obstacle to reducing the size of the entire apparatus.

[0004] For this reason, the magnetic disk drive does not hinder the use of a desktop type computer fixed on a desk, but has the drawbacks of a portable small laptop computer and a notebook computer. Is a big problem.

Therefore, in recent years, attention has been focused on a semiconductor disk device which is small in size and resistant to physical impact. A semiconductor disk device is a flash EEPROM that is a nonvolatile semiconductor memory that can be electrically erased in a batch.
The OM is used as a secondary storage device of a personal computer or the like as in a conventional magnetic disk device or the like. Since this semiconductor disk device does not have a mechanically movable part like a magnetic disk device, malfunction and failure due to physical impact are unlikely to occur. Further, there is an advantage that the size of the device is reduced.

In such a semiconductor disk device, an ECC operation function is provided, and the flash EE
The ECC corresponding to the sector data written to the PROM is added. FIG. 8 shows a typical sector data format of a conventional semiconductor disk device having such an ECC operation function.

As shown in FIG. 8, sector data of 512 bytes is stored over two rows of the flash EEPROM 1, and the sector data is followed by an EC.
C is stored. Sector data is flash EEP
The number of rows stored in the ROM 1 is determined by the flash EE
Although determined by the physical size of the PROM 1, if the largest 16 Mbit flash EEPROM currently being developed is used, the 512-byte sector data is stored in the flash EEPROM as shown in the figure.
The data is stored over two rows of OM1.

[0008] In this case, the ECC operation is executed in the form of the first and second rows of the sector data, and the ECC calculated by the ECC operation is stored following the data of the second row.

However, in a conventional semiconductor disk device using such a sector format,
Considering the following error generation characteristics of a semiconductor memory such as a flash EEPROM, problems such as complicated ECC calculation and inability to execute error correction occur.

That is, in a semiconductor memory such as a flash EEPROM, there is an error mode in which a defect occurs simultaneously not only in a specific memory cell but also in a plurality of memory cells connected to the same bit line. This error mode is for example. This is caused by a defective bit line, a defective contact between the bit line and the cell, and the like.

When such an error mode occurs,
As shown in FIG. 8, the flash EEPROM 1
A defective cell is generated at the same bit position in each of a plurality of rows. In this case, in the conventional semiconductor disk device, two errors occur in the data to be subjected to the ECC operation as shown in the figure.

In general, in error correction using ECC, data can be recovered when there is one error, but it is difficult to correct errors in two or more locations. In order to cope with such an error, a complicated ECC operation formula having a high data recovery capability is required.

However, if the ECC arithmetic expression is complicated, the configuration of the semiconductor disk device is complicated, and the
Since a long time is required for the CC operation, a disadvantage that the data writing speed is reduced is caused.

[0014]

In a conventional semiconductor disk device, when a defective cell is generated at the same bit position in a plurality of rows of a flash EEPROM, a plurality of errors are included in data to be subjected to the ECC operation. Therefore, there is a disadvantage that data cannot be recovered by the normal ECC operation.

Further, a complicated ECC having a high data recovery capability
The use of the arithmetic expression causes a drawback that the configuration of the semiconductor disk device is complicated and that the ECC operation requires a lot of time, thereby deteriorating the performance in terms of data write and read speeds.

The present invention has been made in view of such a point, and even if a defective cell is generated at the same bit position in each of a plurality of rows of a flash EEPROM, two or more error data are included in the data to be subjected to the ECC operation. The object of the present invention is to provide a semiconductor disk device capable of realizing a high data recovery capability by a simple ECC operation without including the data.

[0017]

SUMMARY OF THE INVENTION The present invention provides
In a semiconductor disk device having a multi-bit nonvolatile semiconductor memory and accessing the nonvolatile semiconductor memory in response to a disk access request from a host device, data is stored over a plurality of rows of the nonvolatile semiconductor memory. Write data with different bits along the row direction
It is divided into a plurality of data strings each composed of position data , and the same bit positions of the plurality of rows are mutually
The plurality of rows so that they belong to different operation data groups
Data strings with different bit positions between
Operation data composed by combining
Means for calculating a plurality of error correction code corresponding to each data group, by adding a plurality of error correction code data string of the last line of each of the plurality of operation data group is stored in the nonvolatile semiconductor memory characterized by comprising a means.

In this semiconductor disk device, the operation of the error correction code for the write data is executed for each of a plurality of operation data groups. in this case,
The operation data group is configured by a plurality of data strings corresponding to different bit positions in a plurality of rows in which the write data is stored.

Therefore, even if a defective cell is generated at the same bit position in each of a plurality of rows of the nonvolatile semiconductor memory, only one defective cell is included in each operation data group for which an error correction code is to be operated. Become. Therefore, a high data recovery capability can be realized by a normal simple ECC calculation without using a complicated ECC calculation formula having a high data recovery capability.

Further, by providing a plurality of error correction code operation circuits of a number corresponding to the plurality of divided data strings, a plurality of data strings can be processed in parallel by the plurality of error correction code operation circuits. .
In this case, the plurality of error correction codes respectively corresponding to the plurality of operation data groups are calculated at the same time, so that the data writing speed to the nonvolatile semiconductor memory does not decrease.

Further, for example, when the write data is divided into n data strings in the row direction, the data width of each data string is 1/1 / the data width of the write data.
n. Therefore, the input data width of each error correction code operation circuit is 1 / n of the data width of the write data.
The circuit scale of each error correction code operation circuit can be small. Therefore, even if n error correction code operation circuits are provided, the number of gates required for the operation is not increased.

According to another aspect of the present invention, there is provided a semiconductor disk device having a nonvolatile semiconductor memory having a multi-bit configuration and accessing the nonvolatile semiconductor memory in response to a disk access request from a host device. Means for dividing write data having a data size over a plurality of rows for each row, calculating the data of each row and calculating an error correction code to be added to the data, and converting the data of each row and the corresponding error correction code into Means for storing data in the same row of the nonvolatile semiconductor memory.
The feature of.

In this semiconductor disk device, since the operation of the error correction code is terminated for each row, even if an error mode occurs in which a defective cell occurs at the same bit position in a plurality of rows, the operation of the error correction code is performed. It is possible to easily limit the number of defective cells included in each target operation data group to one or less.

Further, according to the present invention, a function for limiting the number of defective cells included in each ECC operation group to one or less is provided in the nonvolatile semiconductor memory, and the data storage position is automatically switched in the nonvolatile semiconductor memory. The third feature is that the configuration is made such that

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the relationship between a flash EEPROM used in a semiconductor disk device according to an embodiment of the present invention and an ECC operation performed on sector data stored over a plurality of rows of the flash EEPROM. Have been.

This flash EEPROM 11 has a size of × 8
16 Mbit NAND EEP with Bit Configuration
ROM, 8K rows × 264 columns of memory cell array 1
12 are provided. Also, in units of rows, that is, 25
In order to write / read data in 6 + 8 byte page units, a 256 + 8 bit data register 11
8 are provided. Data erasing is executed in units of 4K bytes + 128 bytes of erase blocks.

Now, it is assumed that sector data having a size of 512 bytes is written over two rows of the flash EEPROM 11, a first row and a second row. In this case, in the first row, the upper 4 bits (bit 7-4)
Is performed at the time of writing to the data string 101a corresponding to the data string 101a, and the ECC operation B is performed at the time of writing to the data string 101b of the lower 4 bits (bits 3-0).

On the other hand, in the second row, the data string 102a corresponding to the upper 4 bits (bits 7-4)
Is written, the ECC operation B is executed in a manner to continue the data string 101b in the first row, and the lower 4 bits (bit 3-0) data string 102b
With respect to, the ECC operation A is executed in the form of continuation to the data string 101a in the first row at the time of writing.

Further, in the second row, following the data string 102a, an error correction code (ECC-B) calculated by the ECC operation B is stored. The error correction code (ECC-B) corresponds to the data strings 101b and 102a, and is calculated including the content of the error correction code itself. Therefore, if there is an error anywhere in the data strings 101b and 102a and the error correction code (ECC-B), the error is corrected to the error correction code (ECC-B).
B).

Similarly, following the data string 102b, the error correction code (ECC-A) calculated by the ECC operation A is also stored. This error correction code (ECC-A) is composed of data strings 101a and 1
02b, and is calculated including the content of the error correction code itself. Therefore, if there is an error anywhere in the data strings 101a and 102b and the error correction code (ECC-A), the error can be corrected by the error correction code (ECC-A).

Here, the ECC operation A and the ECC operation B differ only in the data to be operated from each other, and the same operation expression itself can be used. Thus, in the semiconductor disk device of this embodiment,
Different ECC calculations are performed on data at the same bit position in the first row and the second row in which the sector data is stored. Therefore, even if the above-described error mode occurs in the flash EEPROM 11, only one defective cell is included in each ECC operation group.

For example, as shown in the figure, if a cell failure occurs in the second column of bit 6 from row 1 to row 16, the second column of bit 6 in the first and second rows, respectively, Will cause an error.

However, the error location on the first line is EC
The error portion in the second row belongs to the group of the ECC operation B, and the error portion in the second row belongs to the group of the C operation A. Therefore,
Only one defective cell is included in each ECC operation group, and high data recovery capability can be realized by ordinary simple ECC operation without using a complicated ECC operation expression having high data recovery capability.

Next, the configuration of the entire semiconductor disk device according to one embodiment of the present invention will be described with reference to FIG.
The semiconductor disk device 10 is used by being connected to a host system 100 such as a personal computer as an alternative to a hard disk device, and includes flash EEPROMs 11-1 to 11-16 and a controller 20.

Flash EEPROMs 11-1 to 11-
Numeral 16 is used as a recording medium of the semiconductor disk device 10.
It comprises an AND-type EEPROM 11.

These flash EEPROMs 11-1 to 11-1
11-16 are connected to the controller 20 via a common I / O bus and control signal lines. Further, the controller 20 and the flash EEPROMs 11-1 to 11-11
-16, the chip select signals (CS1 to CS
16) Lines are provided independently for each chip.

The flash EEPROMs 11-1 to 11-1
In 11-16, as described above, data writing is performed in units of pages of 256 bytes + 8 bytes,
Data erasure is executed in units of 4 Kbytes + 128 bytes.

The controller 20 is realized by one LSI, and the LSI chip includes a host interface 12, a control circuit 13, an NA
ND interface 14 and data buffer 15
Are integratedly formed.

The host interface 12 communicates with the host system 100 via a pin arrangement conforming to the IDE interface. The host interface 12 includes various interface register groups (sector number register, sector count register, data register, cylinder register, drive / head register, command register, status register) for communication with the host system 100. I have. These registers can be read / written by the host system 100.

The control circuit 13 includes an MPU and a local memory in which a firmware program for controlling the operation of the MPU is stored. In response to a disk access request supplied from the host system 100 via the host interface 12, the control circuit 13 Flash EEPROM 11
-1 to 11-16 are access controlled.

That is, the MPU of the control circuit 13 reads various commands and parameters set in the register group of the host interface 12 and controls access to the flash EEPROMs 11-1 to 11-16 according to the contents. In this case, the MPU of the control circuit 13 performs the address conversion from the logical address to the physical address with reference to the address conversion table 131.

The address conversion table 131 stores the logical address from the host system 100 and the flash EEP.
Address conversion information indicating a correspondence with physical addresses for accessing the ROMs 11-1 to 11-16 is defined. Here, the logical address is an address for disk access, and is determined by a cylinder number, a head number, and a sector number. The physical address is an address for selectively accessing the flash EEPROMs 11-1 to 11-16, and is determined by a chip number and a memory address.

The address conversion table 131 is stored in one of the flash EEPROMs 11-1 to 11-16, and is read into the control circuit 13 when the power is turned on. The NAND interface 14 outputs the flash E according to the conversion result by the address conversion table 131.
The selection of the EPROMs 11-1 to 11-16 and the data read / write control for the selected flash EEPROM are performed. In this case, the NAND interface 14 supplies the flash EE corresponding to the memory chip number converted by the address conversion table 131.
To select a PROM, first, flash EEPROM
OM11-1 to OM-11 to chip select signals CS1 to C
S16 is selectively supplied.

Thereafter, the NAND interface 14
Is generated with the memory address converted by the address conversion table 131 as the head address, and the head address is sequentially changed so that the read / write operation of the data of the number of sectors transmitted from the host system 100 is executed. Count up.

In this case, access to the flash EEPROM is performed by a command method in which an operation mode of the flash EEPROM is specified by a command. That is, the NAND interface 14 first specifies an operation mode (write mode, read mode, erase mode, verify mode, etc.) of the flash EEPROM, and then addresses indicating an access position (address and write data in the write mode). Flash EEP
Supply to ROM. The flash EEPROM has a data register of 256 + 8 bytes as described above. For this reason, for example, in the light mode,
After the 256 + 8-byte write data is transferred to the register, the write operation for one page is automatically executed inside the flash EEPROM, so that the NAND interface 14 is released from the control of the write access.

Further, the NAND interface 14
Means two ECC operation circuits (ECC-A, ECC-B)
141 and 142 are provided. These ECC operation circuits 1
41 and 142 calculate the ECC to be added to the write data in the write mode. In this case, E
The CC operation circuit 141 performs an ECC operation on the data strings belonging to the ECC operation A group,
The ECC operation circuit 142 performs an ECC operation on the data strings belonging to the ECC operation B group. Each of these ECC operation circuits 141 and 142 has a data operation function of 4-bit width.

Next, a control operation of the ECC operation using the ECC operation circuits 141 and 142 will be described with reference to FIG. FIG. 3 shows only a portion related to the ECC operation in the NAND interface 14.

The NAND interface 14 has an EC
In addition to the C operation circuits 141 and 142, selectors 143 and 144 and a data output circuit 145 are provided as shown.

The control circuit 13 shown in FIG.
5 is sequentially transferred to the NAND interface 14 in 8-bit units. As described above, the write data for one sector has a data size (512 bytes) that is stored over two rows of the flash EEPROM 11, and the upper bit and the lower bit position of the first row are respectively located. It is composed of data strings 101a and 101b to be stored, and data strings 102a and 102b to be stored at the upper and lower bit positions of the second row, respectively.

In the NAND interface 14, the write data is transferred to the data output circuit 145 and the selectors 143 and 144 in parallel. in this case,
The write data transferred to the selectors 143 and 144 is
Upper bit part (b7-b4) and lower bit part (b3-b)
0). As a result, the write data is divided into data strings 101a and 102a corresponding to the upper bit portion and data strings 101b and 102b corresponding to the lower bit portion along the length direction, that is, the row direction of the flash EEPROM 11.

For the data strings 101a and 101b stored in the first row, the selector 143 sets the data string 101a, that is, the upper bit data (b7-b).
b4) is selected and supplied to the ECC operation circuit 141. Further, the selector 143 determines that the data strings 102a and 102b stored in the second row are the data strings 102b, that is, the lower bit data (b3-b).
0) and supplies it to the ECC operation circuit 141.

On the other hand, the selector 144 selects the data string 101b, that is, the lower bit data (b3-b0) for the data strings 101a and 101b stored in the first row, and outputs the selected data string to the ECC operation circuit 142.
To supply. The selector 144 selects the data string 102a, that is, the upper bit data (b7-b4) for the data strings 102a and 102b stored in the second row, and outputs the selected data string to the ECC operation circuit 142.
To supply.

By such a selection operation by the selectors 143 and 144, the data strings stored at different bit positions in the first row and the second row are connected to each other, and the ECC operation group composed of the data strings 101a and 102b is formed. A and data strings 101b and 102a
Is generated.

The ECC operation group A output from the selector 143 is supplied to the ECC operation circuit 141, and the ECC operation group B output from the selector 144 is the ECC operation group.
It is supplied to the arithmetic circuit 142.

The ECC operation circuit 141 is a 4-bit operation unit, and operates the ECC operation group A to calculate an error correction code (ECC-A) to be added to the ECC operation group. As the ECC operation, it is preferable to use a redundant operation that can perform not only error detection but also error correction, for example, CRC.

Similarly, the ECC operation circuit 142 is also a 4-bit operation unit, and operates the ECC operation group B to calculate an error correction code (ECC-B) to be added to it. The ECC operation expression of the ECC operation circuit 142 is E
This is the same as the CC operation circuit 141.

The error correction codes (ECC-A, ECC) calculated by the ECC operation circuits 141 and 142, respectively.
CB) is supplied to the data output circuit 145 as an ECC having a total width of 8 bits. In this case, ECC-B is the upper 4 dots, and ECC-B is the lower 4 bits.

The data output circuit 145 operates in parallel with the ECC operation circuits 141 and 142, and writes write data for one sector in units of 8 bits in the flash EEPROM 11.
Sequentially. Then, following the transfer of the write data, the data output circuit 145 outputs the ECC operation circuit 14
The ECCs obtained by the steps 1 and 142 are sequentially transferred to the flash EEPROM 11 in 8-bit units.

As described above, the NAND interface 1
4, the data string divided into the upper bit part and the lower bit part is divided into ECC operation circuits 141 and 142.
And the error correction codes ECC-A and ECC-B respectively corresponding to the ECC operation groups A and B are simultaneously calculated. Further, the processing of these ECC calculations and the data output processing by the data output circuit 105 are performed in parallel. Therefore, two types of ECC calculations can be performed without causing a delay in the data transfer speed to the flash EEPROM 11.

FIG. 4 shows that the sector data is flash EE
An example of grouping of ECC calculation groups when the data is stored over four rows of the PROM 11 is shown. When the sector data is stored over four rows of the flash EEPROM 11, the data in each row is divided into four data strings each having a 2-bit width as shown in FIG. One ECC operation group is created by the data string.

Here, the data string 20 in the first row
The ECC operation group A1 is composed of the data string 1a, the data string 202c in the second row, the data string 203b in the third row, and the data string 204d in the fourth row. Similarly, the data strings 201b, 202d, and 2
The ECC operation group A2 is defined by 03a and 204c.
Data strings 201c, 202a, 203d, 20
4b shows a case where the ECC operation group B1 is constituted by the data strings 201d, 202b, 203c and 204a, and the ECC operation group B2 is constituted by the data strings 201d, 202b, 203c and 204a.

The error correction code (ECC-A1) calculated from the data of the ECC operation group A1 is the data string 204 of the fourth row belonging to the ECC operation group A1.
It is stored following d. Similarly, the error correction code (ECC) calculated from the data of the ECC operation group A2
-A2) is stored subsequent to the data string 204c of the fourth row belonging to the ECC operation group A2, and the error correction code (ECC-B1) calculated from the data of the ECC operation group B1 belongs to the ECC operation group B1. It is stored after the data string 204b of the row,
The error correction code (ECC-B2) calculated from the data of the CC operation group B2 is stored following the data string 204a of the fourth row belonging to the ECC operation group B2.

As described above, in FIG. 4, different ECC operations are performed between the same bit positions in the first to fourth rows in which sector data is stored. Therefore, even if the above-described error mode occurs in the flash EEPROM 11, only one defective cell is included in each ECC operation group.

For example, consider a case where a physical defect of the flash EEPROM 11 has occurred at the position of bit 7 from the first line to the fourth line. In this case, the error occurrence location on the first line is the ECC operation group A1, the error occurrence location on the second row is the ECC operation group B1, the error occurrence location on the third row is the ECC operation group A2, and the error occurrence location on the fourth row is Since it belongs to the ECC calculation group B2, each ECC calculation group contains only one error.

Therefore, even when the sector data is stored over four rows, a normal simple EC calculation is performed without using a complicated ECC arithmetic expression having a high data recovery capability.
High data recovery capability can be realized by the C operation.

When four ECC operation groups are used as described above, it is preferable to provide four ECC operation circuits and four selectors respectively corresponding to the ECC operation groups. In this case, each ECC operation circuit may have a 2-bit operation function. The operations of the ECC operation circuit and the selector are the same as those in FIG.

FIG. 5 shows that the sector data is flash EE
An example of grouping of ECC operation groups when the data is stored over eight rows of the PROM 11 is shown. When the sector data is stored over eight rows of the flash EEPROM 11, the data in each row is divided into eight data strings each having a one-bit width as shown in the figure, and eight data strings having different rows and bit positions are provided. One ECC operation group is created by the data string.

As a result, different ECC operations are performed between the same bit positions in the first to eighth rows, and the number of defective cells included in each ECC operation group can be limited to one or less.

When eight ECC operation groups are used as described above, it is desirable to provide eight ECC operation circuits and eight selectors respectively corresponding to the ECC operation groups. In this case, each of the ECC operation circuits may have a 1-bit operation function.

Next, a second embodiment of the present invention will be described with reference to FIG. Here, when sector data is stored over two rows in the flash EEPROM 11, a function for limiting the number of defective cells included in each ECC operation group to one or less is provided by the flash EEPROM 1.
1 is provided.

In this case, the NAND interface 14
In, there is no need to switch the ECC operation groups between the first and second rows.
The C operation circuit 141 is directly connected to the upper bit data (b7-b4) of the write data, and the ECC operation circuit 142
Are directly connected to the lower bit data (b3-b0) of the write data.

The ECC operation circuit 141 operates the data strings 101a and 102a and calculates an error correction code (ECC-A) to be added to them. Similarly, E
The CC operation circuit 142 outputs the data strings 101b, 1
02b, and an error correction code (ECC-B) to be added to them is calculated.

The data output circuit 145 operates in parallel with the ECC operation circuits 141 and 142, and writes write data for one sector in units of 8 bits in the flash EEPROM 11.
Sequentially. Then, following the transfer of the write data, the data output circuit 145 outputs the ECC operation circuit 14
The ECCs obtained by the steps 1 and 142 are sequentially transferred to the flash EEPROM 11 in 8-bit units.

The flash EEPROM 11 is provided with a data storage position switching circuit 113 in addition to the configuration shown in FIG. In the write mode, the data storage position exchange circuit 113 transfers the data to be stored in the first row to the memory cell array 112 as it is, but transfers the data to be stored in the second row to the upper four The bits and the lower 4 bits are exchanged for each column and transferred to the memory cell array 112.

As a result, the upper 4 bits (b7-
The data to be stored in b4) is the upper 4 bits (b3-
b0), and the lower 4 bits (b3-b) of the second row
0) is the upper 4 bits (b7-b).
4). Therefore, Flash EEPRO
It is possible to make the ECC operation groups different between the data stored in the same bit position in the first and second rows of M11.

The data storage position switching circuit 113
In the read mode, the data stored in the second row of the memory cell array is replaced with the upper 4 bits and the lower 4 bits for each column, and the data register 1
Transfer to 11.

As a result, the controller 20 sets the ECC
Data read / write to the flash EEPROM 11 can be executed without being aware of the operation of exchanging operation groups.

The data storage position switching circuit 113
Can be controlled by the value of the row address supplied from the NAND interface 14 to select the row of the memory cell array 112.

That is, when the sector data is stored over two rows, for example, assuming that the first row is specified by an even row address and the second row is specified by an odd row address, the lowest row address is specified. Only when the bit is “1”, the switching operation by the data storage position switching circuit 113 may be executed.

Even when the sector data is stored over four or eight rows, the data is stored at the same bit position by exchanging the data storage position in units of two bits or one bit. EC between existing data
It is possible to make the C operation groups different.

Next, a third embodiment of the present invention will be described with reference to FIG. Here, the error locations included in the ECC operation group are limited to one or less by improving the sector data format instead of making the ECC operation group different between data stored in the same bit position.

That is, the sector data format adopted in the third embodiment is, as shown in FIG.
The sector data stored over two rows of the PROM 11 is divided into blocks for each row, and ECC is added to the data of each row. The block division of the sector data is NAN
This can be realized by causing the ECC calculation circuit of the D interface 14 to calculate the ECC in 256-byte data units.

In this sector data format, since the ECC operation is terminated for each row, even if an error mode in which a defective cell occurs at the same bit position in a plurality of rows occurs, the error location included in the ECC operation group Can be always limited to 1 or less. In the sector data format, it is of course possible to store the sector ID at the beginning of the first row of each sector as in FIG.

[0084]

As described above in detail, according to the present invention, even if a defective cell is generated at the same bit position in each of a plurality of rows of a flash EEPROM, two or more errors occur in the data to be subjected to the ECC operation. Can be prevented, and a high data recovery ability can be realized by a simple ECC operation.

[Brief description of the drawings]

FIG. 1 shows a relationship between a flash EEPROM used in a semiconductor disk device according to a first embodiment of the present invention and an ECC operation performed on sector data stored over two rows of the flash EEPROM. FIG.

FIG. 2 is an exemplary block diagram showing an example of a specific configuration of the semiconductor disk device of the embodiment;

FIG. 3 shows N provided in the semiconductor disk device of the embodiment.
FIG. 3 is a diagram illustrating an example of a specific circuit configuration of an AND interface.

FIG. 4 is an exemplary view showing a relationship between sector data stored over four rows in a flash EEPROM used in the semiconductor disk device of the embodiment and ECC operations performed on the sector data;

FIG. 5 is an exemplary view showing a relationship between sector data stored over eight rows in a flash EEPROM used in the semiconductor disk device of the embodiment and ECC operations performed on the sector data;

FIG. 6 is a diagram for explaining an ECC calculation operation and a storage position of sector data in the semiconductor disk device according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a sector data format used in a semiconductor disk device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a sector data format in a conventional semiconductor disk device.

[Explanation of symbols]

10 semiconductor disk device, 11, 11-1 to 11-1
6 flash EEPROM, 12 host interface, 13 control circuit, 14 NAND interface, 15 data buffer, 101a, 101b, 1
02a, 102b ... data strings, 141, 142
... ECC operation circuit, 143, 144.

Claims (8)

(57) [Claims] 1. A semiconductor disk device having a multi-bit nonvolatile semiconductor memory and accessing said nonvolatile semiconductor memory in response to a disk access request from a host device, comprising: a plurality of rows of said nonvolatile semiconductor memory; The write data to be stored is stored in different bit positions along the row direction.
The data is divided into a plurality of data strings each composed of data, and the same bit positions of the plurality of rows are different from each other.
Between the rows so that they belong to
To combine data strings with different bit positions
Multiple operation data tags configured by combining
Means for calculating a plurality of error correction codes corresponding to each of the loops; and adding the plurality of error correction codes to the data string of the last row of each of the plurality of operation data groups.
Means for storing data in the nonvolatile semiconductor memory. 2. The error correction code calculation means includes: a plurality of error correction code calculation circuits each calculating an error correction code of input data; and a data string of the plurality of calculation data groups in the plurality of error correction code calculation circuits. 2. The semiconductor disk device according to claim 1, further comprising: a unit for selectively supplying the divided data strings to the plurality of error correction code operation circuits so that each of the divided data strings is input as input data. . 3. A semiconductor disk device having a multi-bit nonvolatile semiconductor memory and accessing said nonvolatile semiconductor memory in response to a disk access request from a host device, wherein said first and second nonvolatile semiconductor memories are the write data to be stored over the two rows of 2 along the row direction is divided into respective first and second data strings composed of different bit position data with each other, and the first Oyo
And operation data in which the same bit position in the second two rows is different from each other.
Of the first and second two rows to belong to the
Data strings with different bit positions between
First and second configured by combining
First and second corresponding to each of the operation data groups
Error means for calculating a correction codes, the first and the first and second error correction code
Data of the second row of each of the second operation data groups
Means for storing in the nonvolatile semiconductor memory in addition to a string . 4. The error correction code calculation means includes: a first and a second error correction code calculation circuit for calculating an error correction code of input data; and a first and a second error correction code calculation circuit. The divided first and second data strings are alternately arranged row by row so that the data strings of the first and second operation data groups are respectively input as input data. 4. The semiconductor disk device according to claim 3, further comprising means for supplying the code operation circuit. 5. An n (≧ 2) bit data input / output terminal,
And a non-volatile semiconductor memory including a memory cell array having a × n bit configuration, wherein the non-volatile semiconductor memory accesses the non-volatile semiconductor memory in response to a disk access request from a host device. The write data stored over the second two rows is written into the upper n /
Divided into first and second data strings respectively corresponding to the 2-bit portion and the lower n / 2 bit portion, and the second
The same bit positions in the first and second two rows are different from each other.
The first and second data to belong to the arithmetic data group.
Data strings with different bit positions between two rows
The first and the first configured by combining
Means for calculating a first and second error-correcting code corresponding to the respective second operation data groups, the first and the first and second error-correcting code
Data of the second row of each of the second operation data groups
Means for storing in the nonvolatile semiconductor memory in addition to a string . 6. The error correction code calculation means includes: a first and a second error correction code calculation circuit for calculating an error correction code of input data; and a first and a second error correction code calculation circuit. The divided first and second data strings are alternately arranged row by row so that the data strings of the first and second operation data groups are respectively input as input data. 6. The semiconductor disk device according to claim 5, further comprising: means for supplying a code operation circuit. 7. A data input / output terminal of n (≧ 2) bits,
And a non-volatile semiconductor memory including a memory cell array having a × n bit configuration, wherein the non-volatile semiconductor memory accesses the non-volatile semiconductor memory in response to a disk access request from a host device. The write data stored over the second two rows is written into the upper n /
Dividing into first and second data strings respectively corresponding to a 2-bit part and a lower n / 2-bit part , and calculating first and second error correction codes respectively corresponding to the first and second data strings Means for adding the first and second error correction codes to the first and second data strings and transferring the same to the nonvolatile semiconductor memory. The nonvolatile semiconductor memory comprises: The first and second data strings in one of the first and second rows are respectively lower n / 2 of the row.
A semiconductor disk device comprising: means for switching the storage positions of first and second data strings so as to be stored in storage positions corresponding to a bit portion and an upper n / 2 bit portion . 8. Data is stored in a multi-bit semiconductor memory.
In a semiconductor memory device for storing, write data is written over a plurality of rows of the semiconductor memory.
When writing, the write data are different from each other in the row direction.
Data consisting of different bit position data
Data strings, and the same bits in the plurality of rows.
So that the positions belong to different operation data groups
A data stream having bit positions different from each other in the plurality of rows.
Multiple composed by combining rings
Error corrections corresponding to each of the calculated data groups
Means for calculating a positive code, and a plurality of error correction codes,
To the data string of the last line of each
Means for storing the data in the nonvolatile semiconductor memory.
A semiconductor memory device characterized by the above-mentioned.